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revision date: dec. 13, 2005 32 sh7780 hardware manual renesas 32-bit risc microcomputer superh tm risc engine family sh7780 series r8a77800a rev.1.00 rej09b0158-0100
rev.1.00 dec. 13, 2005 page ii of l
rev.1.00 dec. 13, 2005 page iii of l 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev.1.00 dec. 13, 2005 page iv of l general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed. 5. reading from/writing reserved bit of each register note: treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. the bit is always read as 0. the write value should be 0 or one, which has been read immediately before writing. writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned.
rev.1.00 dec. 13, 2005 page v of l configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. electrical characteristics 8. appendix 9. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 10. index
rev.1.00 dec. 13, 2005 page vi of l preface this lsi is a risc (reduced instruction set co mputer) microcomputer which includes a renesas technology-original risc cpu as its core, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using this lsi in the design of application systems. user s of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of this lsi to the above users. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. rules: bit order: the msb is on the left and the lsb is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx
rev.1.00 dec. 13, 2005 page vii of l abbreviations alu arithmetic logic unit asid address space identifier bga ball grid array cmt compare match timer (timer/counter) cpg clock pulse generator cpu central processing unit ddr double data rate ddrif ddr-sdram interface dma direct memory access dmac direct memory access controller fifo first-in first-out flctl nand flash memory controller fpu floating-point unit hac audio codec hspi serial protocol interface h-udi user debugging interface intc interrupt controller jtag joint test action group lbsc local bus state controller lram l memory lru least recently used lsb least significant bit
rev.1.00 dec. 13, 2005 page viii of l mmcif multimedia card interface mmu memory management unit msb most significant bit pc program counter pci peripheral component interconnect pcic pci (local bus) controller risc reduced instruction set computer rtc realtime clock scif serial communication interface with fifo siof serial interface with fifo ssi serial sound interface tap test access port tlb translation lookaside buffer tmu timer unit uart universal asynchronou s receiver/transmitter ubc user break controller wdt watchdog timer
rev.1.00 dec. 13, 2005 page ix of l contents section 1 overview................................................................................................1 1.1 sh7780 f eatures................................................................................................................ .... 1 1.2 block diagram .................................................................................................................. ..... 9 1.3 pin arrangement ................................................................................................................ .. 10 1.4 pin functions .................................................................................................................. ..... 11 1.5 memory addr ess map ......................................................................................................... 27 1.6 superhyway bus ................................................................................................................. 30 1.7 superhyway memory (superhywa y ram)........................................................................ 31 section 2 programming model ............................................................................33 2.1 data formats................................................................................................................... ..... 33 2.2 register de scriptions .......................................................................................................... .34 2.2.1 privileged mode and banks .................................................................................... 34 2.2.2 general registers.................................................................................................... 37 2.2.3 floating-point registers.......................................................................................... 38 2.2.4 control registers .................................................................................................... 40 2.2.5 system regi sters..................................................................................................... 42 2.3 memory-mapped registers.................................................................................................. 46 2.4 data formats in registers .................................................................................................... 47 2.5 data formats in memory ..................................................................................................... 48 2.6 processing states.............................................................................................................. .... 49 2.7 usage note..................................................................................................................... ...... 50 2.7.1 notes on self-mod ified co des.................................................................................. 50 section 3 instruction set ......................................................................................51 3.1 execution envi ronment ....................................................................................................... 51 3.2 addressing modes ............................................................................................................... 53 3.3 instruction set ................................................................................................................ ...... 57 section 4 pipelining .............................................................................................73 4.1 pipelines...................................................................................................................... ......... 73 4.2 parallel-ex ecutab ility ......................................................................................................... .. 84 4.3 issue rates and ex ecution cy cles........................................................................................ 87 section 5 exception handling .............................................................................97 5.1 summary of exception handling......................................................................................... 97
rev.1.00 dec. 13, 2005 page x of l 5.2 register de scriptions.......................................................................................................... .97 5.2.1 trapa exception re gister (tra) ........................................................................ 98 5.2.2 exception event regi ster (expevt)..................................................................... 99 5.2.3 interrupt event regi ster (intevt)...................................................................... 100 5.3 exception handlin g functi ons........................................................................................... 101 5.3.1 exception hand ling flow ..................................................................................... 101 5.3.2 exception handling vect or addresses ................................................................. 101 5.4 exception types an d priorities .......................................................................................... 102 5.5 exceptio n fl ow ................................................................................................................. .104 5.5.1 exception flow..................................................................................................... 104 5.5.2 exception source acceptance............................................................................... 106 5.5.3 exception requests and bl bit ............................................................................ 107 5.5.4 return from excep tion handling.......................................................................... 107 5.6 description of exceptions.................................................................................................. 108 5.6.1 resets .................................................................................................................... 108 5.6.2 general exceptions............................................................................................... 110 5.6.3 interrupts............................................................................................................... 124 5.6.4 priority order with mu ltiple exceptions .............................................................. 125 5.7 usage notes .................................................................................................................... ... 127 section 6 floating-point unit (fpu)................................................................. 129 6.1 features....................................................................................................................... ....... 129 6.2 data formats................................................................................................................... ... 130 6.2.1 floating-point format........................................................................................... 130 6.2.2 non-numbers (nan) ............................................................................................ 133 6.2.3 denormalized nu mbers ........................................................................................ 134 6.3 register desc riptions......................................................................................................... 1 35 6.3.1 floating-point re gisters ....................................................................................... 135 6.3.2 floating-point status/contro l register (fpscr) ................................................. 137 6.3.3 floating-point communicati on register (fpul) ................................................. 140 6.4 rounding....................................................................................................................... ..... 141 6.5 floating-point ex ceptions.................................................................................................. 142 6.5.1 general fpu disable exceptions and slot fpu disable exceptions ................... 142 6.5.2 fpu exception sources ........................................................................................ 142 6.5.3 fpu exception ha ndling ...................................................................................... 142 6.6 graphics support functions............................................................................................... 144 6.6.1 geometric operation instructio ns......................................................................... 144 6.6.2 pair single-precision data transfer...................................................................... 145
rev.1.00 dec. 13, 2005 page xi of l section 7 memory management unit (mmu) ..................................................147 7.1 overview of mmu ............................................................................................................ 147 7.1.1 address sp aces ..................................................................................................... 149 7.2 register desc riptions ......................................................................................................... 1 56 7.2.1 page table entry high register (pteh) .............................................................. 157 7.2.2 page table entry low register (ptel) ............................................................... 158 7.2.3 translation table base register (ttb) ................................................................ 159 7.2.4 tlb exception address register (t ea) .............................................................. 159 7.2.5 mmu control regist er (mmucr) ...................................................................... 160 7.2.6 physical address space cont rol register (pascr)............................................. 164 7.2.7 instruction re-fetch inhibit control register (irmcr) ...................................... 165 7.3 tlb functions .................................................................................................................. .167 7.3.1 unified tlb (utlb) co nfiguration .................................................................... 167 7.3.2 instruction tlb (itlb) configura tion................................................................. 170 7.3.3 address transla tion met hod................................................................................. 171 7.4 mmu functions................................................................................................................. 1 73 7.4.1 mmu hardware management .............................................................................. 173 7.4.2 mmu software management ............................................................................... 173 7.4.3 mmu instruction (ldtlb).................................................................................. 174 7.4.4 hardware itlb mi ss handling ............................................................................ 175 7.4.5 avoiding synonym problems ............................................................................... 176 7.5 mmu excepti ons............................................................................................................... 17 7 7.5.1 instruction tlb multiple hit exception............................................................... 177 7.5.2 instruction tlb mi ss exception........................................................................... 178 7.5.3 instruction tlb protection violation exception .................................................. 179 7.5.4 data tlb multiple h it exceptio n ........................................................................ 180 7.5.5 data tlb miss exception .................................................................................... 180 7.5.6 data tlb protection viol ation exception............................................................ 181 7.5.7 initial page write exception................................................................................. 182 7.6 memory-mapped tlb co nfiguration................................................................................ 183 7.6.1 itlb address array ............................................................................................. 184 7.6.2 itlb data array................................................................................................... 185 7.6.3 utlb address array............................................................................................ 186 7.6.4 utlb data array ................................................................................................. 187 7.7 32-bit address ex tended mode......................................................................................... 188 7.7.1 overview of 32-bit addr ess extended mode....................................................... 189 7.7.2 transition to 32-bit addr ess extended mode ...................................................... 189 7.7.3 privileged space mapping buffer (pmb) config uration ..................................... 189 7.7.4 pmb functio n....................................................................................................... 191
rev.1.00 dec. 13, 2005 page xii of l 7.7.5 memory-mapped pmb co nfiguration.................................................................. 192 7.7.6 notes on using 32-bit addr ess extended mode .................................................. 194 section 8 caches................................................................................................ 197 8.1 features....................................................................................................................... ....... 197 8.2 register desc riptions......................................................................................................... 2 00 8.2.1 cache control regi ster (ccr) ............................................................................. 201 8.2.2 queue address control re gister 0 (qacr0)....................................................... 203 8.2.3 queue address control re gister 1 (qacr1)....................................................... 204 8.2.4 on-chip memory control register (r amcr) .................................................... 205 8.3 operand cache op eration.................................................................................................. 207 8.3.1 read opera tion ..................................................................................................... 207 8.3.2 prefetch operation ................................................................................................ 208 8.3.3 write operation .................................................................................................... 209 8.3.4 write-back buffer ................................................................................................ 211 8.3.5 write-through buffer........................................................................................... 211 8.3.6 oc two-way mode ............................................................................................. 211 8.4 instruction cache operation .............................................................................................. 212 8.4.1 read opera tion ..................................................................................................... 212 8.4.2 prefetch operation ................................................................................................ 213 8.4.3 ic two-way mode............................................................................................... 213 8.5 cache operation in struction .............................................................................................. 214 8.5.1 coherency between cache an d external memory ................................................ 214 8.5.2 prefetch operation ................................................................................................ 215 8.6 memory-mapped cache configura tion ............................................................................. 216 8.6.1 ic address array.................................................................................................. 217 8.6.2 ic data array ....................................................................................................... 219 8.6.3 oc address array ................................................................................................ 220 8.6.4 oc data array...................................................................................................... 222 8.7 store queues ................................................................................................................... ... 223 8.7.1 sq configuration.................................................................................................. 223 8.7.2 writing to sq........................................................................................................ 223 8.7.3 transfer to exte rnal memory ............................................................................... 224 8.7.4 determination of sq access exception................................................................ 225 8.7.5 reading from sq .................................................................................................. 225 8.8 notes on using 32-bit addr ess extended mode ............................................................... 226 section 9 l memory.......................................................................................... 227 9.1 features....................................................................................................................... ....... 227 9.2 register desc riptions......................................................................................................... 2 28
rev.1.00 dec. 13, 2005 page xiii of l 9.2.1 on-chip memory control register (r amcr) .................................................... 229 9.2.2 l memory transfer source ad dress register 0 (lsa0) ...................................... 230 9.2.3 l memory transfer source ad dress register 1 (lsa1) ...................................... 232 9.2.4 l memory transfer destination address register 0 (lda0) .............................. 234 9.2.5 l memory transfer destination address register 1 (lda1) .............................. 236 9.3 operation ...................................................................................................................... ..... 238 9.3.1 access from the cp u and fpu............................................................................. 238 9.3.2 access from the superhyway bus master module .............................................. 238 9.3.3 block transfer ...................................................................................................... 238 9.4 l memory protectiv e functions ........................................................................................ 240 9.5 usage notes .................................................................................................................... ... 241 9.5.1 page conflict ........................................................................................................ 241 9.5.2 l memory coherency ........................................................................................... 241 9.5.3 sleep mode ........................................................................................................... 241 9.6 note on using 32-bit ad dress extended mode................................................................. 241 section 10 interrupt controller (intc) .............................................................243 10.1 features....................................................................................................................... ....... 243 10.1.1 interrupt method ................................................................................................... 245 10.1.2 interrupt types in intc ....................................................................................... 246 10.2 input/output pins .............................................................................................................. .250 10.3 register desc riptions ......................................................................................................... 2 51 10.3.1 interrupt control regi ster 0 (i cr0)...................................................................... 255 10.3.2 interrupt control regi ster 1 (i cr1)...................................................................... 258 10.3.3 interrupt priority re gister (int pri)..................................................................... 259 10.3.4 interrupt source regi ster (intreq).................................................................... 260 10.3.5 interrupt mask registers (i ntmsk0 to in tmsk2)............................................ 261 10.3.6 interrupt mask clear registers (i ntmskclr0 to intmskclr2)................... 266 10.3.7 nmi flag control regi ster (nmifcr) ................................................................ 271 10.3.8 user interrupt mask level register (use rimask) ........................................... 273 10.3.9 on-chip module interrupt priority regi sters (int2pri0 to int2pri7).............. 276 10.3.10 interrupt source register (int2a0: not affected by ma sk states) ...................... 277 10.3.11 interrupt source register (int2a1: affected by ma sk states)............................ 280 10.3.12 interrupt mask regist er (int2mskr)................................................................. 282 10.3.13 interrupt mask clear regi ster (int2mskcr)..................................................... 285 10.3.14 on-chip module interrupt source re gisters (int2b0 to int2b7) ...................... 287 10.3.15 gpio interrupt set regi ster (int2gpic)............................................................. 294 10.4 interrupt sources.............................................................................................................. .. 296 10.4.1 nmi interrupt........................................................................................................ 296 10.4.2 irq interr upts ....................................................................................................... 296
rev.1.00 dec. 13, 2005 page xiv of l 10.4.3 irl interr upts ....................................................................................................... 297 10.4.4 on-chip module in terrupts ................................................................................... 299 10.4.5 interrupt priority levels of on-chip module in terrupts ....................................... 300 10.4.6 interrupt exception hand ling and prio rity............................................................ 301 10.5 operation ...................................................................................................................... ..... 308 10.5.1 interrupt sequence ................................................................................................ 308 10.5.2 multiple inte rrupts ................................................................................................ 310 10.5.3 interrupt masking by mai bit.............................................................................. 310 10.6 interrupt respon se time.................................................................................................... 311 10.7 usage notes .................................................................................................................... ... 312 10.7.1 to clear interrupt request when holding function selected ............................. 312 10.7.2 notes on setting irq/ irl[7:0] pin func tion ....................................................... 313 10.7.3 to clear irq and irl in terrupt requ ests .............................................................. 313 section 11 local bus state controller (lbsc)................................................. 315 11.1 features....................................................................................................................... ....... 315 11.2 input/output pins.............................................................................................................. .318 11.3 area overview.................................................................................................................. .320 11.3.1 space divisions .................................................................................................... 320 11.3.2 memory bus width .............................................................................................. 324 11.3.3 data alignm ent..................................................................................................... 325 11.3.4 pcmcia s upport ................................................................................................. 325 11.4 register desc riptions......................................................................................................... 3 29 11.4.1 memory address map select register ( mmselr)............................................. 331 11.4.2 bus control regi ster ( bcr) ................................................................................. 333 11.4.3 csn bus control regi ster (csn bcr) .................................................................. 336 11.4.4 csn wait control regi ster (csn wcr)................................................................ 342 11.4.5 csn pcmcia control re gister (csn pcr).......................................................... 347 11.5 operation ...................................................................................................................... ..... 352 11.5.1 endian/access size and da ta alignment.............................................................. 352 11.5.2 areas..................................................................................................................... 357 11.5.3 sram interface .................................................................................................... 361 11.5.4 burst rom (clock asynch ronous) interface ....................................................... 370 11.5.5 pcmcia inte rface................................................................................................ 372 11.5.6 mpx interface ...................................................................................................... 383 11.5.7 byte control sram interface .............................................................................. 389 11.5.8 wait cycles between accesses............................................................................. 393 11.5.9 bus arbitrat ion ..................................................................................................... 395 11.5.10 bus release and acqu ire sequence...................................................................... 397 11.5.11 cooperation between ma ster and slave................................................................ 399
rev.1.00 dec. 13, 2005 page xv of l section 12 ddr-sdram interface (ddrif)...................................................401 12.1 features....................................................................................................................... ....... 401 12.2 input/output pins .............................................................................................................. .403 12.3 address space, bus width, and data ali gnment............................................................... 404 12.3.1 address space of the ddrif................................................................................ 404 12.3.2 memory data bu s width ...................................................................................... 405 12.3.3 data alignm ent..................................................................................................... 406 12.4 register desc riptions ......................................................................................................... 4 10 12.4.1 memory interface mode register (mim) ............................................................. 412 12.4.2 sdram control regi ster (s cr).......................................................................... 416 12.4.3 sdram timing regi ster (str) .......................................................................... 418 12.4.4 sdram row attribute re gister (sdr)............................................................... 421 12.4.5 sdram mode regist er (sdmr)......................................................................... 422 12.4.6 ddr-sdram back-up re gister (dbk).............................................................. 424 12.5 operation ...................................................................................................................... ..... 425 12.5.1 ddr-sdram access .......................................................................................... 425 12.5.2 ddr-sdram initializat ion sequence................................................................. 425 12.5.3 supported sdram commands............................................................................ 426 12.5.4 sdram access mode.......................................................................................... 427 12.5.5 power-down modes ............................................................................................. 427 12.5.6 address multip lexing ........................................................................................... 429 12.6 ddr-sdram basi c timing ............................................................................................. 430 12.7 usage notes .................................................................................................................... ... 440 12.7.1 operating frequency............................................................................................. 440 12.7.2 stopping cl ock ..................................................................................................... 440 12.7.3 using scr to issue refa command (outsi de the initialization sequence) ....... 440 12.7.4 timing of connect ed sdram ............................................................................. 440 12.7.5 setting auto-refresh interval ............................................................................... 441 section 13 pci controller (pcic) .....................................................................443 13.1 features....................................................................................................................... ....... 443 13.2 input/output pins .............................................................................................................. .446 13.3 register desc riptions ......................................................................................................... 4 49 13.3.1 pcic enable control re gister (pci ecr) ............................................................ 455 13.3.2 configuration re gisters ........................................................................................ 456 13.3.3 local regi ster ....................................................................................................... 481 13.4 operation ...................................................................................................................... ..... 522 13.4.1 supported pci commands.................................................................................... 522 13.4.2 pcic initializ ation ................................................................................................ 523 13.4.3 master a ccess ....................................................................................................... 524
rev.1.00 dec. 13, 2005 page xvi of l 13.4.4 target a ccess........................................................................................................ 532 13.4.5 host bus bridge mode ......................................................................................... 541 13.4.6 normal mode ........................................................................................................ 544 13.4.7 power management .............................................................................................. 544 13.4.8 pci local bus basi c interface.............................................................................. 545 section 14 direct memory access controller (dmac)................................... 557 14.1 features....................................................................................................................... ....... 557 14.2 input/output pins.............................................................................................................. .559 14.3 register desc riptions......................................................................................................... 5 61 14.3.1 dma source address registers 0 to 11 (sar0 to sar11) ................................. 567 14.3.2 dma source address registers b0 to b3, b6 to b9 (sarb0 to sarb3, sa rb6 to sa rb9) .............................................................. 568 14.3.3 dma destination address registers 0 to 11 (dar0 to dar11) ........................ 568 14.3.4 dma destination address registers b0 to b3, b6 to b9 (darb0 to darb3, da rb6 to da rb9) ........................................................... 569 14.3.5 dma transfer count registers 0 to 11 (tcr0 to tcr11).................................. 570 14.3.6 dma transfer count registers b0 to b3, b6 to b9 (tcrb0 to tcrb3, tcrb6 to tcrb9) .............................................................. 571 14.3.7 dma channel control registers 0 to 11 (chcr0 to chcr11) ......................... 572 14.3.8 dma operation register 0, 1 (dmaor0 and dmaor1) .................................. 581 14.3.9 dma extended resource selector s (dmars0 to dmars2)............................. 584 14.4 operation ...................................................................................................................... ..... 588 14.4.1 dma transfer requests ....................................................................................... 588 14.4.2 channel prio rity.................................................................................................... 592 14.4.3 dma transfer types............................................................................................ 595 14.4.4 dma transfer flow ............................................................................................. 602 14.4.5 repeat mode transfer .......................................................................................... 604 14.4.6 reload mode transfer .......................................................................................... 605 14.4.7 dreq pin samplin g timing ................................................................................ 606 14.5 usage notes .................................................................................................................... ... 608 14.5.1 module stop ......................................................................................................... 608 14.5.2 address error........................................................................................................ 608 14.5.3 notes on burst mode transfer.............................................................................. 608 14.5.4 dack output di vision .......................................................................................... 609 14.5.5 clear dmint interrupt......................................................................................... 609 14.5.6 cs output settings and transfer size la rger than external bus width............... 609 14.5.7 dack assertion and dr eq sampling ................................................................ 609
rev.1.00 dec. 13, 2005 page xvii of l section 15 clock pul se generator (cpg)..........................................................613 15.1 features....................................................................................................................... ....... 613 15.2 input/output pins .............................................................................................................. .616 15.3 clock operatin g modes ..................................................................................................... 617 15.4 register desc riptions ......................................................................................................... 6 18 15.4.1 frequency control re gister (f rqcr) ................................................................. 619 15.4.2 pll control regist er (pllcr)............................................................................ 621 15.5 notes on boar d design ...................................................................................................... 622 section 16 watchdog timer and reset..............................................................625 16.1 features....................................................................................................................... ....... 625 16.2 input/output pins .............................................................................................................. .627 16.3 register desc riptions ......................................................................................................... 6 28 16.3.1 watchdog timer stop time register (wdtst) .................................................. 629 16.3.2 watchdog timer control/statu s register (w dtcsr)......................................... 630 16.3.3 watchdog timer base stop ti me register (wdtbst) ........................................ 631 16.3.4 watchdog timer coun ter (wdtcnt)................................................................. 632 16.3.5 watchdog timer base counter (wdtbcnt) ..................................................... 632 16.4 operation ...................................................................................................................... ..... 633 16.4.1 reset requ est......................................................................................................... 633 16.4.2 using watchdog tim er mode ................................................................................. 634 16.4.3 using interval timer mode .................................................................................... 634 16.4.4 time for wdt overflow ...................................................................................... 635 16.4.5 clearing wdt counter......................................................................................... 636 16.5 status pin change timi ng during re set ............................................................................ 636 16.5.1 power-on reset by preset................................................................................ 636 16.5.2 power-on reset by watch dog timer overflow................................................... 638 16.5.3 manual reset by watchdog timer overflow ....................................................... 640 section 17 power-down mode..........................................................................643 17.1 features....................................................................................................................... ....... 643 17.1.1 types of power-down modes .............................................................................. 643 17.2 input/output pins .............................................................................................................. .645 17.3 register desc riptions ......................................................................................................... 6 45 17.3.1 standby control regi ster (mst pcr)................................................................... 646 17.4 sleep mode ..................................................................................................................... ... 648 17.4.1 transition to sleep mode ...................................................................................... 648 17.4.2 cancellation of sleep mode.................................................................................. 648
rev.1.00 dec. 13, 2005 page xviii of l 17.5 module standby state........................................................................................................ 649 17.5.1 transition to module standby mode .................................................................... 649 17.5.2 cancellation of module sta ndby mode and resume............................................ 649 17.6 ddr-sdram power supply backup............................................................................... 650 17.6.1 self-refresh and initializatio n .............................................................................. 650 17.6.2 ddr-sdram backup sequence when turn ing off system po wer supply ....... 651 17.7 rtc power suppl y backup ............................................................................................... 653 17.7.1 transition to rtc powe r supply backup............................................................. 653 17.7.2 cancellation of rtc powe r supply b ackup......................................................... 653 17.8 mode tran sitio ns ............................................................................................................... 655 17.9 status pin chan ge timing ............................................................................................ 656 17.9.1 in reset ................................................................................................................. 656 17.9.2 in sleep ................................................................................................................. 656 section 18 timer unit (tmu)........................................................................... 657 18.1 features....................................................................................................................... ....... 657 18.2 input/output pins.............................................................................................................. .659 18.3 register desc riptions......................................................................................................... 6 60 18.3.1 timer output control register (t ocr)............................................................... 662 18.3.2 timer start register (tstr0, tstr1)................................................................. 663 18.3.3 timer constant register (t corn) (n = 0 to 5) .................................................... 665 18.3.4 timer counter (tcntn) (n = 0 to 5).................................................................... 665 18.3.5 timer control registers (t crn) (n = 0 to 5) ....................................................... 666 18.3.6 input capture regist er 2 (tcpr2) ....................................................................... 668 18.4 operation ...................................................................................................................... ..... 669 18.4.1 counter operation ................................................................................................ 669 18.4.2 input capture function ......................................................................................... 673 18.5 interrupts..................................................................................................................... ....... 674 18.6 usage notes .................................................................................................................... ... 675 18.6.1 register wr ites ..................................................................................................... 675 18.6.2 reading from tcnt............................................................................................. 675 18.6.3 reset rtc frequency di vider circuit.................................................................. 675 18.6.4 external clock frequency .................................................................................... 675 section 19 compare match timer (cmt) ........................................................ 677 19.1 features....................................................................................................................... ....... 677 19.2 input/output pins.............................................................................................................. .679 19.3 register desc riptions......................................................................................................... 6 79 19.3.1 configuration regist er (cmtcfg)...................................................................... 681 19.3.2 free-running time r (cmtfrt).......................................................................... 684
rev.1.00 dec. 13, 2005 page xix of l 19.3.3 control register (cmtctl) ................................................................................ 684 19.3.4 interrupt status regi ster (cmtirqs) .................................................................. 688 19.3.5 channels 0 to 3 time register s (cmtch0t to cmtch3t)............................... 689 19.3.6 channels 0 to 1 stop time regist ers (cmtch0st to cmtch1st).................. 689 19.3.7 channels 0 to 3 counters (cmtch0c to cmtch3c)........................................ 690 19.4 operation ...................................................................................................................... ..... 691 19.4.1 edge detec tion...................................................................................................... 691 19.4.2 32-bit timer: inpu t capture ................................................................................. 692 19.4.3 32-bit timer: out put compare............................................................................. 693 19.4.4 16-bit timer: inpu t capture ................................................................................. 697 19.4.5 16-bit timer: out put compare............................................................................. 699 19.4.6 counter: up-c ounter ............................................................................................. 701 19.4.7 counter: updown- counter .................................................................................... 703 19.4.8 counter: rotary switch opera tion of updown -counter ....................................... 705 19.4.9 interrupts............................................................................................................... 706 section 20 realtime clock (rtc) .....................................................................707 20.1 features....................................................................................................................... ....... 707 20.1.1 block diag ram...................................................................................................... 708 20.2 input/output pins .............................................................................................................. .709 20.3 register desc riptions ......................................................................................................... 7 10 20.3.1 64 hz counter (r64cnt)..................................................................................... 712 20.3.2 second counter (rseccnt) ............................................................................... 712 20.3.3 minute counter (r mincnt) ............................................................................... 713 20.3.4 hour counter (rhrcnt)..................................................................................... 713 20.3.5 day-of-week counte r (rwkcnt)...................................................................... 714 20.3.6 day counter (r daycnt) ................................................................................... 715 20.3.7 month counter (r moncnt) .............................................................................. 716 20.3.8 year counter (ryrcnt) ..................................................................................... 716 20.3.9 second alarm regist er (rsecar) ...................................................................... 717 20.3.10 minute alarm regist er (rminar)...................................................................... 717 20.3.11 hour alarm regist er (rhrar) ........................................................................... 718 20.3.12 day-of-week alarm regi ster (rwkar)............................................................. 718 20.3.13 day alarm register (rdaya r).......................................................................... 719 20.3.14 month alarm regist er (rmonar) ..................................................................... 720 20.3.15 year-alarm regist er (ryrar)............................................................................ 720 20.3.16 rtc control regist er 1 (rcr1)........................................................................... 721 20.3.17 rtc control regist er 2 (rcr2)........................................................................... 723 20.3.18 rtc control regist er (rcr3).............................................................................. 726
rev.1.00 dec. 13, 2005 page xx of l 20.4 operation ...................................................................................................................... ..... 727 20.4.1 time setting pr ocedures....................................................................................... 727 20.4.2 time reading pr ocedures..................................................................................... 728 20.4.3 alarm func tion..................................................................................................... 729 20.5 interrupts..................................................................................................................... ....... 730 20.6 usage notes .................................................................................................................... ... 730 20.6.1 register initia lization............................................................................................ 730 20.6.2 crystal oscillato r circuit ...................................................................................... 730 20.6.3 interrupt source and reques t generating order....................................................... 732 section 21 serial communication interface with fifo (scif)........................ 733 21.1 features....................................................................................................................... ....... 733 21.2 input/output pins.............................................................................................................. .739 21.3 register desc riptions......................................................................................................... 7 40 21.3.1 receive shift regi ster (scrs r) .......................................................................... 742 21.3.2 receive fifo data re gister (scf rdr) .............................................................. 742 21.3.3 transmit shift regi ster (sct sr) ......................................................................... 743 21.3.4 transmit fifo data re gister (scftdr)............................................................. 743 21.3.5 serial mode regist er (scsmr)............................................................................ 744 21.3.6 serial control regi ster (scs cr).......................................................................... 747 21.3.7 serial status regist er n (scfsr) ......................................................................... 751 21.3.8 bit rate regist er n (s cbrr) ............................................................................... 758 21.3.9 fifo control regist er n (scfcr) ....................................................................... 759 21.3.10 transmit fifo data count register n (sctfdr) ............................................... 762 21.3.11 receive fifo data count register n (s crfdr)................................................. 763 21.3.12 serial port regist er n (scsptr) .......................................................................... 764 21.3.13 line status regist er n (sclsr) ........................................................................... 767 21.3.14 serial error regist er n (screr) .......................................................................... 768 21.4 operation ...................................................................................................................... ..... 769 21.4.1 overview .............................................................................................................. 769 21.4.2 operation in asynch ronous mode ........................................................................ 772 21.4.3 operation in clocked synchronous mode ............................................................ 783 21.5 scif interrupt sources and the dmac ............................................................................. 792 21.6 usage notes .................................................................................................................... ... 794 section 22 serial i/o with fifo (siof) ........................................................... 797 22.1 features....................................................................................................................... ....... 797 22.2 input/output pins.............................................................................................................. .799 22.3 register desc riptions......................................................................................................... 8 00 22.3.1 mode register (simdr) ...................................................................................... 802
rev.1.00 dec. 13, 2005 page xxi of l 22.3.2 clock select regi ster (siscr) ............................................................................. 804 22.3.3 control register (sictr) ..................................................................................... 806 22.3.4 transmit data regist er (sitdr) .......................................................................... 809 22.3.5 receive data regist er (sirdr) ........................................................................... 810 22.3.6 transmit control data re gister (sitcr) ............................................................. 811 22.3.7 receive control data register (s ircr) .............................................................. 812 22.3.8 status register (sistr)........................................................................................ 813 22.3.9 interrupt enable regi ster (siier)......................................................................... 819 22.3.10 fifo control regist er (sifctr) ......................................................................... 821 22.3.11 transmit data assign re gister (sitdar) ........................................................... 823 22.3.12 receive data assign re gister (sirdar)............................................................. 824 22.3.13 control data assign re gister (sicdar) ............................................................. 825 22.4 operation ...................................................................................................................... ..... 827 22.4.1 serial cl ocks ......................................................................................................... 827 22.4.2 serial ti ming ........................................................................................................ 829 22.4.3 transfer data format............................................................................................ 830 22.4.4 register allocation of transfer data .................................................................... 832 22.4.5 control data interface .......................................................................................... 834 22.4.6 fifo...................................................................................................................... 836 22.4.7 transmit and receive procedures......................................................................... 838 22.4.8 interrupts............................................................................................................... 843 22.4.9 transmit and recei ve timi ng............................................................................... 845 section 23 serial protoc ol interface (hspi) ......................................................849 23.1 features....................................................................................................................... ....... 849 23.2 input/output pins .............................................................................................................. .851 23.3 register desc riptions ......................................................................................................... 8 51 23.3.1 control register (spcr)....................................................................................... 852 23.3.2 status register (spsr) ......................................................................................... 854 23.3.3 system control regi ster (sps cr)........................................................................ 857 23.3.4 transmit buffer regi ster (spt br)....................................................................... 859 23.3.5 receive buffer regi ster (spr br)........................................................................ 860 23.4 operation ...................................................................................................................... ..... 861 23.4.1 operation overview without dm a (fifo mode disabled)................................. 861 23.4.2 operation overview with dma ........................................................................... 862 23.4.3 operation with fifo mode enab led .................................................................... 862 23.4.4 timing diag rams .................................................................................................. 863 23.4.5 hspi software reset ............................................................................................ 864 23.4.6 clock polarity and tr ansmit cont rol .................................................................... 864 23.4.7 transmit and receive routines ............................................................................ 864
rev.1.00 dec. 13, 2005 page xxii of l section 24 multimedia ca rd interface (mmcif) ............................................. 865 24.1 features....................................................................................................................... ....... 865 24.2 input/output pins.............................................................................................................. .866 24.3 register desc riptions......................................................................................................... 8 67 24.3.1 command registers 0 to 5 (cmdr0 to cmdr5)................................................ 871 24.3.2 command start regist er (cmdstrt) ................................................................ 872 24.3.3 operation control re gister (o pcr)..................................................................... 873 24.3.4 card status regi ster (cstr)................................................................................ 875 24.3.5 interrupt control registers 0 to 2 (intcr0 to intcr2)..................................... 877 24.3.6 interrupt status registers 0 to 2 (intstr0 to intstr2) ................................... 880 24.3.7 transfer clock control register (c lkon).......................................................... 885 24.3.8 command timeout control register (ctocr) ................................................... 886 24.3.9 transfer byte number co unt register (tbcr) ................................................... 887 24.3.10 mode register (moder)..................................................................................... 888 24.3.11 command type regist er (cmdtyr).................................................................. 889 24.3.12 response type regi ster (rsp tyr)..................................................................... 890 24.3.13 transfer block number counter (t bncr).......................................................... 894 24.3.14 response registers 0 to 16, d (rspr0 to rspr16 , rsprd).............................. 895 24.3.15 data timeout regist er (dtoutr) ...................................................................... 897 24.3.16 data register (dr) ............................................................................................... 898 24.3.17 fifo pointer clear regi ster (fifoclr) ............................................................. 899 24.3.18 dma control regist er (dmacr) ....................................................................... 900 24.4 operation ...................................................................................................................... ..... 901 24.4.1 operations in mmc mode.................................................................................... 901 24.5 mmcif interrupt sources.................................................................................................. 931 24.6 operations when using dma ........................................................................................... 932 24.6.1 operation in read sequence................................................................................. 932 24.6.2 operation in write sequence ................................................................................ 942 24.7 register accesses with little endian speci fication........................................................... 953 section 25 audio codec interface (hac)......................................................... 955 25.1 features....................................................................................................................... ....... 955 25.2 input/output pins.............................................................................................................. .956 25.3 register desc riptions......................................................................................................... 9 57 25.3.1 control and status re gister ( haccr) ................................................................. 958 25.3.2 command/status address re gister (ha ccsar) ................................................ 960 25.3.3 command/status data regi ster (haccsdr)...................................................... 962 25.3.4 pcm left channel regi ster (hacpcml)........................................................... 963 25.3.5 pcm right channel regi ster (hacpc mr) ........................................................ 965 25.3.6 tx interrupt enable re gister (hac tier)........................................................... 966
rev.1.00 dec. 13, 2005 page xxiii of l 25.3.7 tx status regist er (hactsr)............................................................................. 967 25.3.8 rx interrupt enable re gister (hacrier)........................................................... 969 25.3.9 rx status regist er (hacrsr) ............................................................................ 970 25.3.10 hac control regist er (hacacr) ...................................................................... 971 25.4 ac 97 frame slot structure............................................................................................... 973 25.5 operation ...................................................................................................................... ..... 974 25.5.1 receiver ................................................................................................................ 974 25.5.2 transmitte r............................................................................................................ 975 25.5.3 dma ..................................................................................................................... 975 25.5.4 interrupts............................................................................................................... 975 25.5.5 initialization se quence.......................................................................................... 976 25.5.6 notes ..................................................................................................................... 981 25.5.7 reference .............................................................................................................. 981 section 26 serial sound interface (ssi) module...............................................983 26.1 features....................................................................................................................... ....... 983 26.2 input/output pins .............................................................................................................. .984 26.3 register desc riptions ......................................................................................................... 9 85 26.3.1 control register (ssicr) ..................................................................................... 986 26.3.2 status register (ssisr) ........................................................................................ 992 26.3.3 transmit data regist er (ssitdr)........................................................................ 997 26.3.4 receive data regist er (ssirdr) ......................................................................... 997 26.4 operation ...................................................................................................................... ..... 998 26.4.1 bus format............................................................................................................ 998 26.4.2 non-compressed modes....................................................................................... 999 26.4.3 compressed modes............................................................................................. 1008 26.4.4 operation m odes................................................................................................. 1011 26.4.5 transmit oper ation ............................................................................................. 1012 26.4.6 receive oper ation............................................................................................... 1015 26.4.7 serial clock control ........................................................................................... 1018 26.5 usage note..................................................................................................................... .. 1019 26.5.1 restrictions when an overflow occurs during receive dma operation .......... 1019 section 27 nand flash mem ory controller (flctl) ..................................1021 27.1 features....................................................................................................................... ..... 1021 27.2 input/output pins ............................................................................................................. 1 024 27.3 register desc riptions ....................................................................................................... 102 5 27.3.1 common control regi ster (flc mncr)............................................................ 1026 27.3.2 command control regi ster (flc mdcr).......................................................... 1028 27.3.3 command code regist er (flcmcdr) ............................................................. 1030
rev.1.00 dec. 13, 2005 page xxiv of l 27.3.4 address register (fladr) ................................................................................ 1030 27.3.5 data counter regist er (fldtc ntr) ................................................................ 1032 27.3.6 data register (fldatar) ................................................................................ 1033 27.3.7 interrupt dma control regi ster (flint dmacr) ........................................... 1034 27.3.8 ready busy timeout setting register (flb sytmr) ....................................... 1039 27.3.9 ready busy timeout c ounter (flbsy cnt)..................................................... 1040 27.3.10 data fifo register (fldtfifo)....................................................................... 1041 27.3.11 control code fifo regi ster (flecfi fo)......................................................... 1042 27.3.12 transfer control re gister (f ltrcr)................................................................. 1043 27.4 operation ...................................................................................................................... ... 1044 27.4.1 operating m odes ................................................................................................ 1044 27.4.2 command acce ss mode ..................................................................................... 1044 27.4.3 sector acces s mode ........................................................................................... 1046 27.4.4 ecc error corr ection ......................................................................................... 1048 27.4.5 status r ead ......................................................................................................... 1049 27.5 example of regist er setti ng ............................................................................................ 1050 27.6 interrupt sources.............................................................................................................. 1053 27.7 dma transfer sp ecificati ons .......................................................................................... 1053 section 28 general purpose i/o (gpio) ......................................................... 1055 28.1 features....................................................................................................................... ..... 1055 28.2 register desc riptions....................................................................................................... 106 0 28.2.1 port a control regi ster (pac r) ........................................................................ 1063 28.2.2 port b control re gister (p bcr)......................................................................... 1064 28.2.3 port c control re gister (p ccr)......................................................................... 1066 28.2.4 port d control regi ster (pdc r) ........................................................................ 1067 28.2.5 port e control regi ster (pec r) ......................................................................... 1069 28.2.6 port f control regi ster (pfc r).......................................................................... 1070 28.2.7 port g control regi ster (pgc r) ........................................................................ 1072 28.2.8 port h control regi ster (phc r) ........................................................................ 1074 28.2.9 port j control regi ster (pjc r) ........................................................................... 1075 28.2.10 port k control regi ster (pkc r) ........................................................................ 1077 28.2.11 port l control regi ster (plc r) ......................................................................... 1079 28.2.12 port m control regi ster (pm cr) ....................................................................... 1080 28.2.13 port a data regi ster (padr)............................................................................. 1081 28.2.14 port b data regi ster (pbdr) ............................................................................. 1081 28.2.15 port c data regi ster (pcdr) ............................................................................. 1082 28.2.16 port d data regi ster (pddr)............................................................................. 1082 28.2.17 port e data regi ster (ped r).............................................................................. 1083 28.2.18 port f data regi ster (pfd r) .............................................................................. 1084
rev.1.00 dec. 13, 2005 page xxv of l 28.2.19 port g data regi ster (pgdr)............................................................................. 1084 28.2.20 port h data regi ster (phdr)............................................................................. 1085 28.2.21 port j data regi ster (pjd r) ............................................................................... 1085 28.2.22 port k data regi ster (pkdr)............................................................................. 1086 28.2.23 port l data regi ster (pld r).............................................................................. 1086 28.2.24 port m data regi ster (pmd r) ........................................................................... 1087 28.2.25 port e pull-up control register (p epupr) ....................................................... 1087 28.2.26 port h pull-up control register (p hpupr) ...................................................... 1088 28.2.27 port j pull-up control register (p jpupr)......................................................... 1089 28.2.28 port k pull-up control register (p kpupr) ...................................................... 1090 28.2.29 port m pull-up control register (p mpupr) ..................................................... 1091 28.2.30 input-pin pull-up control register 1 (ppupr1)................................................ 1092 28.2.31 input-pin pull-up control register 2 (ppupr2)................................................ 1093 28.2.32 on-chip module select re gister (oms elr) ..................................................... 1094 28.3 usage example ................................................................................................................ 10 97 28.3.1 port output function .......................................................................................... 1097 28.3.2 port input fu nction .............................................................................................. 1098 28.3.3 on-chip module function ................................................................................... 1099 section 29 user break controller (ubc) ........................................................1101 29.1 features....................................................................................................................... ..... 1101 29.2 register desc riptions ....................................................................................................... 110 3 29.2.1 match condition setting registers 0 and 1 (cbr0 an d cbr1) ......................... 1105 29.2.2 match operation setting register s 0 and 1 (crr0 and crr1) ......................... 1111 29.2.3 match address setting registers 0 and 1 (car0 an d car1)............................ 1113 29.2.4 match address mask setting register s 0 and 1 (camr0 and camr1)........... 1114 29.2.5 match data setting re gister 1 (cdr1) .............................................................. 1115 29.2.6 match data mask setting re gister 1 (cdmr1) ................................................. 1116 29.2.7 execution count break re gister 1 (c etr1) ...................................................... 1117 29.2.8 channel match flag re gister (ccm fr) ............................................................ 1118 29.2.9 break control regi ster (cbc r) ......................................................................... 1119 29.3 operation desc ription ...................................................................................................... 1120 29.3.1 definition of words rela ted to acce sses ........................................................... 1120 29.3.2 user break opera tion sequenc e ......................................................................... 1121 29.3.3 instruction fetch cycle brea k ............................................................................ 1122 29.3.4 operand access cy cle brea k.............................................................................. 1123 29.3.5 sequential break ................................................................................................. 1124 29.3.6 program counter value to be saved................................................................... 1126 29.4 user break debugging support func tion ........................................................................ 1127 29.5 user break ex amples ....................................................................................................... 1128
rev.1.00 dec. 13, 2005 page xxvi of l 29.6 usage notes .................................................................................................................... . 1132 section 30 user debugging interface (h-udi)............................................... 1135 30.1 features....................................................................................................................... ..... 1135 30.2 input/output pins............................................................................................................. 1 137 30.3 boundary scan tap controllers (idcode, extest, sample/ preload, and bypass) .......................................... 1138 30.4 register desc riptions....................................................................................................... 114 0 30.4.1 instruction regist er (sdir) ................................................................................ 1141 30.4.2 interrupt source regi ster (sdint)..................................................................... 1142 30.4.3 bypass register (sdbpr) .................................................................................. 1142 30.4.4 boundary scan regist er (sdbsr) ..................................................................... 1143 30.5 operation ...................................................................................................................... ... 1152 30.5.1 tap contro l ....................................................................................................... 1152 30.5.2 h-udi rese t ....................................................................................................... 1153 30.5.3 h-udi interrupt .................................................................................................. 1153 30.6 usage notes .................................................................................................................... . 1154 section 31 electrical characteristics ............................................................... 1155 31.1 absolute maximu m ratings ............................................................................................ 1155 31.2 dc character istics ........................................................................................................... 11 56 31.3 ac character istics ........................................................................................................... 11 59 31.3.1 clock and control signal timi ng ....................................................................... 1160 31.3.2 control signal timing ........................................................................................ 1163 31.3.3 bus timi ng ......................................................................................................... 1164 31.3.4 ddrif signal timing ........................................................................................ 1182 31.3.5 intc module signa l timing .............................................................................. 1186 31.3.6 pcic module si gnal timi ng .............................................................................. 1188 31.3.7 dmac module sign al timi ng ........................................................................... 1190 31.3.8 tmu module signa l timing .............................................................................. 1191 31.3.9 cmt module signa l timing .............................................................................. 1192 31.3.10 scif module signa l timing ............................................................................... 1193 31.3.11 siof module si gnal timi ng .............................................................................. 1195 31.3.12 hspi module si gnal timi ng .............................................................................. 1199 31.3.13 mmcif module signa l timing .......................................................................... 1201 31.3.14 hac interface module signal ti ming ............................................................... 1203 31.3.15 ssi interface module signal ti ming .................................................................. 1205 31.3.16 flctl module sign al timi ng........................................................................... 1207 31.3.17 gpio signal timing ........................................................................................... 1211 31.3.18 h-udi module sign al timi ng............................................................................ 1212
rev.1.00 dec. 13, 2005 page xxvii of l 31.4 ac characteristic te st condi tions................................................................................... 1214 31.5 change in delay time based on load capa citance ........................................................ 1215 appendix ..........................................................................................................1217 a. cpu operation mode re gister (cpu opm) .................................................................... 1217 b. instruction prefetching an d its side ef fects ..................................................................... 1219 c. speculative execution for subroutine re turn.................................................................. 1220 d. register addr ess map ...................................................................................................... 1221 e. package dime nsions ........................................................................................................ 1255 f. mode pin settings ............................................................................................................ 12 56 g. pin functions .................................................................................................................. . 1258 g.1 pin stat es ............................................................................................................ 1258 g.2 handling of unus ed pins .................................................................................... 1267 h. turning on and off power supp ly .................................................................................. 1275 i. version registers (pvr, prr) ........................................................................................ 1276 j. part number list.............................................................................................................. 1 277 index ................................................................................................................1279
rev.1.00 dec. 13, 2005 page xxviii of l
rev.1.00 dec. 13, 2005 page xxix of l figures section 1 overview figure 1.1 sh7780 block diagram .............................................................................................. .. 9 figure 1.2 sh7780 pin arrangement............................................................................................ 10 figure 1.3 physical address space of sh7780............................................................................. 28 figure 1.4 relationship between area sel bits and memory address map............................. 29 section 2 programming model figure 2.1 data formats ...................................................................................................... ......... 33 figure 2.2 cpu register configur ation in each pr ocessing mode .............................................. 36 figure 2.3 ge neral registers ................................................................................................. ....... 37 figure 2.4 floatin g-point registers .......................................................................................... .... 39 figure 2.5 relationship be tween sz bit and endian..................................................................... 45 figure 2.6 formats of byte da ta and word data in register ....................................................... 47 figure 2.7 data formats in memory............................................................................................ .48 figure 2.8 processi ng state tr ansitions...................................................................................... .. 49 section 4 pipelining figure 4.1 basic pi pelines ................................................................................................... ......... 73 figure 4.2 instruction execution patterns (1) ............................................................................... 7 5 figure 4.2 instruction execution patterns (2) ............................................................................... 7 6 figure 4.2 instruction execution patterns (3) ............................................................................... 7 7 figure 4.2 instruction execution patterns (4) ............................................................................... 7 8 figure 4.2 instruction execution patterns (5) ............................................................................... 7 9 figure 4.2 instruction execution patterns (6) ............................................................................... 8 0 figure 4.2 instruction execution patterns (7) ............................................................................... 8 1 figure 4.2 instruction execution patterns (8) ............................................................................... 8 2 figure 4.2 instruction execution patterns (9) ............................................................................... 8 3 section 5 exception handling figure 5.1 instruction execu tion and exception handling......................................................... 105 figure 5.2 example of general exception acceptance order .................................................... 106 section 6 floating-point unit (fpu) figure 6.1 format of single-p recision floating- point number.................................................. 130 figure 6.2 format of double-p recision floating-point number ................................................ 130 figure 6.3 single-preci sion nan bit pattern .............................................................................. 133 figure 6.4 floatin g-point registers .......................................................................................... .. 136 figure 6.5 relation betw een sz bit an d endian......................................................................... 139
rev.1.00 dec. 13, 2005 page xxx of l section 7 memory management unit (mmu) figure 7.1 role of mmu....................................................................................................... ..... 149 figure 7.2 virtual addre ss space (at in mmucr = 0) ............................................................ 150 figure 7.3 virtual addre ss space (at in mmucr = 1) ............................................................ 151 figure 7.4 p4 area........................................................................................................... ........... 153 figure 7.5 phys ical address space............................................................................................ .154 figure 7.6 utlb configuration ................................................................................................ .167 figure 7.7 relationship between page size and addr ess format............................................... 169 figure 7.8 itlb configuration................................................................................................ ... 170 figure 7.9 flowchart of memory access us ing utlb.............................................................. 171 figure 7.10 flowchart of memory access using itlb ............................................................. 172 figure 7.11 operation of ldtlb inst ruction............................................................................. 175 figure 7.12 memory-mappe d itlb addre ss array................................................................... 184 figure 7.13 memory-ma pped itlb data array ........................................................................ 185 figure 7.14 memory-mappe d utlb address array ................................................................. 187 figure 7.15 memory-ma pped utlb data array....................................................................... 188 figure 7.16 physical address spa ce (32-bit address ex tended mode)..................................... 188 figure 7.17 pm b configuration ................................................................................................ .190 figure 7.18 memory-ma pped pmb addre ss array ................................................................... 193 figure 7.19 memory-ma pped pmb data array......................................................................... 193 section 8 caches figure 8.1 configuration of operand c ache (oc) ..................................................................... 198 figure 8.2 configuration of instruction ca che (ic) ................................................................... 199 figure 8.3 configuratio n of write-bac k buffer ......................................................................... 211 figure 8.4 configuration of write-throu gh buffer .................................................................... 211 figure 8.5 memory-mappe d ic address array ......................................................................... 218 figure 8.6 memory-map ped ic data array ............................................................................... 219 figure 8.7 memory-mappe d oc address array........................................................................ 221 figure 8.8 memory-map ped oc data array ............................................................................. 222 figure 8.9 store qu eue configur ation........................................................................................ 2 23 section 10 interrupt controller (intc) figure 10.1 bloc k diagram of intc.......................................................................................... 24 4 figure 10.2 example of irl interrupt co nnection ..................................................................... 297 figure 10.3 on-chip mo dule interrupt priority .......................................................................... 301 figure 10.4 interrupt operation flowchart................................................................................. 309 figure 10.5 example of in terrupt handling routine .................................................................. 312 section 11 local bus state controller (lbsc) figure 11.1 lbsc block diagram ............................................................................................. 31 7
rev.1.00 dec. 13, 2005 page xxxi of l figure 11.2 corresponden ce between virtual address space and external memory space of lb sc........................................................................................................ 321 figure 11.3 external memory space allocation (29-bit address mode)..................................... 323 figure 11.4 basic timi ng of sram interface............................................................................ 362 figure 11.5 example of 32-bit data-width sram connectio n ................................................ 363 figure 11.6 example of 16-bit data-width sram connectio n ................................................ 364 figure 11.7 example of 8-bit data-width sram connection .................................................. 365 figure 11.8 sram interface wa it timing (software wait only) ............................................. 366 figure 11.9 sram interface wait timing (wait cycle insertion by rdy signal, rdy signal is synchronous input) ............ 367 figure 11.10 sram interface wait timing (read-strobe negate timing setting) .................. 369 figure 11.11 burst rom basic ti ming...................................................................................... 371 figure 11.12 burs t rom wait ti ming....................................................................................... 371 figure 11.13 burs t rom wait ti ming....................................................................................... 372 figure 11.14 cexx and dack output of ata complement mode in dma transfer............. 374 figure 11.15 example of pcmcia interface ............................................................................. 377 figure 11.16 basic timing for pc mcia memory card interface ............................................. 378 figure 11.17 wait timing for pc mcia memory card interface .............................................. 379 figure 11.18 basic timing for pcmcia i/o card interface ..................................................... 380 figure 11.19 wait timing for pcmcia i/o card interface ...................................................... 381 figure 11.20 dynamic bus sizing timi ng for pcmcia i/o ca rd interface ............................. 382 figure 11.21 example of 32-b it data width mpx connection ................................................. 384 figure 11.22 mpx interface ti ming 1 (single read cycle, iw = 0, no external wait) ........... 384 figure 11.23 mpx interface timing 2 (single read, iw = 0, one external wait inserted)...... 385 figure 11.24 mpx interface timing 3 (single write cycle, iw = 0, no external wait) .......... 385 figure 11.25 mpx interface timing 4 (single write cycle, iw = 1, one external wait inserted).................................. 386 figure 11.26 mpx interface timing 5 (burst read cycle, iw = 0, no external wait, 32 -byte data transfer) ............... 386 figure 11.27 mpx interface timing 6 (burst read cycle, iw = 0, external wait control, 32-byte data transfer)........ 387 figure 11.28 mpx interface timing 7 (burst write cycle, iw = 0, no external wait, 32 -byte data transfer) .............. 387 figure 11.29 mpx interface timing 8 (burst write cycle, iw = 1, external wait control, 32-byte data transfer) ....... 388 figure 11.30 example of 32-bit data-width byte-c ontrol sram ........................................... 389 figure 11.31 byte-control sram basic read cycl e (no wa it) ............................................... 390 figure 11.32 byte-control sram basic re ad cycle (one intern al wait cy cle)...................... 391 figure 11.33 byte-control sram basic read cycle (one internal wait + one external wait).............................................................. 392
rev.1.00 dec. 13, 2005 page xxxii of l figure 11.34 wait cycles between acces s cycles ..................................................................... 394 figure 11.35 ar bitration sequence............................................................................................ .396 figure 11.36 example of the bus release restraint by the dmac chcr lckn bit .............. 398 section 12 ddr-sd ram interface (ddrif) figure 12.1 ddrif block diagram ........................................................................................... 402 figure 12.2 physical addr ess space of th is lsi ....................................................................... 405 figure 12.3 data alignmen t in ddr-sdram and ddrif....................................................... 409 figure 12.4 relationship between write values in sdmr and output signals to memory pins .............................................................................. 423 figure 12.5 ddrif basic timing (1-/2-/4-/8-byte single burst r ead without auto precharge) ................................. 430 figure 12.6 ddrif basic timing (1-/2-/4-/8-byte single burst wr ite without auto precharge) ................................ 431 figure 12.7 ddrif basic timing (1-/2-/4-/8-byte single burst read with auto precharge)... 432 figure 12.8 ddrif basic timing (1-/2-/4-/8-byte single burst wr ite with auto precharge) ..................................... 433 figure 12.9 ddrif basic timing (4 burst read: 32-byte without auto precharge)................. 434 figure 12.10 ddrif basic timing (4 burst write: 32-byte without auto precharge).............. 435 figure 12.11 ddrif basic timing (from prec harging all banks to bank activation)............. 436 figure 12.12 ddrif basic ti ming (mode regist er setting)..................................................... 437 figure 12.13 ddrif basic timing (enter auto-refresh/exit to bank activation)................... 438 figure 12.14 ddrif basic timing (enter self-refresh/exit to command issuing) ................. 439 section 13 pci controller (pcic) figure 13.1 pcic block diagram .............................................................................................. 4 45 figure 13.2 superhyway bu s to pci local bus access ............................................................ 525 figure 13.3 superhyway bus to pci local bus address translation (pci memory space 0) ........................................................................................... 526 figure 13.4 superhyway bus to pci local bus address translation (pci memory space 1) ........................................................................................... 527 figure 13.5 superhyway bus to pci local bus address translation (pci memory space 2)............................................................................................ 527 figure 13.6 superhyway bus to pci lo cal bus address transl ation (pci i/o) ....................... 528 figure 13.7 endian conversion from superhyway bus to pci local bus (non-byte swapping: tbs = 0) .............................................................................. 530 figure 13.8 endian conversion from superhyway bus to pci local bus (byte swapping: tbs = 1)...................................................................................... 531 figure 13.9 pci local bus to superhyway bus me mory map .................................................... 532 figure 13.10 pci local bus to superhyway bus address translation (local address space 0/1)..................................................................................... 534
rev.1.00 dec. 13, 2005 page xxxiii of l figure 13.11 pci local bus to superhyway bus address translation (pcic i/o space) ........ 535 figure 13.12 endian conversion from pci local bus to superhyway bus (non-byte swapping: tbs = 0) ............................................................................ 537 figure 13.13 endian conversion from pci local bus to superhyway bus (non-byte swapping: tbs = 1) ............................................................................ 538 figure 13.14 cache flush/purge execution fl ow for pci local bus to superhyway bus......... 540 figure 13.15 address generation fo r type 0 configur ation access.......................................... 542 figure 13.16 pci local bus po wer down state transition ....................................................... 545 figure 13.17 master write cycle in host bus bridge mode (single)........................................ 546 figure 13.18 master read cycle in host bus bridge mode (single)......................................... 547 figure 13.19 master write cycl e in normal mode (burst)........................................................ 548 figure 13.20 master read cycl e in normal mode (burst)......................................................... 549 figure 13.21 target read cycl e in normal mode (single)........................................................ 551 figure 13.22 target write cycl e in normal mode (single)....................................................... 552 figure 13.23 target memory read cycl e in host bus bridge mode (burst) ............................ 553 figure 13.24 target memory write cycl e in host bus bridge mode (burst) ........................... 554 figure 13.25 master write cycle in host bus bridge mode (burst, with stepping) .................. 555 figure 13.26 target memory read cycle in ho st bus bridge mode (bur st, with stepping)..... 556 section 14 direct memory access controller (dmac) figure 14.1 block diagram of dmac ....................................................................................... 558 figure 14.2 round-robin mode (e xample of channe l 0 to 5) .................................................... 593 figure 14.3 changes in channel priority in round-robin mode (example of channel 0 to 5)..................................................................................... 594 figure 14.4 data flow of dual addr ess mode........................................................................... 595 figure 14.5 example of dma transfer timing in dual address mode (source: ordinary memory, destin ation: ordinary memory) ................................ 596 figure 14.6 dma transfer timing ex ample in cycle-steal normal mode 1 (dreq low level detection) ................................................................................ 597 figure 14.7 dma transfer timing ex ample in cycle-steal normal mode 2 (dreq low level detection) ................................................................................ 598 figure 14.8 example of dma transfer timing in cycle steal intermittent mode (dreq low level detection) ................................................................................ 598 figure 14.9 dma transfer timing example in burst mode (dreq low level detection) .... 599 figure 14.10 bus state when mu ltiple channels ar e operating ................................................. 602 figure 14.11 dma tr ansfer flowchart ...................................................................................... 603 figure 14.12 relo ad mode transfer........................................................................................... 6 05 figure 14.13 example of dreq input detec tion in cycle steal mode edge detection............ 606 figure 14.14 example of dreq input detec tion in cycle steal mode level detection........... 606 figure 14.15 example of dreq input det ection in burst mode edge detection ..................... 607 figure 14.16 example of dreq input det ection in burst mode level detection .................... 607
rev.1.00 dec. 13, 2005 page xxxiv of l section 15 clock pulse generator (cpg) figure 15.1 bloc k diagram of cpg ........................................................................................... 61 4 figure 15.2 points for attenti on when using crysta l resonator................................................ 622 figure 15.3 points for attention when using pll and dll circuit.......................................... 623 section 16 watchdog timer and reset figure 16.1 block diagram of wdt .......................................................................................... 626 figure 16.2 wdt coun ting up oper ation ................................................................................. 635 figure 16.3 status ou tput during power-on.......................................................................... 637 figure 16.4 status output by rese t input during norm al operation .................................... 637 figure 16.5 status output by reset input during sleep mode .............................................. 638 figure 16.6 status output by watchdog timer overflow power-on reset during normal operation ........................................................................................ 639 figure 16.7 status output by watchdog timer overflow power-on reset during sleep mode .................................................................................................. 639 figure 16.8 status output by watchdog timer overflow manual reset during normal operation........................................................................................ 640 figure 16.9 status output by watchdog timer overflow manual reset during sleep mode.................................................................................................. 641 section 17 power-down mode figure 17.1 ddr-sdram interface operation when turning system powe r supply on /off ................................................................... 650 figure 17.2 sequence for turning off syst em power supply in se lf-refresh mode ................ 652 figure 17.3 sequence for turnin g system power su pply on/off.............................................. 654 figure 17.4 mode transition di agram ....................................................................................... 655 figure 17.5 status pins outp ut from sleep to interrupt.............................................................. 656 section 18 timer unit (tmu) figure 18.1 block diagram of tmu .......................................................................................... 658 figure 18.2 example of coun t operation setting procedure ..................................................... 670 figure 18.3 tcnt au to-reload oper ation ................................................................................ 671 figure 18.4 count timing when operating on inte rnal cloc k ................................................... 671 figure 18.5 count timing when operating on exte rnal clock .................................................. 672 figure 18.6 count timing when opera ting on on-chip rtc output clock ............................... 672 figure 18.7 operation timing when using input capt ure function .......................................... 673 section 19 timer/counter (cmt) figure 19.1 block diagram of cmt .......................................................................................... 678 figure 19.2 edge detection (example of rising edge) ................................................................ 691 figure 19.3 32-bit timer mode: input capture (channel 1 and channel 0)................................ 692 figure 19.4 32-bit timer mode: input capture operation timing ............................................. 692
rev.1.00 dec. 13, 2005 page xxxv of l figure 19.5 cmt_ctrn assert timing (channel 0 and 1) ........................................................ 694 figure 19.6 32-bit timer mode: output compare (channel 1 and channel 0) ........................... 694 figure 19.7 32-bit timer mode: output compare operation timing (example of high output in active and not active by cmtchnst).................... 695 figure 19.8 32-bit timer mode: output compare operation timing (example of high output in activ e and not active by cmtfrt)......................... 695 figure 19.9 16-bit timer mode: input capture (channel 1 and channel 0)................................ 697 figure 19.10 16-bit timer mode: input capture oper ation timing .......................................... 698 figure 19.11 16-bit timer mode: output compare (cmt_ctr pins are available fo r channel 1 and channel 0) ................................ 699 figure 19.12 16-bit timer mode: ou tput compare oper ation timing ..................................... 700 figure 19.13 up-counter mode (channel 1 and channel 0)........................................................ 701 figure 19.14 up-counter mode operation timing..................................................................... 701 figure 19.15 updown-counter mode (only ch annel 0).............................................................. 703 figure 19.16 updown-counter mode: coun tdown operation timing (only channel 0)............ 703 figure 19.17 rotary switch operation count- up timing.......................................................... 705 figure 19.18 rotary switch op eration count-do wn timing..................................................... 705 section 20 realtime clock (rtc) figure 20.1 bloc k diagram of rtc ........................................................................................... 70 8 figure 20.2 examples of time setting pr ocedures..................................................................... 727 figure 20.3 examples of time reading pr ocedures................................................................... 728 figure 20.4 example of use of alarm function......................................................................... 729 figure 20.5 example of crysta l oscillator circu it connectio n .................................................. 731 figure 20.6 interrupt request signal generation timing of complex sources ......................... 732 section 21 serial communicati on interface with fifo (scif) figure 21.1 bloc k diagram of scif........................................................................................... 7 35 figure 21.2 scif0_rts pin (only in channel 0) ...................................................................... 736 figure 21.3 scif0_cts pin (only in channel 0) ...................................................................... 736 figure 21.4 scifn_ sck pin (n = 0, 1)....................................................................................... 73 7 figure 21.5 scifn_txd pin (n = 0, 1) ...................................................................................... 737 figure 21.6 scifn_rx d pin (n = 0, 1)...................................................................................... 738 figure 21.7 data format in asynchronous communication (example with 8-bit data, par ity, and two stop bits) ........................................... 772 figure 21.8 sample scif initialization fl owchart ..................................................................... 775 figure 21.9 sample serial transmission flowchart ................................................................... 776 figure 21.10 sample scif transmission operation (example with 8-bit data, parity, one st op bit).................................................. 778 figure 21.11 sample operation using modem control ( scif0_cts ) (only in channel 0) ..... 778 figure 21.12 sample serial reception flowch art (1)................................................................. 779
rev.1.00 dec. 13, 2005 page xxxvi of l figure 21.12 sample serial reception flowch art (2)................................................................. 780 figure 21.13 sample scif receive operation (example with 8-bit data, parity, one st op bit) .................................................. 782 figure 21.14 sample operation using modem control ( scif0_rts ) (only in channel 0)..... 782 figure 21.15 data format in cl ocked synchronous communication ........................................ 783 figure 21.16 sample scif initialization fl owchart ................................................................... 785 figure 21.17 sample serial transmission flowchart ................................................................. 786 figure 21.18 sample scif transmission operation in clocked synchronous mode................ 787 figure 21.19 sample serial reception flowch art (1)................................................................. 788 figure 21.19 sample serial reception flowch art (2)................................................................. 789 figure 21.20 sample scif reception op eration in clocked sy nchronous mode ..................... 790 figure 21.21 sample simultaneous seri al transmission and r eception flowchart................... 791 figure 21.22 receive data sampli ng timing in asynchronous mode ...................................... 795 figure 21.23 example of synchroni zation clock transf er by dmac ...................................... 796 section 22 serial i/o with fifo (siof) figure 22.1 bloc k diagram of siof .......................................................................................... 79 8 figure 22.2 se rial cloc k supply.............................................................................................. ... 827 figure 22.3 serial data synchronizati on timing ....................................................................... 829 figure 22.4 siof tr ansmit/receive timing .............................................................................. 830 figure 22.5 transmit/receiv e data bit a lignment .................................................................... 832 figure 22.6 control data bit alig nment .................................................................................... 833 figure 22.7 control data interface (slot position) ..................................................................... 834 figure 22.8 control data interface (seconda ry fs) ................................................................... 835 figure 22.9 example of transm it operation in ma ster mode.................................................... 838 figure 22.10 example of receive operation in ma ster mode ................................................... 839 figure 22.11 example of tran smit operation in slave mode .................................................... 840 figure 22.12 example of recei ve operation in slave m ode ..................................................... 841 figure 22.13 transmit and receive timing (8-bit monaur al data (1))..................................... 845 figure 22.14 transmit and receive timing (8-bit monaur al data (2))..................................... 845 figure 22.15 transmit and receive timing (16-bit mona ural data) ........................................ 846 figure 22.16 transmit and receive timing (16-bit ster eo data (1)) ........................................ 846 figure 22.17 transmit and receive timing (16-bit ster eo data (2)) ........................................ 847 figure 22.18 transmit and receive timing (16-bit ster eo data (3)) ........................................ 847 figure 22.19 transmit and receive timing (16-bit ster eo data (4)) ........................................ 848 figure 22.20 transmit and receive timing (16-bit st ereo data).............................................. 848 section 23 serial pr otocol interface (hspi) figure 23.1 bloc k diagram of hspi .......................................................................................... 85 0 figure 23.2 oper ational fl owchart............................................................................................ .861 figure 23.3 timing cond itions when fb s = 0........................................................................... 863
rev.1.00 dec. 13, 2005 page xxxvii of l figure 23.4 timing cond itions when fb s = 1........................................................................... 864 section 24 multimedia card interface (mmcif) figure 24.1 block diagram of mmcif...................................................................................... 866 figure 24.2 dr access example ................................................................................................ 899 figure 24.3 example of command sequence for commands not requiring comma nd response ........................................................................ 903 figure 24.4 example of operational flow for commands not requiring comma nd response ........................................................................ 904 figure 24.5 example of command sequen ce for commands without data transfer (no data busy state)............................................................................................... 905 figure 24.6 example of command sequen ce for commands without data transfer (with data busy state)............................................................................................. 906 figure 24.7 example of operational flow for commands without data transfer..................... 907 figure 24.8 example of command sequence for commands with read data (block size fifo size) ........................................................................................ 909 figure 24.9 example of command sequence for commands with read data (block size > fi fo size) ........................................................................................ 910 figure 24.10 example of command sequence for commands with read data (multiple block transfer)...................................................................................... 911 figure 24.11 example of command sequence for commands with read data (stream transfer)................................................................................................... 912 figure 24.12 example of operational flow for commands with read data (single block tr ansfer) ......................................................................................... 913 figure 24.13 example of operational flow for commands with read data (1) (open-ended multiple block transfer) ................................................................. 914 figure 24.13 example of operational flow for commands with read data (2) (open-ended multiple block transfer).................................................................. 915 figure 24.13 example of operational flow for commands with read data (3) (pre-defined multiple block transf er) .................................................................. 916 figure 24.13 example of operational flow for commands with read data (4) (pre-defined multiple block transf er) .................................................................. 917 figure 24.14 example of operational flow for commands with read data (stream transfer) .................................................................................................. 918 figure 24.15 example of command sequence for commands with write data (block size fifo size) ...................................................................................... 921 figure 24.16 example of command sequence for commands with write data (block size > fi fo size) ...................................................................................... 922 figure 24.17 example of command sequence for commands with write data (multiple block transfer) ..................................................................................... 923
rev.1.00 dec. 13, 2005 page xxxviii of l figure 24.18 example of command sequence for commands with write data (stream transfer)................................................................................................... 924 figure 24.19 example of operational flow for commands with write data (single block tr ansfer) ......................................................................................... 925 figure 24.20 example of operational flow for commands with write data (1) (open-ended multiple block transfer) ................................................................. 926 figure 24.20 example of operational flow for commands with write data (2) (open-ended multiple block transfer) ................................................................. 927 figure 24.20 example of operational flow for commands with write data (3) (pre-defined multiple block transf er).................................................................. 928 figure 24.20 example of operational flow for commands with write data (4) (pre-defined multiple block transf er).................................................................. 929 figure 24.21 example of operational flow for commands with write data (stream transfer) .................................................................................................. 930 figure 24.22 example of read sequen ce flow (single block transfer) ................................... 934 figure 24.23 example of read sequence flow (1) (open-ended multiple block transfer)...... 935 figure 24.23 example of read sequence flow (2) (open-ended multiple block transfer)...... 936 figure 24.23 example of read sequence flow (3) (pre-defined multiple block transfer) ...... 937 figure 24.23 example of read sequence flow (4) (pre-defined multiple block transfer) ...... 938 figure 24.24 example of operationa l flow for stream read transfer ...................................... 939 figure 24.25 example of operational flow for auto-mode pre-defined multiple block read transfer (1)...................................................... 940 figure 24.25 example of operational flow for auto-mode pre-defined multiple block read transfer (2) ...................................................... 941 figure 24.26 example of write sequen ce flow (1) (single bl ock transfer)............................. 944 figure 24.26 example of write sequen ce flow (2) (single bl ock transfer)............................. 945 figure 24.27 example of write sequence flow (1) (open-ended multiple block transfer)..... 946 figure 24.27 example of write sequence flow (2) (open-ended multiple block transfer)..... 947 figure 24.27 example of write sequence flow (3) (pre-defined multiple block transfer)...... 948 figure 24.27 example of write sequence flow (4) (pre-defined multiple block transfer)...... 949 figure 24.28 example of operationa l flow for stream write transfer ..................................... 950 figure 24.29 example of operational flow for auto-mode pre-defined multiple block write transfer (1)..................................................... 951 figure 24.29 example of operational flow for auto-mode pre-defined multiple block write transfer (2)..................................................... 952 section 25 audio codec interface (hac) figure 25.1 block diagram .................................................................................................... .... 956 figure 25.2 ac97 fr ame slot stru cture ..................................................................................... 973 figure 25.3 in itialization sequence .......................................................................................... .. 976 figure 25.4 sample flowchart fo r off-chip codec re gister write ........................................... 977
rev.1.00 dec. 13, 2005 page xxxix of l figure 25.5 sample flowchart for of f-chip codec regist er read (1) ...................................... 978 figure 25.6 sample flowchart for of f-chip codec regist er read (2) ...................................... 979 figure 25.7 sample flowchart for of f-chip codec regist er read (3) ...................................... 980 section 26 serial so und interface (ssi) module figure 26.1 block di agram of ssi module ................................................................................ 984 figure 26.2 philips form at (with no padding).......................................................................... 1000 figure 26.3 philips fo rmat (with pa dding)............................................................................... 1000 figure 26.4 sony format (with serial data first, fo llowed by paddin g bits) ......................... 1001 figure 26.5 matsushita format (with paddi ng bits first, followed by serial data)................ 1001 figure 26.6 multi-ch annel format (4 channe ls, no padd ing).................................................. 1003 figure 26.7 multi-channel format (6 channels with hi gh padding) ....................................... 1003 figure 26.8 multi-channel format (8 channels, with padd ing bits first, followed by serial data , with padding)................................................................ 1004 figure 26.9 basic sample format (transmit mode with example system/data word length)................................. 1005 figure 26.10 inverted clock .................................................................................................. ... 1005 figure 26.11 inve rted word select........................................................................................... 1 006 figure 26.12 inverted padding po larity .................................................................................... 100 6 figure 26.13 padding bits first, fo llowed by serial data , with delay.................................... 1006 figure 26.14 padding bits first, follo wed by serial data, without de lay............................... 1007 figure 26.15 serial data first, foll owed by padding bits, without de lay............................... 1007 figure 26.16 parallel right aligned with delay ....................................................................... 1007 figure 26.17 mute enabled .................................................................................................... .. 1008 figure 26.18 compressed data format, sl ave transmitter, burst mode disabled .................. 1009 figure 26.19 compressed data format, slav e transmitter, and burst mode enabled ............ 1009 figure 26.20 transition diagra m between opera tion mode s................................................... 1011 figure 26.21 transmissi on using dma controller ................................................................. 1013 figure 26.22 transmission using interrupt data fl ow control ................................................ 1014 figure 26.23 reception using dma cont roller ........................................................................ 1016 figure 26.24 reception using inte rrupt data flow control ..................................................... 1017 section 27 nand flash memory controller (flctl) figure 27.1 flc tl block diagram ......................................................................................... 1023 figure 27.2 read operation timing for nand-type flash memory (1)................................ 1044 figure 27.3 programming operation ti ming for nand-type flash memory (1) .................. 1045 figure 27.4 programming operation ti ming for nand-type flash memory (2) .................. 1045 figure 27.5 relationship between dma transfer and sector (data and control code), and memory and dm a transfer........................................................................... 1046 figure 27.6 relationship between sector number and address expansion of nand-type flash memory.................................................................................. 1047
rev.1.00 dec. 13, 2005 page xl of l figure 27.7 sector access when unusable sector exists in con tinuous sect ors..................... 1048 figure 27.8 nand flash co mmand access (block erase)..................................................... 1050 figure 27.9 nand flash sector access (flash write ) using dm a ....................................... 1051 figure 27.10 nand flash co mmand access (flash read) .................................................... 1052 section 28 general purpose i/o (gpio) figure 28.1 port data output timing (example of port a) ..................................................... 1097 figure 28.2 port data input timing (example of port a) ........................................................ 1098 section 29 user break controller (ubc) figure 29.1 block diagram of ubc......................................................................................... 1102 figure 29.2 flowchart of user br eak debugging support function ........................................ 1127 section 30 user debugging interface (h-udi) figure 30.1 h-ud i block diagram .......................................................................................... 1136 figure 30.2 sequence for switching from boundary-scan tap controller to h-udi ............ 1139 figure 30.3 tap contro ller state tran sitions .......................................................................... 1152 figure 30.4 h-udi reset...................................................................................................... .... 1153 section 31 electrical characteristics figure 31.1 extal clock input timing ................................................................................. 1161 figure 31.2 clkout cloc k output timi ng (1)...................................................................... 1161 figure 31.3 clkout cloc k output timi ng (2)...................................................................... 1161 figure 31.4 power-on oscillation settlin g time ..................................................................... 1162 figure 31.5 mode pins setup/hold timing............................................................................ 1162 figure 31.6 pll synchr onization settlin g time ...................................................................... 1163 figure 31.7 cont rol signal timing........................................................................................... 1 163 figure 31.8 sram bus cycle: basic bus cycle (no wait) .................................................... 1165 figure 31.9 sram bus cycle: basi c bus cycle (one in ternal wa it) ..................................... 1166 figure 31.10 sram bus cycle: basic bus cycle (one internal wait + on e external wait) ........................................................... 1167 figure 31.11 sram bus cycle: basic bus cycle (no wait, no address setup/ hold time insertion, rds = 1, rdh = 0, wts = 1, wth = 1)......................... 1168 figure 31.12 burst ro m bus cycle (n o wait) ....................................................................... 1169 figure 31.13 burst rom bus cycle (1st data: one internal wait + one external wait ; 2nd/3rd/4th data: one intern al wait) ................................. 1170 figure 31.14 burst rom bus cycle (no wait, no address setup/ hold time insertion, rds = 1, rd h = 0) .......................................................... 1171 figure 31.15 burst rom bus cycle (one internal wait + one external wait) ...................... 1172 figure 31.16 pcmcia memory bus cycle ............................................................................. 1173 figure 31.17 pcmcia i/o bus cy cle...................................................................................... 1174
rev.1.00 dec. 13, 2005 page xli of l figure 31.18 pcmcia i/o bus cycle (tedx = 1, thex = 1, iw/pciw = 1, one internal wa it, dynamic bus sizing).................................... 1175 figure 31.19 mpx basi c bus cycle: read ............................................................................... 1176 figure 31.20 mpx basi c bus cycle: write .............................................................................. 1177 figure 31.21 mpx bus cycle: burs t read ............................................................................... 1178 figure 31.22 mpx bus cycle: burs t write .............................................................................. 1179 figure 31.23 byte cont rol sram bus cycle .......................................................................... 1180 figure 31.24 byte control sram bus cycle: basic read cycle (no wait, no address setup/hold time insertion, rds = 1, rdh = 0)............ 1181 figure 31.25 mclk output timing......................................................................................... 1183 figure 31.26 read timing of ddr-sdram (2 bu rst read ) ................................................. 1184 figure 31.27 write timing of ddr-sdram (2 bu rst write )................................................. 1185 figure 31.28 nm i input timing ............................................................................................... 1 186 figure 31.29 irq/irl, gpio interr upt input and irqout output timing............................ 1187 figure 31.30 pci cl ock input timing ...................................................................................... 1189 figure 31.31 out put signal timing .......................................................................................... 11 89 figure 31.32 i nput signal timing............................................................................................. 1189 figure 31.33 dreq and drak timing .................................................................................. 1190 figure 31.34 tclk input timing ............................................................................................ 119 1 figure 31.35 cmt timing (1).................................................................................................. 1192 figure 31.36 cmt timing (2).................................................................................................. 1192 figure 31.37 scifn_sck input clock timing (n = 0, 1) ........................................................ 1193 figure 31.38 scif channel n i/o synchr onous mode clock timi ng (n = 0, 1) ...................... 1194 figure 31.39 siof_m clk input ti ming................................................................................. 1195 figure 31.40 siof transmission/reception timing (master mode 1, fall sampling)............ 1196 figure 31.41 siof transmission/reception timing (master mode 1, rise sampling)........... 1196 figure 31.42 siof transmission/reception timing (master mode 2, fall sampling)............ 1197 figure 31.43 siof transmission/reception timing (master mode 2, rise sampling)........... 1197 figure 31.44 siof transmission/reception timing (slave mode 1, slave mode 2) .............. 1198 figure 31.45 hspi data output/input timing ......................................................................... 1200 figure 31.46 mmcif transmit timing.................................................................................... 1201 figure 31.47 mmcif receive ti ming ..................................................................................... 1202 figure 31.48 hac co ld reset ti ming ..................................................................................... 1203 figure 31.49 hac sy nc output timing ................................................................................ 1203 figure 31.50 hac cl ock input ti ming.................................................................................... 1203 figure 31.51 hac interface module signal timing ................................................................ 1204 figure 31.52 ssi cloc k input/output timing .......................................................................... 1205 figure 31.53 ssi tr ansmit timing (1) ..................................................................................... 1205 figure 31.54 ssi tr ansmit timing (2) ..................................................................................... 1206 figure 31.55 ssi r eceive timing (1) ....................................................................................... 120 6
rev.1.00 dec. 13, 2005 page xlii of l figure 31.56 ssi r eceive timing (2)....................................................................................... 120 6 figure 31.57 command issue timi ng of nand-type flash memory ..................................... 1208 figure 31.58 address issue timi ng of nand-type fl ash memo ry......................................... 1209 figure 31.59 data read timi ng of nand-type flash memory .............................................. 1209 figure 31.60 data write timi ng of nand-type fl ash memory ............................................. 1210 figure 31.61 status read timi ng of nand-type fl ash memory ............................................ 1210 figure 31.62 gpio timing..................................................................................................... .. 1211 figure 31.63 tc k input timing............................................................................................... 1 212 figure 31.64 preset hold timing......................................................................................... 1213 figure 31.65 h-udi da ta transfer timing.............................................................................. 1213 figure 31.66 asebrk pin break timing................................................................................ 1213 figure 31.67 output load circuit ............................................................................................ 1 214 figure 31.68 load cap acitance-delay time ............................................................................ 1215 appendix figure b.1 inst ruction prefetch.............................................................................................. ... 1219 figure e.1 package dime nsions (449-p in bga) ..................................................................... 1255 figure h.1 sequence of turni ng on and off po wer supp ly .................................................... 1275
rev.1.00 dec. 13, 2005 page xliii of l tables section 1 overview table 1.1 sh7780 features....................................................................................................... 2 table 1.2 pin functions .......................................................................................................... 11 section 2 programming model table 2.1 initial register values............................................................................................. 35 table 2.2 bit allocation for fpu exception handling........................................................... 45 section 3 instruction set table 3.1 execution order of delaye d branch instructions ................................................... 51 table 3.2 addressing modes and ef fective addresses........................................................... 53 table 3.3 notation used in in struction list............................................................................ 57 table 3.4 fixed-point transfer instructions ........................................................................... 59 table 3.5 arithmetic operatio n instructions .......................................................................... 61 table 3.6 logic operation instructions .................................................................................. 63 table 3.7 shift instru ctions..................................................................................................... 64 table 3.8 branch instructions ................................................................................................. 65 table 3.9 system control instructions.................................................................................... 66 table 3.10 floating-point single-preci sion instructions ...................................................... 69 table 3.11 floating-point double-pr ecision inst ructions..................................................... 70 table 3.12 floating-point contro l instructions .................................................................... 70 table 3.13 floating-point graphics a cceleration instructions ............................................. 71 section 4 pipelining table 4.1 representations of instruc tion execution patterns.................................................. 74 table 4.2 instruction groups .................................................................................................. 84 table 4.3 combination of preceding and following inst ructions........................................... 86 table 4.4 issue rates and ex ecution cy cles........................................................................... 88 section 5 exception handling table 5.1 register conf iguration............................................................................................ 97 table 5.2 states of register in each opera ting mode ............................................................ 97 table 5.3 exceptions............................................................................................................. 102 section 6 floating-point unit (fpu) table 6.1 floating-point number form ats and parameters .................................................. 131 table 6.2 floating-point ranges........................................................................................... 132 table 6.3 bit allocation for fpu exception hand ling......................................................... 140
rev.1.00 dec. 13, 2005 page xliv of l section 7 memory management unit (mmu) table 7.1 register config uration.......................................................................................... 156 table 7.2 register states in each processing state .............................................................. 156 section 8 caches table 8.1 cache feat ures...................................................................................................... 197 table 8.2 store queue features ............................................................................................ 197 table 8.3 register config uration.......................................................................................... 200 table 8.4 register states in each processing state .............................................................. 200 section 9 l memory table 9.1 l memory addresses............................................................................................ 227 table 9.2 register config uration.......................................................................................... 228 table 9.3 register status in each processing state .............................................................. 228 table 9.4 protective function exceptions to access l memory.......................................... 240 section 10 interrupt controller (intc) table 10.1 interrupt types...................................................................................................... 246 table 10.2 intc pin config uration ....................................................................................... 250 table 10.3 intc register co nfiguration ............................................................................... 251 table 10.4 register states in ea ch operating mode .............................................................. 253 table 10.5 interrupt request sources and int2pri0 to int2pri7....................................... 276 table 10.6 correspondence between bits in int2a0 and sources ........................................ 277 table 10.7 correspondence between bits in int2a1 and sources ........................................ 280 table 10.8 correspondence between bits in int2 mskr and interrupt masking ................. 283 table 10.9 correspondence between bits in int2mskcr and interrupt mask clearing ..... 285 table 10.10 correspondence between interrupt inpu t pins and bits in int2gpic ............. 295 table 10.11 irl[3:0], irl[7:4] pins and interrupt levels ................................................... 298 table 10.12 interrupt exceptio n handling and priority........................................................ 302 table 10.13 interrupt response time................................................................................... 311 table 10.14 switching sequence of irq/ irl[7:0] pin function ......................................... 313 section 11 local bus state controller (lbsc) table 11.1 pin configuration.................................................................................................. 318 table 11.2 lbsc external memo ry space map .................................................................... 322 table 11.3 correspondence between external pins (mode4 and mode3)......................... 324 table 11.4 correspondence between external pin (mode5) and endian ............................ 325 table 11.5 pcmcia interface features ................................................................................. 325 table 11.6 pcmcia support interface .................................................................................. 326 table 11.7 register config uration.......................................................................................... 329 table 11.8 register state in each processing mode............................................................... 330 table 11.9 32-bit external device/big-endian access and data alignment......................... 353
rev.1.00 dec. 13, 2005 page xlv of l table 11.10 16-bit external device/big-endian access and data alignment..................... 353 table 11.11 8-bit external device/big-endian access and data alignment....................... 354 table 11.12 32-bit external device/little-endian access and data alignment.................. 355 table 11.13 16-bit external device/little-endian access and data alignment.................. 355 table 11.14 8-bit external device/little-endian access and data alignment.................... 356 table 11.15 relationship between address and ce when using pcmcia interface ......... 375 table 11.16 relationship between d31 to d29 and access size in address phase ............. 383 section 12 ddr-sd ram interface (ddrif) table 12.1 pin configuration.................................................................................................. 403 table 12.2 access and data alignment in little endian mode.............................................. 406 table 12.3 access and data alignment in big endian mode................................................. 408 table 12.4 register config uration.......................................................................................... 410 table 12.5 register states in ea ch operating mode .............................................................. 411 table 12.6 sdram commands issuable by ddrif ............................................................. 426 table 12.7 relationship between split bits and address multiplexing............................... 429 section 13 pci controller (pcic) table 13.1 input/output pins.................................................................................................. 446 table 13.2 list of pcic registers .......................................................................................... 449 table 13.3 register states in ea ch operating mode .............................................................. 452 table 13.4 supported bus commands.................................................................................... 522 table 13.5 pcic address map ............................................................................................... 524 table 13.6 interrupt priority ................................................................................................... 543 section 14 direct memory access controller (dmac) table 14.1 pin configuration.................................................................................................. 559 table 14.2 register configura tion of dmac......................................................................... 561 table 14.3 register states in each processing mode ............................................................. 564 table 14.4 transfer request sources ..................................................................................... 587 table 14.5 selecting external request det ection with dl, ds bits ...................................... 589 table 14.6 selecting external request de tection with do bit .............................................. 589 table 14.7 peripheral module re quest mode s ....................................................................... 591 table 14.8 dma transfer matrix in auto-re quest mode (all channels)............................... 599 table 14.9 dma transfer matrix in external reque st mode (only channels 0 to 3)............. 600 table 14.10 dma transfer matrix in peripheral module request mode ............................ 601 table 14.11 register settings for sram, burst rom, byte control sram interface....... 611 table 14.12 register settings for pcmcia inte rface .......................................................... 612 table 14.13 register settings for mpx interface (read access)......................................... 612 table 14.14 register settings for mpx in terface (write access) ........................................ 612
rev.1.00 dec. 13, 2005 page xlvi of l section 15 clock pulse generator (cpg) table 15.1 cpg pin configuration......................................................................................... 616 table 15.2 clock operatin g modes ........................................................................................ 617 table 15.3 register config uration........................................................................................... 618 table 15.4 register states of cpg in each processing mode ................................................ 618 section 16 watchdog timer and reset table 16.1 pin configuration.................................................................................................. 627 table 16.2 register config uration.......................................................................................... 628 table 16.3 register states in each processing mode ............................................................. 628 section 17 power-down mode table 17.1 power-down modes ............................................................................................. 644 table 17.2 pin configuration.................................................................................................. 645 table 17.3 register config uration........................................................................................... 645 table 17.4 register states in each processing mode ............................................................. 645 table 17.5 pin configuration.................................................................................................. 653 section 18 timer unit (tmu) table 18.1 pin configuration.................................................................................................. 659 table 18.2 register config uration.......................................................................................... 660 table 18.3 register states in each processing mode ............................................................. 661 table 18.4 tmu interrupt sources......................................................................................... 674 section 19 timer/counter (cmt) table 19.1 pin configuration.................................................................................................. 679 table 19.2 register config uration.......................................................................................... 679 table 19.3 register states of cmt in each processing mode ............................................... 680 table 19.4 32-bit timer mode: example of input capture setting ........................................ 693 table 19.5 32-bit timer mode: example of output compare setting ................................... 696 table 19.6 16-bit timer mode: example of input capture setting ........................................ 698 table 19.7 16-bit timer mode: example of output compare setting ................................... 700 table 19.8 setting example of up -counter mode .................................................................. 702 table 19.9 setting example of updo wn-counter mode ......................................................... 704 table 19.10 setting example of updo wn-counter mode ..................................................... 706 table 19.11 cmt interrupt setting ...................................................................................... 706 section 20 realtime clock (rtc) table 20.1 rtc pins............................................................................................................... 709 table 20.2 rtc regist ers....................................................................................................... 710 table 20.3 register states of rtc in each processing mode ................................................ 711 table 20.4 crystal oscillator circuit consta nts (recommended values).............................. 730
rev.1.00 dec. 13, 2005 page xlvii of l section 21 serial communicati on interface with fifo (scif) table 21.1 pin configuration.................................................................................................. 739 table 21.2 register config uration.......................................................................................... 740 table 21.3 register states of scif in each processing mode ............................................... 741 table 21.4 scsmr settin gs ................................................................................................... 758 table 21.5 scsmr settings for serial tran sfer format se lection......................................... 770 table 21.6 scsmr and scscr settings for scif clock source selection.......................... 771 table 21.7 serial transfer formats (asynchronous mode).................................................... 773 table 21.8 scif interrup t sources ......................................................................................... 793 section 22 serial i/o with fifo (siof) table 22.1 pin configuration.................................................................................................. 799 table 22.2 register configura tion of siof............................................................................ 800 table 22.3 register states of siof in each processing mode ............................................... 801 table 22.4 operation in each transfer mode......................................................................... 804 table 22.5 siof serial cloc k frequency ............................................................................... 828 table 22.6 serial transfer modes........................................................................................... 830 table 22.7 frame length........................................................................................................ 831 table 22.8 audio mode specification for transmit data....................................................... 833 table 22.9 audio mode specification for receive data ........................................................ 833 table 22.10 setting number of channels in control data ................................................... 834 table 22.11 conditions to issue transmit request .............................................................. 836 table 22.12 conditions to issue receive request ................................................................ 836 table 22.13 transmit and recei ve reset.............................................................................. 842 table 22.14 siof interrupt sources ..................................................................................... 843 section 23 serial pr otocol interface (hspi) table 23.1 pin configuration.................................................................................................. 851 table 23.2 register config uration.......................................................................................... 851 table 23.3 register states of hspi in each processing mode ............................................... 851 section 24 multimedia card interface (mmcif) table 24.1 pin configuration.................................................................................................. 866 table 24.2 register config uration.......................................................................................... 867 table 24.3 register states of hspi in each processing mode ............................................... 869 table 24.4 cmdr configur ation ........................................................................................... 871 table 24.5 correspondence between commands and settings of cmdtyr and rsptyr ........................................................................................................ 892 table 24.6 correspondence between command response byte number and rspr............. 895 table 24.7 mmcif interrupt sources..................................................................................... 931
rev.1.00 dec. 13, 2005 page xlviii of l section 25 audio codec interface (hac) table 25.1 pin configuration.................................................................................................. 956 table 25.2 register config uration.......................................................................................... 957 table 25.3 register states of hac in each processing mode ............................................... 957 table 25.4 ac97 transmit fram e structure........................................................................... 973 table 25.5 ac97 receive fram e structur e ............................................................................ 974 section 26 serial so und interface (ssi) module table 26.1 pin configuration.................................................................................................. 984 table 26.2 register config uration.......................................................................................... 985 table 26.3 register states of ssi in each processing mode .................................................. 985 table 26.4 bus formats of ssi module.................................................................................. 998 table 26.5 number of padding bits for e ach valid config uration...................................... 1002 section 27 nand flash memory controller (flctl) table 27.1 pin configur ation................................................................................................ 1024 table 27.2 register configura tion of fl ctl ...................................................................... 1025 table 27.3 register states of flctl in each processing mode.......................................... 1025 table 27.4 status read of nand-t ype flash memory....................................................... 1049 table 27.5 flctl interrupt requests .................................................................................. 1053 table 27.6 dma transfer speci fications ............................................................................. 1053 section 28 general purpose i/o (gpio) table 28.1 multiplexed pins controlled by port control re gisters ..................................... 1056 table 28.2 register config uration ........................................................................................ 1060 table 28.3 register states of gpio in each processing mode ............................................ 1062 section 29 user break controller (ubc) table 29.1 register config uration ........................................................................................ 1103 table 29.2 register status in each processing state ............................................................ 1104 table 29.3 settings for match data setting regi ster............................................................ 1116 table 29.4 relation between operand sizes and address bits to be compared .................. 1123 section 30 user debugging interface (h-udi) table 30.1 pin configur ation................................................................................................ 1137 table 30.2 commands supported by boundary-scan tap controller ................................ 1139 table 30.3 register configur ation (1 ) .................................................................................. 1140 table 30.4 register configur ation (2 ) .................................................................................. 1140 table 30.5 register status in each processing state ............................................................ 1140 table 30.6 sdbsr configur ation ........................................................................................ 1143 section 31 electrical characteristics table 31.1 absolute maximu m ratings ............................................................................... 1155
rev.1.00 dec. 13, 2005 page xlix of l table 31.2 dc characteristics (t a = ? 20 to 75c / ? 40 to 85 c)......................................... 1156 table 31.3 permissible output currents ............................................................................... 1159 table 31.4 clock timi ng ...................................................................................................... 1159 table 31.5 clock and control signal timi ng ....................................................................... 1160 table 31.6 control signal timing ........................................................................................ 1163 table 31.7 bus timi ng ......................................................................................................... 1164 table 31.8 ddrif signal timing ........................................................................................ 1182 table 31.9 intc module signa l timing .............................................................................. 1186 table 31.10 pcic signal timing (in pcireq/pci gnt non-port mode) (1)................... 1188 table 31.11 dmac module sign al timi ng ....................................................................... 1190 table 31.12 tmu module signa l timing .......................................................................... 1191 table 31.13 cmt module signa l timing .......................................................................... 1192 table 31.14 scif module si gnal timing........................................................................... 1193 table 31.15 siof modu le signal ti ming .......................................................................... 1195 table 31.16 hspi module si gnal timing .......................................................................... 1199 table 31.17 mmcif module si gnal timi ng...................................................................... 1201 table 31.18 hac interface module signal timing............................................................ 1203 table 31.19 ssi interface module signal timing .............................................................. 1205 table 31.20 flctl modu le signal timing ....................................................................... 1207 table 31.21 gpio signal timing ....................................................................................... 1211 table 31.22 h-udi module signal timing........................................................................ 1212 appendix table f.1 clock operating modes with ex ternal pin comb ination.................................... 1256 table f.2 area 0 memory map and bus width.................................................................. 1256 table f.3 endian ................................................................................................................. 1256 table f.4 pci mode ............................................................................................................ 1257 table f.5 clock inpu t ......................................................................................................... 1257 table f.6 mode cont rol...................................................................................................... 1257 table g.1 pin states in reset, power-down st ate, and bus-rel eased state........................ 1258 table g.2 treatment of un used pins................................................................................... 1267 table i.1 register config uration ........................................................................................ 1276 table j.1 sh7780 produc t lineup ...................................................................................... 1277
rev.1.00 dec. 13, 2005 page l of l
section 1 overview rev.1.00 dec. 13, 2005 page 1 of 1286 rej09b0158-0100 section 1 overview 1.1 sh7780 features the sh7780 is an integrated system-on-a-chip micr oprocessor that is designed as a high performance, embedded, stand-alone host proces sor aimed at the multimedia, infotainment and consumer networking market. th e sh7780 features a ddr-sdram interface that can be coupled to the ddr320* or 266 sdram. also, because of its built-in functions, such as a pci bus controller, a dma controller, timer s, and serial communications func tions with an audio interface, as required for multimedia, network, and oa equipment, use of the sh7780 enables a high performance and high integrated system. the sh7780 contains the new generation sh-4a 32-bit risc (reduced instruction set computer) microprocessor core which runs at 400 mhz (720 mips, 2.8 gflops). the sh-4a is upwardly compatible with the sh-1, sh-2, sh-3, and sh-4 microcomputers at the instruction set level. this microprocessor core integrates a cache memory and the mmu. note: "ddr320" indicates the ddr-sdram bus inte rface which operates at a frequency of 160 mhz in this manual. the features of th e sh7780 are summarized in table 1.1.
section 1 overview rev.1.00 dec. 13, 2005 page 2 of 1286 rej09b0158-0100 table 1.1 sh7780 features item features lsi ? operating frequency: 400 mhz ? performance: 720mips, 2.8 gflops ? voltage: 1.25 v (interna l), 2.5 v (ddr-sdram interface), 3.3 v (i/o) ? superscalar architecture: parallel execution of two instructions ? packages: 449-pin bga (size: 21 21 mm, pin pitch: 0.8 mm) ? local bus interface (external bus): ? separate 26-bit address and 32-bit data buses ? external bus frequency: 100 mhz ? ddr-sdram bus interface (external bus): ? separate 14-bit address and 32-bit data buses ? external bus frequency: 133 m or 160 mhz (ddr266/320) ? pci bus interface (external bus): ? 32-bit address/data multiplexing ? external bus frequency: 33m or 66 mhz cpu ? renesas technology original architecture ? 32-bit internal data bus ? general-register files: ? sixteen 32-bit general registers (eight 32-bit shadow registers) ? seven 32-bit control registers ? four 32-bit system registers ? risc-type instruction set (upward co mpatible with the sh-1, sh-2, sh-3 and sh-4 microcomputers) ? instruction length: 16-bit fixed length for improved code efficiency ? load/store architecture ? delayed branch instructions ? instructions executed with conditions ? instruction set based on the c language ? super scalar which executes two instructions simultaneously including the fpu ? instruction execution time: tw o instructions per cycle (max) ? virtual address space: 4 gbytes ? space identifier asid: 8 bits, 256 virtual address spaces ? on-chip multiplier ? seven-stage pipeline
section 1 overview rev.1.00 dec. 13, 2005 page 3 of 1286 rej09b0158-0100 item features fpu ? on-chip floating-point coprocessor ? supports single-precision (32 bits) and double-precision (64 bits) ? supports ieee754-compliant data types and exceptions ? two rounding modes: round to nearest and round to zero ? handling of denormalized numbers: truncation to zero or interrupt generation for ieee754 compliance ? floating-point registers: 32 bits 16 words 2 banks (single-precision 16 words or double-precision 8 words) 2 banks ? 32-bit cpu-fpu floating-point communication register (fpul) ? supports fmac (multiply- and-accumulate) instruction ? supports fdiv (divide) and fsqrt (square root) instructions ? supports fldi0/fldi1 (load c onstant 0/1) instructions ? instruction execution times ? latency (fadd/fsub): 3 cycles (single-precision), 5 cycles (double- precision) ? latency (fmac/ fmul): 5 cycles (single-precision), 7 cycles (double- precision) ? pitch (fadd/fsub): 1 cycle (singl e-precision/doubl e-precision) ? pitch (fmac/fmul): 1 cycle (singl e-precision), 3 cycles (double- precision) note: fmac is supported for single-precision only. ? 3-d graphics instructions (single-precision only): ? 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 8 cycles (latency) ? 4-dimensional vector (fipr) inner product: 1 cycle (pitch), 5 cycles (latency) ? ten-stage pipeline
section 1 overview rev.1.00 dec. 13, 2005 page 4 of 1286 rej09b0158-0100 item features memory management unit (mmu) ? 4 gbytes of physical address spac e, 256 address space identifiers (address space identifier asid: 8 bits) ? supports single virtual memory mode and multiple virtual memory mode ? supports multiple page sizes: 1 kbyt e, 4 kbytes, 64 kbytes, or 1 mbyte ? 4-entry full associative tlb for instructions ? 64-entry full associative tlb for instructions and operands ? supports software selection of r eplacement method and random-counter replacement algorithms ? contents of tlb are directly accessible through address mapping cache memory ? instruction cache (ic) ? 32-kbyte 4-way set associative ? 32-byte block length ? operand cache (oc) ? 32-kbyte 4-way set associative ? 32-byte block length ? selectable write method (copy-back or write-through) ? storage queue (32 bytes 2 entries) l memory ? three independent read/write ports ? instruction fetch access by the cpu ? 8-/16-/32-/64-bit operand access by the cpu ? 8-/16-/32-/64-bit and 16-/32-byte access by the superhyway bus master ? 16-kbyte capacity ? supports memory protective functions during cpu accesses superhyway memory ? 8-/16-/32-/64-bit and 16-/32-byte access from the superhyway bus master ? 32-kbyte capacity
section 1 overview rev.1.00 dec. 13, 2005 page 5 of 1286 rej09b0158-0100 item features interrupt controller (intc) ? nine independent external interrupts: nmi and irq7 to irq0 ? nmi: fall/rise selectable ? irq: fall/rise/high level/low level selectable ? 15-level signed external interrupts: irl3 to irl0 , or irl7 to irl4 ? on-chip module interrupts: priority level can be set for each module the following modules can issue on-chip module interrupts: tmu, rtc, scif, wdt, h-udi, dmac, cmt, hac, pcic, siof, hspi, mmcif, ssi, flctl, and gpio user break controller (ubc) ? supports debugging by means of user break interrupts ? two break channels ? address, data value, access type, and data size are available as break condition settings ? supports sequential break functions local bus state controller (lbsc) ? supports external memory access ? external memory space divided into seven areas, each of up to 64 mbytes, with the following parameters settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (hardware wait function also supported) ? sram or burst rom ? supports pcmcia interface (only in little endian mode) ? big endian or little endian mode can be set ddr-sdram interface (ddrif) ? the data bus width of the ddrif is 32 bits ? supports ddr-sdram self-refreshing ? supports the ddr320 or ddr266 sdram ? efficient data transfer is possible using the superhyway bus(internal bus) ? supports a 4-bank ddr-sdram ? supports a burst length of 2 ? connectable memory size: 256-mb it, 512-mbit, 1-gbit, and 2-gbit
section 1 overview rev.1.00 dec. 13, 2005 page 6 of 1286 rej09b0158-0100 item features pci bus controller (pcic) ? pci bus controller (subset of revision 2.2) ? 32-bit bus ? 33 mhz/66 mhz support ? pci master/target support ? pci host function support ? built-in bus arbiter ? interrupt requests can be sent to cpu ? up to 512-mbyte memory can be connected for pci memory space direct memory access controller (dmac) ? 12-channel physical address dma controller ? 4-channel supports external requests (channel 0 to 3) ? address space: 4 gbytes on architecture ? transfer data size: 8, 16, or 32 bits; 16, or 32 bytes ? address modes: ? 2-bus-cycle dual address mode ? transfer requests: external (channel 0 to 3), peripheral module (channel 0 to 5), or auto-requests ? choice of dack or drak (four external pins) ? bus modes: cycle-steal or burst mode clock pulse generator (cpg) ? main clock: 12 times xtal clock ? clock modes: ? cpu frequency: 1/1 time main clock ? local bus frequency: 1/4, 1/6, 1/8, or 1/12 times main clock ? ddr-sdram frequency: 2/5 or 1/3 times main clock (supports ddr320 or ddr266 sdram devices) ? peripheral frequency: 1/8 or 1/12 times main clock ? power-down modes: ? sleep mode ? module standby mode watchdog timer (wdt) ? single-channel watchdog timer (watchdog timer mode or interval timer mode can be selectable) ? selectable reset function: power-on reset or manual reset
section 1 overview rev.1.00 dec. 13, 2005 page 7 of 1286 rej09b0158-0100 item features timer unit (tmu) ? 6-channel auto-reload 32-bit timer ? input-capture function (only channel 2) ? choice of seven types counter input clocks (external and peripheral clocks) compare match timer (cmt) ? 4-channel auto-reload 32-bit timers ? choice of 16 or 32 bits ? choice of 1-shot or free-running operation ? choice of an interrupt source or dma transfer request from compare match or overflow realtime clock (rtc) ? on-chip clock and calendar functions ? built-in 32 khz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) ? rtc power supply back-up function serial communication interface (scif) ? two full-duplex communications channels ? on-chip 64-byte fifos for all channels ? choice of asynchronous mode or synchronous mode ? can select any bit rate generated by on-chip baud-rate generator ? on-chip modem control function ( scif0_rts and scif0_cts ) for channel 0 serial i/o with fifo (siof) ? internal 64-byte transmit/receive fifos ? supports 8-/16-bit data and 16-bit stereo audio input/output ? sampling rate clock input selectable from pck and external pin ? maximum sampling rate: 48-khz ? internal prescaler for pck serial protocol interface (hspi) ? 1 channel ? master/slave mode ? selectable bit rate generated by on-chip baud-rate generator multimedia card interface (mmcif) ? complies with the multimedia card system specificat ion version 3.1 ? supports mmc mode ? interface with mcclk output for transfer clock output, mccmd i/o for command output/response input, mcdat i/o (data i/o) ? four interrupt sources
section 1 overview rev.1.00 dec. 13, 2005 page 8 of 1286 rej09b0158-0100 item features audio codec interface (hac) ? digital interface for audio codec ? supports transfer for slot 1 to slot 4 ? choice of 16- or 20-bit dma transfer ? supports various sampling rates by adjusting slot data ? generates interrupt: data ready, dat a request, overflow, and underrun serial sound interface (ssi) ? 1-channel bi-directional transfer ? support compressed-data and non-compressed-data transfer ? the compressed mode is used for continuous bit stream transfer ? the non-compressed mode supports all serial audio streams divided into channels. ? the ssi module is configured as any of a transmitter or receiver. the serial bus format can be used in the compressed and non-compressed mode. nand flash memory controller (flctl) ? interface connectable to a nand-type flash memory ? read or write in sector units (512 + 16 bytes) ? read or write in byte units ? supports up to 512-mbit of flash memory general purpose i/o (gpio) ? 83 general purpose i/o ports (75 for i/os and 8 for outputs) ? gpio interrupts are supported debug interface ? h-udi (user debugging interface) ? aud (advanced user debugger)
section 1 overview rev.1.00 dec. 13, 2005 page 9 of 1286 rej09b0158-0100 1.2 block diagram cpu i-cache lbsc (external bus) [legend] aud: cmt: cpg: cpu: ddrif: dmac: flctl: fpu: gpio: hac: hpb: hspi: h-udi: i-cache: intc: lbsc: lram: mmcif: mmu: o-cache: pcic: rtc: advanced user debugger timer/counter clock pulse generator central processing unit ddr-sdram interface direct memory access controller nand flash memory controller floating-point unit general purpose i/o audio codec peripheral bus bridge serial protocol interface user debugging interface instruction cache interrupt controller local bus state controller l memory multimedia card interface memory management unit operand (data) cache pci controller realtime clock scif: siof: ssi: superhyway ram: tmu: ubc: wdt: serial communication interface with fifo serial i/o with fifo serial sound interface superhyway memory timer unit user break controller watchdog timer fpu mmu o-cache lram sh-4a core ubc aud instruction bus operand bus ddrif (external bus) pcic (external bus) i/o multiplexed i/o multiplexed i/o multiplexed hpb tmu scif channel 0 hspi flctl scif channel 1 mmcif siof hac ssi gpio cpg wdt rtc cmt h-udi intc dmac superhyway ram superhyway router peripheral bus superhyway bus figure 1.1 sh7780 block diagram
section 1 overview rev.1.00 dec. 13, 2005 page 10 of 1286 rej09b0158-0100 1.3 pin arrangement 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae 23456789101112131415161718192021222324 25 vssq-ddr vssq-ddr mda0 mda1 mda2 mda3 mda4 mda5 mda7 mdqm0 mdqs1 mda8 mda9 mda10 mda11 mda13 mda15 vccq-ddr a25 a22 a19 a16 a14 a13 vssq vccq-ddr vccq-ddr vccq-ddr mda16 mda17 mda19 mda21 mda23 mda6 mdqs0 mdqm1 mda24 mda26 mda28 mda30 mda12 mda14 vccq-ddr a23 a20 a17 a15 vddq a12 ddr-vref bkprst vssq-ddr vssq-ddr mda18 mda20 mda22 mdqs2 mdqm2 mdqs3 mdqm3 mda25 mda27 mda29 mda31 vssq-ddr vssq-ddr vccq-ddr a24 a21 a18 vddq a11 a10 mclk cke vccq-ddr vccq-ddr vccq-ddr vccq-ddr vss vdd vdd-dll1 vdd vdd vdd-dll2 vssq-ddr vccq-ddr vccq-ddr vssq-ddr vssq-ddr vccq-ddr vdd vss vddq vssq a9 a8 a7 mclk ma13 ma12 vssq-ddr vssq-ddr vssq-ddr vss vdd vss-dll1 vss vss vss-dll2 vssq-ddr vccq-ddr vccq-ddr vccq-ddr vssq-ddr vccq-ddr vdd vss vssq a6 a5 a4 a3 mwe mcas ma11 vssq-ddr vssq-ddr mras mcs ma9 vccq-ddr vccq-ddr ba0 ba1 ma8 vccq-ddr vdd ma10 ma0 ma7 vssq-ddr vss ma1 ma2 ma6 vssq-ddr vssq-ddr ma3 ma4 ma5 vccq-ddr vccq-ddr preset vss vssq vssq drak0 / mode2 drak1 / mode7 drak2 / ce2a / audck drak3 / ce2b / audsync vddq vddq dreq2 / intb / audata0 dreq3 / intc / audata1 dack2 / mresetout / audata2 scif1_txd /mcclk /mode5 scif0_rts / hspi_cs / fse scif0_cts / intd /fcle siof_sync/ hac_sync/ ssi_ws scif0_rxd hspi_rx/ frb siof_rxd/ hac_sdin/ ssi_sck scif0_txd hspi_tx fwe /mode8 siof_txd/ hac_sdout/ ssi_sdata dack3 / irqout / audata3 dack0 / mode0 audsync / fce audck /fale audata3 /fd3 audata2 /fd2 dack1 / mode1 vddq vdd vssq vss vss vss vss vss vss vss vss vss (top view) vss vss vss vss vss vss vss vss vss-ddr vss-ddr vss-ddr vss vss vss vssq vssq vssq vssq vssq vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vddq asebrk /brkack audata1/ fd1 audata0/ fd0 siof_sck/ hac_bitclk/ ssi_clk siof_mclk / hac_res scif1_rxd mcdat scif1_sck /mccmd vddq vddq xtal2 req0 / reqout vssq vddq vssq vss vdd vdd vddq vss vss vdd vddq vdd vdd vss vss vddq vssq vdd vss-pll2 vdd-pll3 vdd-pll2 tms tck vssq dreq0 dreq1 tdi tdo trst vssq vss a2 a1 a0 d31 vdd d30 d29 d28 d27 vddq d26 d25 d24 vssq d23 d22 d21 d20 vss vssq d19 d18 d17 vdd vddq d15 d16 vddq vddq d14 d13 d12 vssq vssq d11 d10 d9 vssq vddq d8 d7 we1 vdd vddq d6 d5 d4 vss vssq d3 d2 d1 vddq back breq d0 vddq cs4 bs rd / frmae r /w vssq cs6 cs5 cs2 rdy vssq vss-pll3 cs1 cs0 clkout vdd vdd vddq ad1 ad7 ad10 ad14 serr lock irdy ad17 ad21 cbe3 ad27 ad31 req2 nc * vddq vdd vss-pll1 vdd-pll1 extal2 vdd-rtc xrtcstbi vddq irq/ irl6 / fd6/ mode6 irq/ irl3 irq/ irl0 ad5 ad2 ad6 ad9 ad13 par trdy ad16 ad20 idsel ad26 ad30 gnt2 gnt0/ gntin vss vss vddq vddq extal vdd irq/ irl1 irq/ irl4 / fd4/ mode3 ad3 ad8 ad12 cbe1 perr devsel cbe2 ad19 ad23 ad25 ad29 req3 req1 pciclk nc * vddq vddq vssq xtal tclk/ iois16 scif0_sck/ hspi_clk/ fre vss-rtc vssq irq/ irl7 / fd7 irq/ irl5 / fd5/ mode4 irq/ irl2 nmi ad0 ad4 cbe0 ad11 ad15 stop pciframe ad18 ad22 ad24 ad28 gnt3 gnt1 pcireset inta vss mpmd vssq vssq status0/ cmt_ctr0 status1/ cmt_ctr1 we3 / iowr we2 / iord we0 / reg figure 1.2 sh7780 pin arrangement
section 1 overview rev.1.00 dec. 13, 2005 page 11 of 1286 rej09b0158-0100 1.4 pin functions table 1.2 lists the pin functions of the sh7780. in the i/o column, i, o, and io indicate input, output, and input/output, respectively. in the gpio column, for example, a0 indicates the port a0, which also functions as a general i/o port (input/output). table 1.2 pin functions no. pin no. pin name i/o function gpio * 1 a1 vssq-ddr ? ddr i/o gnd 2 a2 vccq-ddr ? ddr i/o vcc 3 a3 ddr-vref i ddr vref 4 a4 mclk o ddr clock 5 a5 mclk o ddr clock 6 a6 mwe o ddr write enable 7 a7 mras o ddr ras 8 a8 ba0 o ddr bank address 0 9 a9 ma10 o ddr address 10 a10 ma1 o ddr address 11 a11 ma3 o ddr address 12 a12 preset i power-on reset 13 a13 drak1 /mode7 o/i dma channel 1 transfer request acknowledge/mode control 7 l0(o) 14 a14 dreq0 i dma channel 0 request k7 15 a15 dreq3 / intc /audata1 i/i/o dma channel 3 request/ pci interrupt c/h-udi emulator k4 * 16 a16 dack2 / mresetout /audata2 o/o/o dma channel 2 bus acknowledgment/manual reset output/ h-udi emulator k3 17 a17 tdi i h-udi data 18 a18 audsync/ fce o/o h-udi emulator/nand flash ce 19 a19 audata1/fd1 o/io h-udi emulator/nand flash data 20 a20 siof_sync/hac_sync/ssi_ws io/o/io siof flame synchronous/ hac flame synchronous/ssi word select j3
section 1 overview rev.1.00 dec. 13, 2005 page 12 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 21 a21 scif1_txd/mcclk/mode5 o/o/i scif 1 transmit data/ card clock output/mode control 5 h6(o) 22 a22 xtal2 o rtc clock 23 a23 extal2 i rtc crystal resonator 24 a24 vdd-rtc ? rtc vdd 25 a25 vss-rtc ? rtc gnd 26 b1 vssq-ddr ? ddr i/o gnd 27 b2 vccq-ddr ? ddr i/o vcc 28 b3 bkprst i back-up reset 29 b4 cke o ddr clock enable 30 b5 ma13 o ddr address 31 b6 mcas o ddr cas 32 b7 mcs o ddr chip select 33 b8 ba1 o ddr bank address 1 34 b9 ma0 o ddr address 35 b10 ma2 o ddr address 36 b11 ma4 o ddr address 37 b12 vss ? internal gnd 38 b13 drak2 / ce2a /audck o/o/o dma channel 2 transfer request acknowledge/pcmcia ce2/ h-udi emulator k1(o) 39 b14 dreq1 i dma channel 1 request k6 40 b15 dack0 /mode0 o/i dma channel 0 bus acknowledgement/mode control 0 l3(o) 41 b16 dack3 / irqout /audata3 o/o/o dma channel 3 bus acknowledgement/ interrupt request output/h-udi emulator k2 42 b17 tdo o h-udi data 43 b18 audck/fale o/o h-udi emulator/nand flash ale 44 b19 audata0/fd0 o/io h-udi emulator/nand flash data 45 b20 siof_rxd/hac_sdin/ssi_sck i/i/io siof receive data/hac serial data incoming to rx frame/ ssi serial bit clock j4 46 b21 scif1_sck/mccmd io/io scif1 serial clock/ mmcif command response h7
section 1 overview rev.1.00 dec. 13, 2005 page 13 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 47 b22 scif0_rxd/hspi_rx/frb i/i/i scif receive data/hspi receive data input/nand flash ready or busy h2 48 b23 tclk/ iois16 io/i tmu clock/pcmcia iois16 j0 * 49 b24 xrtcstbi i rtc standby 50 b25 vssq ? i/o gnd 51 c1 mda0 io ddr data 52 c2 vccq-ddr ? ddr i/o vcc 53 c3 vssq-ddr ? ddr i/o gnd 54 c4 vccq-ddr ? ddr i/o vcc 55 c5 ma12 o ddr address 56 c6 ma11 o ddr address 57 c7 ma9 o ddr address 58 c8 ma8 o ddr address 59 c9 ma7 o ddr address 60 c10 ma6 o ddr address 61 c11 ma5 o ddr address 62 c12 drak0 /mode2 o/i dma channel 0 transfer request acknowledge/mode control 2 l1(o) 63 c13 drak3 / ce2b /audsync o/o/o dma channel 3 request acknowledgment/pcmcia ce2/ h-udi emulator k0(o) 64 c14 dreq2 / intb /audata0 i/i/o dma channel 2 request/pci interrupt b/h-udi emulator k5 * 65 c15 dack1 /mode1 o/i dma channel 1 bus acknowledgement/mode control 1 l2(o) 66 c16 tck i h-udi clock 67 c17 asebrk /brkack i/o h-udi emulator 68 c18 audata3/fd3 o/io h-udi emulator/nand flash data 69 c19 siof_sck/hac_bitclk/ssi_clk io/i/io siof serial clock/hac/ssi serial bit clock j1 70 c20 siof_txd/hac_sdout/ ssi_sdata o/o/io siof transmit data/hac serial data/ ssi serial data j5 71 c21 scif0_rts / hspi_cs / fse io/io/o scif modem control/hspi chip selection/nand flash spare area enable h0 *
section 1 overview rev.1.00 dec. 13, 2005 page 14 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 72 c22 scif0_txd/hspi_tx/ fwe /mode8 o/o/o/i scif0 transmit data/hspi transmit data/nand flash write enable/ mode control 8 h3(o) 73 c23 scif0_sck/hspi_clk/ fre io/io/o scif0 serial clock/hspi serial clock/nand flash read enable h4 74 c24 vddq ? i/o vdd 75 c25 irq/ irl7 /fd7 i/io irl irq interrupt request 7/ nand flash data e6 * 76 d1 mda1 io ddr data 77 d2 mda16 io ddr data 78 d3 vssq-ddr ? ddr i/o gnd 79 d4 vccq-ddr ? ddr i/o vcc 80 d5 vssq-ddr ? ddr i/o gnd 81 d6 vssq-ddr ? ddr i/o gnd 82 d7 vccq-ddr ? ddr i/o vcc 83 d8 vccq-ddr ? ddr i/o vcc 84 d9 vssq-ddr ? ddr i/o gnd 85 d10 vssq-ddr ? ddr i/o gnd 86 d11 vccq-ddr ? ddr i/o vcc 87 d12 vssq ? i/o gnd 88 d13 vddq ? i/o vdd 89 d14 vddq ? i/o vdd 90 d15 vssq ? i/o gnd 91 d16 tms i h-udi emulator 92 d17 trst i h-udi emulator 93 d18 audata2/fd2 o/io h-udi emulator/nand flash data 94 d19 siof_mclk/ hac_res i/o siof master clock/hac reset j2 95 d20 scif1_rxd/mcdat i/io scif1 receive data/mmcif data h5 96 d21 scif0_cts / intd /fcle io/i/o scif modem control/pci interrupt d /nand flash command latch enable h1 * 97 d22 vdd ? internal vdd
section 1 overview rev.1.00 dec. 13, 2005 page 15 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 98 d23 vdd ? internal vdd 99 d24 irq/ irl6 /fd6/mode6 i/io/i irl irq interrupt request 6/nand flash data/mode control 6 100 d25 irq/ irl5 /fd5/mode4 i/io/i irl irq interrupt request 5/nand flash data/mode control 4 101 e1 mda2 io ddr data 102 e2 mda17 io ddr data 103 e3 mda18 io ddr data 104 e4 vccq-ddr ? ddr i/o vcc 105 e5 vssq-ddr ? ddr i/o gnd 106 e6 vssq-ddr ? ddr i/o gnd 107 e7 vccq-ddr ? ddr i/o vcc 108 e8 vdd ? internal vdd 109 e9 vss ? internal gnd 110 e10 vssq-ddr ? ddr i/o gnd 111 e11 vccq-ddr ? ddr i/o vcc 112 e12 vssq ? i/o gnd 113 e13 vddq ? i/o vdd 114 e14 vdd ? internal vdd 115 e15 vss ? internal gnd 116 e16 vssq ? i/o gnd 117 e17 vssq ? i/o gnd 118 e18 vddq ? i/o vdd 119 e19 vddq ? i/o vdd 120 e20 vddq ? i/o vdd 121 e21 vssq ? i/o gnd 122 e22 vdd ? internal vdd 123 e23 irq/ irl4 /fd4/mode3 i/io/i irl irq interrupt request 4/ nand flash data/mode control 3 124 e24 irq/ irl3 i irl irq interrupt request 3 125 e25 irq/ irl2 i irl irq interrupt request 2
section 1 overview rev.1.00 dec. 13, 2005 page 16 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 126 f1 mda3 io ddr data 127 f2 mda19 io ddr data 128 f3 mda20 io ddr data 129 f4 vccq-ddr ? ddr i/o vcc 130 f5 vssq-ddr ? ddr i/o gnd 131 f21 vddq ? i/o vdd 132 f22 vddq ? i/o vdd 133 f23 irq/ irl1 i irl irq interrupt request 1 134 f24 irq/ irl0 i irl irq interrupt request 0 135 f25 nmi i nonmaskable interrupt 136 g1 mda4 io ddr data 137 g2 mda21 io ddr data 138 g3 mda22 io ddr data 139 g4 vss ? internal gnd 140 g5 vss ? internal gnd 141 g21 vssq ? i/o gnd 142 g22 ad1 io pci address/data d1 143 g23 ad3 io pci address/data d3 144 g24 ad5 io pci address/data d5 145 g25 ad0 io pci address/data d0 146 h1 mda5 io ddr data 147 h2 mda23 io ddr data 148 h3 mdqs2 io ddr data strobe 149 h4 vdd ? internal vdd 150 h5 vdd ? internal vdd 151 h21 vss ? internal gnd 152 h22 ad7 io pci address/data d7 153 h23 ad8 io pci address/data c0 154 h24 ad2 io pci address/data d2 155 h25 ad4 io pci address/data d4
section 1 overview rev.1.00 dec. 13, 2005 page 17 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 156 j1 mda7 io ddr data 157 j2 mda6 io ddr data 158 j3 mdqm2 o ddr data mask 159 j4 vdd-dll1 ? dll1 vdd 160 j5 vss-dll1 ? dll1 gnd 161 j21 vdd ? internal vdd 162 j22 ad10 io pci address/data c2 163 j23 ad12 io pci address/data c4 164 j24 ad6 io pci address/data d6 165 j25 cbe0 io pci command/byte enable 166 k1 mdqm0 o ddr data mask 167 k2 mdqs0 io ddr data strobe 168 k3 mdqs3 io ddr data strobe 169 k4 vdd ? internal vdd 170 k5 vss ? internal gnd 171 k10 vss ? internal gnd 172 k11 vss ? internal gnd 173 k12 vss ? internal gnd 174 k13 vss ? internal gnd 175 k14 vss ? internal gnd 176 k15 vss ? internal gnd 177 k16 vss ? internal gnd 178 k21 vdd ? internal vdd 179 k22 ad14 io pci address/data c6 180 k23 cbe1 io pci command/byte enable 181 k24 ad9 io pci address/data c1 182 k25 ad11 io pci address/data c3 183 l1 mdqs1 io ddr data strobe 184 l2 mdqm1 o ddr data mask
section 1 overview rev.1.00 dec. 13, 2005 page 18 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 185 l3 mdqm3 o ddr data mask 186 l4 vdd ? internal vdd 187 l5 vss ? internal gnd 188 l10 vss ? internal gnd 189 l11 vss ? internal gnd 190 l12 vss ? internal gnd 191 l13 vssq ? i/o gnd 192 l14 vss ? internal gnd 193 l15 vss ? internal gnd 194 l16 vss ? internal gnd 195 l21 vddq ? i/o vdd 196 l22 serr io pci system error 197 l23 perr io pci parity error 198 l24 ad13 io pci address/data c5 199 l25 ad15 io pci address/data c7 200 m1 mda8 io ddr data 201 m2 mda24 io ddr data 202 m3 mda25 io ddr data 203 m4 vdd-dll2 ? dll2 vdd 204 m5 vss-dll2 ? dll2 gnd 205 m10 vss ? internal gnd 206 m11 vss ? internal gnd 207 m12 vssq-ddr ? ddr i/o gnd 208 m13 vssq ? i/o gnd 209 m14 vss ? internal gnd 210 m15 vss ? internal gnd 211 m16 vss ? internal gnd 212 m21 vss ? internal gnd 213 m22 lock io pci lock 214 m23 devsel io pci device select
section 1 overview rev.1.00 dec. 13, 2005 page 19 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 215 m24 par io pci parity 216 m25 stop io pci transaction stop 217 n1 mda9 io ddr data 218 n2 mda26 io ddr data 219 n3 mda27 io ddr data 220 n4 vssq-ddr ? ddr i/o gnd 221 n5 vssq-ddr ? ddr i/o gnd 222 n10 vss ? internal gnd 223 n11 vss ? internal gnd 224 n12 vssq-ddr ? ddr i/o gnd 225 n13 vssq ? i/o gnd 226 n14 vss ? internal gnd 227 n15 vss ? internal gnd 228 n16 vss ? internal gnd 229 n21 vss ? internal gnd 230 n22 irdy io pci initiator ready 231 n23 cbe2 io pci command/byte enable 232 n24 trdy io pci target ready 233 n25 pciframe io pci cycle frame 234 p1 mda10 io ddr data 235 p2 mda28 io ddr data 236 p3 mda29 io ddr data 237 p4 vccq-ddr ? ddr i/o vcc 238 p5 vccq-ddr ? ddr i/o vcc 239 p10 vss ? internal gnd 240 p11 vss ? internal gnd 241 p12 vssq-ddr ? ddr i/o gnd 242 p13 vssq ? i/o gnd 243 p14 vss ? internal gnd 244 p15 vss ? internal gnd
section 1 overview rev.1.00 dec. 13, 2005 page 20 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 245 p16 vss ? internal gnd 246 p21 vdd ? internal vdd 247 p22 ad17 io pci address/data b1 248 p23 ad19 io pci address/data b3 249 p24 ad16 io pci address/data b0 250 p25 ad18 io pci address/data b2 251 r1 mda11 io ddr data 252 r2 mda30 io ddr data 253 r3 mda31 io ddr data 254 r4 vccq-ddr ? ddr i/o vcc 255 r5 vccq-ddr ? ddr i/o vcc 256 r10 vss ? internal gnd 257 r11 vss ? internal gnd 258 r12 vss ? internal gnd 259 r13 vssq ? i/o gnd 260 r14 vss ? internal gnd 261 r15 vss ? internal gnd 262 r16 vss ? internal gnd 263 r21 vddq ? i/o vdd 264 r22 ad21 io pci address/data b5 265 r23 ad23 io pci address/data b7 266 r24 ad20 io pci address/data b4 267 r25 ad22 io pci address/data b6 268 t1 mda13 io ddr data 269 t2 mda12 io ddr data 270 t3 vssq-ddr ? ddr i/o gnd 271 t4 vssq-ddr ? ddr i/o gnd 272 t5 vccq-ddr ? ddr i/o vcc 273 t10 vss ? internal gnd 274 t11 vss ? internal gnd
section 1 overview rev.1.00 dec. 13, 2005 page 21 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 275 t12 vss ? internal gnd 276 t13 vss ? internal gnd 277 t14 vss ? internal gnd 278 t15 vss ? internal gnd 279 t16 vss ? internal gnd 280 t21 vdd ? internal vdd 281 t22 cbe3 io pci command/byte enable 282 t23 ad25 io pci address/data a1 283 t24 idsel i pci configuration device select 284 t25 ad24 io pci address/data a0 285 u1 mda15 io ddr data 286 u2 mda14 io ddr data 287 u3 vssq-ddr ? ddr i/o gnd 288 u4 vssq-ddr ? ddr i/o gnd 289 u5 vssq-ddr ? ddr i/o gnd 290 u21 vdd ? internal vdd 291 u22 ad27 io pci address/data a3 292 u23 ad29 io pci address/data a5 293 u24 ad26 io pci address/data a2 294 u25 ad28 io pci address/data a4 295 v1 vccq-ddr ? ddr i/o vcc 296 v2 vccq-ddr ? ddr i/o vcc 297 v3 vccq-ddr ? ddr i/o vcc 298 v4 vccq-ddr ? ddr i/o vcc 299 v5 vccq-ddr ? ddr i/o vcc 300 v21 vss ? internal gnd 301 v22 ad31 io pci address/data a7 302 v23 req3 i bus request (pci host) e3 * 303 v24 ad30 io pci address/data a6 304 v25 gnt3 o pci bus grant e0 *
section 1 overview rev.1.00 dec. 13, 2005 page 22 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 305 w1 a25 o address bus 306 w2 status0/cmt_ctr0 o/io status0/cmt0 timer counter 307 w3 status1/cmt_ctr1 o/io status1/cmt1 timer counter 308 w4 vdd ? internal vdd 309 w5 vdd ? internal vdd 310 w21 vss ? internal gnd 311 w22 req2 i bus request (pci host) e4 * 312 w23 req1 i bus request (pci host) e5 * 313 w24 gnt2 o pci bus grant e1 * 314 w25 gnt1 o pci bus grant e2 * 315 y1 a22 o address bus 316 y2 a23 o address bus 317 y3 a24 o address bus 318 y4 vss ? internal gnd 319 y5 vss ? internal gnd 320 y21 vddq ? i/o vdd 321 y22 req0 / reqout i/o bus request (pci host)/ bus request output 322 y23 pciclk i pci input clock 323 y24 gnt0 / gntin o/i pci bus grant 324 y25 pcireset o pci reset 325 aa1 a19 o address bus 326 aa2 a20 o address bus 327 aa3 a21 o address bus 328 aa4 vddq ? i/o vdd 329 aa5 vssq ? i/o gnd 330 aa6 vss ? internal gnd 331 aa7 vdd ? internal vdd 332 aa8 vddq ? i/o vdd 333 aa9 vssq ? i/o gnd
section 1 overview rev.1.00 dec. 13, 2005 page 23 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 334 aa10 vss ? internal gnd 335 aa11 vdd ? internal vdd 336 aa12 vddq ? i/o vdd 337 aa13 vssq ? i/o gnd 338 aa14 vssq ? i/o gnd 339 aa15 vdd ? internal vdd 340 aa16 vss ? internal gnd 341 aa17 vddq ? i/o vdd 342 aa18 vddq ? i/o vdd 343 aa19 vssq ? i/o gnd 344 aa20 vssq ? i/o gnd 345 aa21 vssq ? i/o gnd 346 aa22 nc ? open 347 aa23 nc ? open 348 aa24 vss ? internal gnd 349 aa25 inta io pci interrupt a 350 ab1 a16 o address bus 351 ab2 a17 o address bus 352 ab3 a18 o address bus 353 ab4 vssq ? i/o gnd 354 ab5 a6 o address bus 355 ab6 a2 o address bus 356 ab7 d30 io data bus f6 357 ab8 d26 io data bus f2 358 ab9 d23 io data bus g7 359 ab10 vssq ? i/o gnd 360 ab11 vddq ? i/o vdd 361 ab12 vddq ? i/o vdd 362 ab13 vssq ? i/o gnd 363 ab14 vddq ? i/o vdd
section 1 overview rev.1.00 dec. 13, 2005 page 24 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 364 ab15 vddq ? i/o vdd 365 ab16 vssq ? i/o gnd 366 ab17 back o bus acknowledgement m0 367 ab18 cs4 o chip select 4 368 ab19 cs6 o chip select 6 369 ab20 vss-pll3 ? pll3 gnd 370 ab21 vdd ? internal vdd 371 ab22 vddq ? i/o vdd 372 ab23 vddq ? i/o vdd 373 ab24 vss ? internal gnd 374 ab25 vss ? internal gnd 375 ac1 a14 o address bus 376 ac2 a15 o address bus 377 ac3 vddq ? i/o vdd 378 ac4 a9 o address bus 379 ac5 a5 o address bus 380 ac6 a1 o address bus 381 ac7 d29 io data bus f5 382 ac8 d25 io data bus f1 383 ac9 d22 io data bus g6 384 ac10 d19 io data bus g3 385 ac11 d15 io data bus 386 ac12 d14 io data bus 387 ac13 d11 io data bus 388 ac14 d8 io data bus 389 ac15 d6 io data bus 390 ac16 d3 io data bus 391 ac17 breq i bus request m1 392 ac18 bs o bus start 393 ac19 cs5 o chip select 5
section 1 overview rev.1.00 dec. 13, 2005 page 25 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 394 ac20 cs1 o chip select 1 395 ac21 vss-pll2 ? pll2 gnd 396 ac22 vdd ? internal vdd 397 ac23 vddq ? i/o vdd 398 ac24 vddq ? i/o vdd 399 ac25 mpmd i mode control 400 ad1 a13 o address bus 401 ad2 vddq ? i/o vdd 402 ad3 a11 o address bus 403 ad4 a8 o address bus 404 ad5 a4 o address bus 405 ad6 a0 o address bus 406 ad7 d28 io data bus f4 407 ad8 d24 io data bus f0 408 ad9 d21 io data bus g5 409 ad10 d18 io data bus g2 410 ad11 d16 io data bus g0 411 ad12 d13 io data bus 412 ad13 d10 io data bus 413 ad14 d7 io data bus 414 ad15 d5 io data bus 415 ad16 d2 io data bus 416 ad17 d0 io data bus 417 ad18 rd / frame o read strobe/mpx interface cycle frame 418 ad19 cs2 o chip select 2 419 ad20 cs0 o chip select 0 420 ad21 vdd-pll3 ? pll3 vdd 421 ad22 vss-pll1 ? pll1 gnd 422 ad23 vssq ? i/o gnd 423 ad24 vddq ? i/o vdd
section 1 overview rev.1.00 dec. 13, 2005 page 26 of 1286 rej09b0158-0100 no. pin no. pin name i/o function gpio * 424 ad25 vssq ? i/o gnd 425 ae1 vssq ? i/o gnd 426 ae2 a12 o address bus 427 ae3 a10 o address bus 428 ae4 a7 o address bus 429 ae5 a3 o address bus 430 ae6 d31 io data bus f7 431 ae7 d27 io data bus f3 432 ae8 we3 / iowr o/o selection signal for d31 to d24 433 ae9 d20 io data bus g4 434 ae10 d17 io data bus g1 435 ae11 we2 / iord o/o selection signal for d23 to d16/pcmcia iord 436 ae12 d12 io data bus 437 ae13 d9 io data bus 438 ae14 we1 o selection signal for d15 to d8 439 ae15 d4 io data bus 440 ae16 d1 io data bus 441 ae17 we0 / reg o/o selection signal for d7 to d0/pcmcia reg 442 ae18 r/ w o read/write 443 ae19 rdy i bus ready 444 ae20 clkout o clock output 445 ae21 vdd-pll2 ? pll2 vdd 446 ae22 vdd-pll1 ? pll1 vdd 447 ae23 xtal o crystal resonator 448 ae24 extal i external input clock/crystal resonator 449 ae25 vssq ? i/o gnd note: * can be used as a gpio interrupt pin. (o) only outputs.
section 1 overview rev.1.00 dec. 13, 2005 page 27 of 1286 rej09b0158-0100 1.5 memory address map the sh7780 supports 32-bit virtual address space, and suppor ts both 29-bit and 32-bit physical address spaces (normal mode and extended mode). for details of mappings from the virtual address space to the phy sical address spaces, see section 7, memory management unit (mmu). the external memory space of the sh7780 consists of the lb sc space, ddrif space and pcic space. the lbsc has up to 384 mb ytes, the ddrif has up to 256 mb ytes and the pcic has up to 512 mbytes external memory sp ace individually and the sh7780 can control the external memory space up to 1152 mbytes totally. ar eas 0, 1, and 6 are controlled by the lbsc. areas 2, 4, and 5 are controlled by the lbsc, ddrif or pcic that depends on the setting of the memory address map select register (mmselr) of the lbsc. note that area 3 is for the ddrif. for details, see section 11, local bus sate controller (lbsc), section 12, ddr-sdram interface (ddrif) or section 13, pci controller (pcic). figure 1.3 shows the physical address space of the sh7780. figure 1.4 shows the relationship between the areasel bits and the memory address map. th e 32-bit physical address space corresponds with th e address space of the superhyway bus.
section 1 overview rev.1.00 dec. 13, 2005 page 28 of 1286 rej09b0158-0100 area 0 (lbsc) area 1 (lbsc) area 2 (lbsc/ddrif) area 3 (ddrif) area 4 (lbsc/ddrif/pcic) area 5 (lbsc/ddrif) area 6 (lbsc) area 7 (reserved) (undefined) ddr-sdram (ddrif) (undefined) pci (pcic) (internal resources) h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'2000 0000 h'4000 0000 h'8000 0000 h'c000 0000 h'e000 0000 h'ffff ffff h'fc00 0000 h'fc80 0000 h'fd00 0000 h'fe00 0000 h'fe40 0000 h'fe80 0000 h'ff00 0000 h'ff40 0000 h'ff80 0000 h'ffc0 0000 control register area (h'fc00 0000 to h'ffff ffff) 32-bit physical address space (extended mode) h'e000 0000 h'e500 0000 h'f000 0000 29-bit physical address space (normal mode) note: for details of these areas, refer to section 7.1.1, address spaces. h-udi (8mb) dmac (8mb) pci memory (16mb) pcic (4mb) superhyway ram (4mb) ddrif (8mb) cpu (4mb) superhyway router (4mb) lbsc (4mb) peripheral modules (4mb) store queue area (64mb) * on-chip memory area (16mb) * cache, tlb and pmb address /data array area (128mb) * figure 1.3 physical address space of sh7780
section 1 overview rev.1.00 dec. 13, 2005 page 29 of 1286 rej09b0158-0100 area 0 (lbsc) area 1 (lbsc) area 2 (lbsc/ddrif) area 3 (ddrif) area 4 (lbsc/ddrif/pcic) area 5 (lbsc/ddrif) area 6 (lbsc) area 7 (reserved area) (undefined) ddr-sdram (ddrif) (undefined) pci (pcic) (internal resources) lbsc lbsc lbsc ddrif-1 lbsc lbsc lbsc lbsc lbsc lbsc ddrif-1 pcic lbsc lbsc ddrif-0 : shadow ddrif-2 ddrif-3 pcic pcic pcic pcic pcic lbsc lbsc ddrif-0 ddrif-1 lbsc lbsc lbsc lbsc lbsc ddrif-0 ddrif-1 pcic lbsc lbsc lbsc lbsc ddrif-0 ddrif-1 ddrif-2 ddrif-3 lbsc ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-1 h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'2000 0000 h'4000 0000 h'4400 0000 h'4800 0000 h'4c00 0000 h'5000 0000 h'5400 0000 h'5800 0000 h'5c00 0000 h'6000 0000 h'6400 0000 h'6800 0000 h'6c00 0000 h'7000 0000 h'7400 0000 h'7800 0000 h'7c00 0000 h'8000 0000 h'c000 0000 h'e000 0000 h'ffff ffff 32-bit physical address space (extended mode) 29-bit physical address space (normal mode) note: memory address map select register (mmselr) area select bit (areasel) for details, refer to section 11.4.1, memory address map select register (mmselr). mmselr.areasel[2:0] * b'000 b'001 b'010 b'011 b'100 figure 1.4 relationship between areasel bits and memory address map
section 1 overview rev.1.00 dec. 13, 2005 page 30 of 1286 rej09b0158-0100 1.6 superhyway bus the sh7780 is implemented with the superhyway bus as the system bus. the superhyway bus is a 32-bit-address, 64-bit-data internal bus capable of up to 200 mhz operation that is connected to on-chip modules to allow high speed communication. each module that is connected to the superhyway bus operates as an initiator (i.e. , bus master) that issues a transfer request or a target that replies with a response to the request. the transaction is controlled by the dedicated superhyway router. the cpu, pcic, and dmac modules can all operate as an initiator. the lru method is used to decide the request priority of the superhyway bus mastership. the initial request priority order is: cpu > dmac > pcic. the response priority level is fixed: peripheral modules* > dmac > cpu > superhyway ram > lbsc > pcic > ddrif. note that when using debugging function (h- udi emulator), the debugging functional module has the highest priority. the transfer data size varies with each module. for details, refer to the corresponding section for each module. an actual transaction on the superhyway bus is started from a request issued by the initiator module according to a read/write command sent to the superhyway bus address (physical address), and then the target module replies with a response to the request (load/store transaction). in addition, a tran saction that controls the cache coherency occurs if necessary (flush/purge transaction). note that these transactions are done automatically by the superhyway modules, so they cannot be explicitly issued by software. note: "peripheral modules" means modules that ar e connected to the peripheral bus (except for the intc and dmac modules).
section 1 overview rev.1.00 dec. 13, 2005 page 31 of 1286 rej09b0158-0100 1.7 superhyway memory (superhyway ram) the sh7780 includes an on-chip superhyway memory which stores instructions or data. the superhyway memory has the following features. ? capacity total superhyway memory capacity is 32 kbytes (512 words 256 bits 2 pages). ? memory address map the superhyway memory is allo cated within the physical addr ess h'fe41 0000 to h'fe41 3fff and h'fe42 0000 to h'fe42 3fff. ? ports each page has one common read and write port, and is connected to the superhyway bus via a 4-stage buffer respectively. high-speed access to the superhyway memory is enabled by the superhyway bus master. ? access the superhyway memory is always accessed by the superhyway bus master module, including the cpu, via the superhyway bus which is a physical address bus. 1-/2-/4-/8-/16-/32-byte access is possible for both reading and writing (with wraparound on 32-byte boundary data). a 32-byte cache fill can be read out with one access (an 8-byte 4 transfer on the superhyway bus). note that the read/write operation on the superhyway bus is done with one clock. after that the bus is released. ? minimum access time 1-/2-/4-/8-byte read access: 14 clock cycles; 1-/2-/4-/8-byte write access: 12 clock cycles 16-/32-byte read access: 17 clock cycles; 16-/32-byte write access: 15 clock cycles (the superhyway clock 200 mhz) ? usage note a superhyway bus master module, such as dmac, can access the superhyway memory in sleep mode.
section 1 overview rev.1.00 dec. 13, 2005 page 32 of 1286 rej09b0158-0100
section 2 programming model rev.1.00 dec. 13, 2005 page 33 of 1286 rej09b0158-0100 section 2 programming model the programming model of this lsi is explained in this section. this lsi has registers and data formats as shown below. 2.1 data formats the data formats supported in this lsi are shown in figure 2.1. byte (8 bits) word (16 bits) longword (32 bits) single-precision floating-point (32 bits) double-precision floating-point (64 bits) 0 7 0 15 0 31 0 31 30 22 se f 0 63 62 51 se f [legend] s: e: f: sign field exponent field fraction field figure 2.1 data formats
section 2 programming model rev.1.00 dec. 13, 2005 page 34 of 1286 rej09b0158-0100 2.2 register descriptions 2.2.1 privileged mode and banks processing modes: this lsi has two processing modes, user mode and privileged mode. this lsi normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. there ar e four kinds of registers?genera l registers, system registers, control registers, and floating-poi nt registers?and the registers th at can be accessed differ in the two processing modes. general registers: there are 16 general registers, designated r0 to r15. general registers r0 to r7 are banked registers which are switched by a pr ocessing mode change. ? ?
section 2 programming model rev.1.00 dec. 13, 2005 page 35 of 1286 rej09b0158-0100 floating-point registers and system registers related to fpu: there are thirty-two floating- point registers, fr0?fr15 and xf0?xf15. fr0?fr15 and xf0?xf15 can be assigned to either of two banks (fpr0_bank0?fpr15_bank0 or fpr0_bank1?fpr15_bank1). fr0?fr15 can be used as the eight registers dr0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers fv0/4/8/12 (register vectors), while xf0? xf15 can be used as the eight registers xd0/2/4/6/8/10/12/14 (register pairs) or register matrix xmtrx. system registers related to the fpu comprise th e floating-point communication register (fpul) and the floating-point status/control register (fpscr). these registers are used for communication between the fpu and the cpu, and the exception handling setting. register values after a reset are shown in table 2.1. table 2.1 initial register values type registers initial value * general registers r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, r8 to r15 undefined sr md bit = 1, rb bit = 1, bl bit = 1, fd bit = 0, imask = b'1111, reserved bits = 0, others = undefined gbr, ssr, spc, sgr, dbr undefined control registers vbr h'00000000 mach, macl, pr undefined system registers pc h'a0000000 fr0 to fr15, xf0 to xf15, fpul undefined floating-point registers fpscr h'00040001 note: * initialized by a power-on reset and manual reset. the cpu register configuration in each processing mode is shown in figure 2.2. user mode and privileged mode are switched by the processing mode bit (md) in the status register.
section 2 programming model rev.1.00 dec. 13, 2005 page 36 of 1286 rej09b0158-0100 31 0 r0 _ bank0 * 1, * 2 r1 _ bank0 * 2 r2 _ bank0 * 2 r3 _ bank0 * 2 r4 _ bank0 * 2 r5 _ bank0 * 2 r6 _ bank0 * 2 r7 _ bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc (a) register configuration in user mode 31 0 r0 _ bank1 * 1, * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1, * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (b) register configuration in privileged mode (rb = 1) gbr mach macl vbr pr sr ssr pc spc 31 0 r0 _ bank1 * 1, * 3 r1 _ bank1 * 3 r2 _ bank1 * 3 r3 _ bank1 * 3 r4 _ bank1 * 3 r5 _ bank1 * 3 r6 _ bank1 * 3 r7 _ bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 r0 _ bank0 * 1, * 4 r1 _ bank0 * 4 r2 _ bank0 * 4 r3 _ bank0 * 4 r4 _ bank0 * 4 r5 _ bank0 * 4 r6 _ bank0 * 4 r7 _ bank0 * 4 (c) register configuration in privileged mode (rb = 0) gbr mach macl vbr pr sr ssr pc spc sgr dbr sgr dbr r0 is used as the index register in indexed register-indirect addressing mode and indexed gbr indirect addressing mode. banked registers banked registers accessed as general registers when the rb bit is set to 1 in sr. accessed only by ldc/stc instructions when the rb bit is cleared to 0. banked registers accessed as general registers when the rb bit is cleared to 0 in sr. accessed only by ldc/stc instructions when the rb bit is set to 1. notes: 1. 2. 3. 4. figure 2.2 cpu register configuration in each processing mode
section 2 programming model rev.1.00 dec. 13, 2005 page 37 of 1286 rej09b0158-0100 2.2.2 general registers figure 2.3 shows the relationship between the processing modes and general registers. this lsi has twenty-four 32-bit general registers (r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, and r8 to r15). howeve r, only 16 of these can be accessed as general registers r0 to r15 in one processing mode. this lsi has two processing modes, user mode and privileged mode. ? ? sr.md = 0 or (sr.md = 1, sr.rb = 0) r0_bank0 r1_bank0 r2_bank0 r3_bank0 r4_bank0 r5_bank0 r6_bank0 r7_bank0 r0 _ bank0 r1 _ bank0 r2 _ bank0 r3 _ bank0 r4 _ bank0 r5 _ bank0 r6 _ bank0 r7 _ bank0 r0_bank1 r1_bank1 r2_bank1 r3_bank1 r4_bank1 r5_bank1 r6_bank1 r7_bank1 r0 _ bank1 r1 _ bank1 r2 _ bank1 r3 _ bank1 r4 _ bank1 r5 _ bank1 r6 _ bank1 r7 _ bank1 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 r8 r9 r10 r11 r12 r13 r14 r15 (sr.md = 1, sr.rb = 1) figure 2.3 general registers
section 2 programming model rev.1.00 dec. 13, 2005 page 38 of 1286 rej09b0158-0100 note on programming: as the user's r0 to r7 are assigned to r0_bank0 to r7_bank0, and after an exception or interrupt r0 to r7 are assigned to r0_bank1 to r7_bank1, it is not necessary for the interrupt handler to save and restore the user's r0 to r7 (r0_bank0 to r7_bank0). 2.2.3 floating-point registers figure 2.4 shows the floating-point register conf iguration. there are thirty-two 32-bit floating- point registers, fpr0_bank0 to fpr15_bank0, and fpr0_bank1 to fpr15_bank1, comprising two banks. these registers are referenced as fr0 to fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0 to xf15, xd0/2/4/6/8/10/12/14, or xmtrx. reference names of each register are defined depending on the state of the fr bit in fpscr (see figure 2.4). 1. floating-point registers, fprn_banki (32 registers) fpr0_bank0 to fpr15_bank0 fpr0_bank1 to fpr15_bank1 2. single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0 to fr15 are a ssigned to fpr0_bank0 to fpr15_bank0; when fpscr.fr = 1, fr0 to fr15 are a ssigned to fpr0_bank1 to fpr15_bank1. 3. double-precision floating-point registers or single-precision floating-point registers, dri (8 registers): a dr register co mprises two fr registers. dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} 4. single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers. fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} 5. single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0 to xf15 are assigned to fpr0_bank1 to fpr15_bank1; when fpscr.fr = 1, xf0 to xf15 are assigned to fpr0_bank0 to fpr15_bank0. 6. double-precision floating-point extended registers, xdi (8 registers): an xd register comprises two xf registers. xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15}
section 2 programming model rev.1.00 dec. 13, 2005 page 39 of 1286 rej09b0158-0100 7. single-precision floating-point extended register matrix, xmtrx: xmtrx comprises all 16 xf registers. xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 fpr0_bank0 fpr1_bank0 fpr2_bank0 fpr3_bank0 fpr4_bank0 fpr5_bank0 fpr6_bank0 fpr7_bank0 fpr8_bank0 fpr9_bank0 fpr10_bank0 fpr11_bank0 fpr12_bank0 fpr13_bank0 fpr14_bank0 fpr15_bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0_bank1 fpr1_bank1 fpr2_bank1 fpr3_bank1 fpr4_bank1 fpr5_bank1 fpr6_bank1 fpr7_bank1 fpr8_bank1 fpr9_bank1 fpr10_bank1 fpr11_bank1 fpr12_bank1 fpr13_bank1 fpr14_bank1 fpr15_bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr=0 fpscr.fr=1 figure 2.4 floating-point registers
section 2 programming model rev.1.00 dec. 13, 2005 page 40 of 1286 rej09b0158-0100 2.2.4 control registers status register (sr): 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0111000000000000 md rb bl fd m q imask s t initial value: rr/wr/wr/wrrrrrrrrrrrr r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: 0000000011110000 initial value: r/w r r r r r r/w r/w r/w r/w r/w r/w r r r/w r/w r/w: bit bit name initial value r/w description 31 ? 0 r reserved for details on reading/writing this bit, see general precautions on handling of product. 30 md 1 r/w processing mode selects the processing mode. 0: user mode (some instruct ions cannot be executed and some resources cannot be accessed.) 1: privileged mode this bit is set to 1 by an exception or interrupt. 29 rb 1 r/w privileged mode general register bank specification bit 0: r0_bank0 to r7_bank0 are accessed as general registers r0 to r7 and r0_bank1 to r7_bank1 can be accessed using ldc/stc instructions 1: r0_bank1 to r7_bank1 are accessed as general registers r0 to r7 and r0_bank0?r7_bank0 can be accessed using ldc/stc instructions this bit is set to 1 by an exception or interrupt. 28 bl 1 r/w exception/interrupt block bit this bit is set to 1 by a reset, an exception, or an interrupt. while this bit is set to 1, an interrupt request is masked. in this case, this processor enters the reset state when a general exception other than a user break occurs.
section 2 programming model rev.1.00 dec. 13, 2005 page 41 of 1286 rej09b0158-0100 bit bit name initial value r/w description 27 to 16 ? all 0 r reserved for details on reading/writing this bit, see general precautions on handling of product. 15 fd 0 r/w fpu disable bit when this bit is set to 1 and an fpu instruction is not in a delay slot, a general fpu disable exception occurs. when this bit is set to 1 and an fpu instruction is in a delay slot, a slot fpu disable exception occurs. (fpu instructions: h'f *** instructions and lds (.l)/sts(.l) instructions using fpul/fpscr) 14 to 10 ? all 0 r reserved for details on reading/writing this bit, see general precautions on handling of product. 9 m 0 r/w m bit used by the div0s, div0u, and div1 instructions. 8 q 0 r/w q bit used by the div0s, div0u, and div1 instructions. 7 to 4 imask all 1 r/w interrupt mask level bits an interrupt whose priority is equal to or less than the value of the imask bits is masked. it can be chosen by cpu operation mode register (cpuopm) whether the level of imask is changed to accept an interrupt or not when an interrupt is occurred. for details, see appendix a, cpu operation mode register (cpuopm). 3, 2 ? all 0 r reserved for details on reading/writing this bit, see general precautions on handling of product. 1 s 0 r/w s bit used by the mac instruction. 0 t 0 r/w t bit indicates true/false condition, carry/borrow, or overflow/underflow. for details, see section 3, instruction set.
section 2 programming model rev.1.00 dec. 13, 2005 page 42 of 1286 rej09b0158-0100 saved status register (ssr) (32 bits, privileged mode, initial value = undefined): the contents of sr are saved to ssr in the event of an exception or interrupt. saved program counter (spc) (32 bits, priv ileged mode, initial value = undefined): the address of an instruction at which an interrupt or exception occurs is saved to spc. global base register (gbr) (32 bits, initial value = undefined): gbr is referenced as the base address of addressing @(disp,gbr) and @(r0,gbr). vector base register (vbr) (32 bits, priv ileged mode, initial value = h'00000000): vbr is referenced as the branch destination base address in the event of an exception or interrupt. for details, see section 5, exception handling. saved general register 15 (sgr) (32 bits, pr ivileged mode, initial value = undefined): the contents of r15 are saved to sgr in the event of an exception or interrupt. debug base register (dbr) (32 bits, priv ileged mode, initial value = undefined): when the user break debugging function is enabled (cbcr.ub de = 1), dbr is referenced as the branch destination address of the user break handler instead of vbr. 2.2.5 system registers multiply-and-accumulate re gisters (mach and macl) (32 bits, initial value = undefined): mach and macl are used for the added va lue in a mac instruct ion, and to store the operation result of a mac or mul instruction. procedure register (pr) (32 bits, initial value = undefined): the return address is stored in pr in a subroutine call using a bsr, bsrf, or jsr instruction. pr is refe renced by the subroutine return instruction (rts). program counter (pc) (32 bits, initial value = h'a0000000): pc indicates the address of the instruction currently being executed.
section 2 programming model rev.1.00 dec. 13, 2005 page 43 of 1286 rej09b0158-0100 floating-point status/control register (fpscr) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000100 rrrrrrrrrrr/wr/wr/wr/wr/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000001 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w enable (en) fr sz pr dn flag rm cause cause bit: initial value: r/w: bit: initial value: r/w: bit bit name initial value r/w description 31 to 22 ? all 0 r reserved for details on reading/writing this bit, see general precautions on handling of product. 21 fr 0 r/w floating-point register bank 0: fpr0_bank0 to fpr15_bank0 are assigned to fr0 to fr15 and fpr0_bank1 to fpr15_bank1 are assigned to xf0 to xf15 1: fpr0_bank0 to fpr15_bank0 are assigned to xf0 to xf15 and fpr0_bank1 to fpr15_bank1 are assigned to fr0 to fr15 20 sz 0 r/w transfer size mode 0: data size of fmov instruction is 32-bits 1: data size of fmov instruction is a 32-bit register pair (64 bits) for relationship between the sz bit, pr bit, and endian, see figure 2.5. 19 pr 0 r/w precision mode 0: floating-point instruct ions are executed as single-precision operations 1: floating-point instruct ions are executed as double-precision operations (graphics support instructions are undefined) for relationship between the sz bit, pr bit, and endian, see figure 2.5 18 dn 1 r/w denormalization mode 0: denormalized number is treated as such 1: denormalized number is treated as zero
section 2 programming model rev.1.00 dec. 13, 2005 page 44 of 1286 rej09b0158-0100 bit bit name initial value r/w description 17 to 12 cause all 0 r/w 11 to 7 enable (en) all 0 r/w 6 to 2 flag all 0 r/w fpu exception cause field fpu exception enable field fpu exception flag field each time an fpu operation in struction is executed, the fpu exception cause field is cleared to 0. when an fpu exception occurs, the bits corresponding to fpu exception cause field and flag field are set to 1. the fpu exception flag field remains set to 1 until it is cleared to 0 by software. for bit allocations of each field, see table 2.2. 1, 0 rm 01 r/w rounding mode these bits select the rounding mode. 00: round to nearest 01: round to zero 10: reserved 11: reserved
section 2 programming model rev.1.00 dec. 13, 2005 page 45 of 1286 rej09b0158-0100 dr (2i) fr (2i) fr (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 floating-point register memory area 63 0 floating-point register memory area dr (2i) fr (2i) fr (2i+1) 4n 4m 4n+3 4m+3 63 0 63 32 31 0 dr (2i) fr (2i+1) fr (2i) 8n+4 8n+7 8n+3 8n 63 0 63 32 31 0 (1) sz = 0 (2) sz = 1, pr = 0 63 0 63 0 dr (2i) fr (2i+1) fr (2i) 8n 8n+3 8n+7 8n+4 63 0 63 32 31 0 (3) sz = 1, pr = 1 63 0 * 1, * 2 * 2 notes: 1. in the case of sz = 0 and pr = 0, dr register can not be used. 2. the bit-location of dr register is used for double precision format when pr = 1. (in the case of (2), it is used when pr is changed from 0 to 1.) figure 2.5 relationship between sz bit and endian table 2.2 bit allocation for fpu exception handling field name fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2 floating-point communication register (fpu l) (32 bits, initial value = undefined): information is transferred betw een the fpu and cpu via fpul.
section 2 programming model rev.1.00 dec. 13, 2005 page 46 of 1286 rej09b0158-0100 2.3 memory-mapped registers some control registers are mapped to the following memory areas. each of the mapped registers has two addresses. h'1c00 0000 to h'1fff ffff h'fc00 0000 to h'ffff ffff these two areas are used as follows. ? ?
section 2 programming model rev.1.00 dec. 13, 2005 page 47 of 1286 rej09b0158-0100 2.4 data formats in registers register operands are always longwords (32 bits). when a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 ss s 0 6 7 6 7 0 31 ss s 0 14 15 14 15 0 figure 2.6 formats of byte data and word data in register
section 2 programming model rev.1.00 dec. 13, 2005 page 48 of 1286 rej09b0158-0100 2.5 data formats in memory memory data formats are classifi ed into bytes, words, and longwords. memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. a memory operand less than 32 bits in length is sign-extended before being loaded into a register. a word operand must be accessed starting from a word boundary (e ven address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). an address error will result if this rule is not observed. a byte operand can be accessed from any address. big endian or little endian byte order can be selected for the data format. the endian should be set with the external pin after a power-on reset. the endian cannot be changed dynamically. bit positions are numbered left to right from most-significant to least-significant. thus, in a 32-bit longword, the leftmost bit, bit 31, is the most signifi cant bit and the rightmost bit, bit 0, is the least significant bit. the data format in memory is shown in figure 2.7. address a a 70707070 31 15 0 15 0 31 0 15 0 31 0 23 15 7 0 a + 1 a + 2 a + 3 byte 0 word 0 longword word 1 byte 1 byte 2 byte 3 a + 11 70707070 31 15 0 23 15 7 0 a + 10 a + 9 a + 8 byte 3 word 1 longword word 0 byte 2 byte 1 byte 0 address a + 4 address a + 8 address a + 8 address a + 4 address a big endian little endian figure 2.7 data formats in memory for the 64-bit data format, see figure 2.5.
section 2 programming model rev.1.00 dec. 13, 2005 page 49 of 1286 rej09b0158-0100 2.6 processing states this lsi has major three processing states: the re set state, instruction ex ecution state, and power- down state. reset state: in this state the cpu is reset. the reset state is divided into the power-on reset state and the manual reset. in the power-on reset state, th e internal state of the cpu and the on-chip peripheral module registers are initialized. in the manual reset state, the internal state of the cpu and some registers of on-chip peripheral modules are initialized. for deta ils, see register descriptions for each section. instruction execution state: in this state, the cpu executes program instructions in sequence. the instruction execution state ha s the normal program execution state and the exception handling state. power-down state: in a power-down state, the cpu halts operation and power consumption is reduced. the power-down state is entered by ex ecuting a sleep instruction. this lsi supports sleep mode for the po wer-down state. from any state when reset/manual reset input reset state instruction execution state sleep instruction execution power-down state interrupt occurence reset/manual reset clearance reset/manual reset input reset/manual reset input figure 2.8 processing state transitions
section 2 programming model rev.1.00 dec. 13, 2005 page 50 of 1286 rej09b0158-0100 2.7 usage note 2.7.1 notes on self-modified codes* this lsi prefetches instructions more drastic ally than conventional sh-4 to accelerate the processing speed. therefore if the instruction in the memory is modified and it is executed immediately, then the pre- modified code that is prefetched are likely to be executed. in order to execute the modified code defin itely, one of the following sequences should be executed between the execution of modifying codes and modified codes. (1) in case the modified code s are in non-cacheable area synco icbi @rn the target for the icbi instruct ion can be any address within the range where no address error exception occurs. (2) in case the modified codes are in cacheable area (write-through) synco icbi @rn the all instruction cache area corresponding to the modified codes should be invalidated by the icbi instruction. the icbi instru ction should be issued to each cache line. one cache line is 32 bytes. (3) in case the modified codes are in cacheable area (copy-back) ocbp @rm or ocbwb @rm synco icbi @rn the all operand cache area corresponding to the modified codes should be written back to the main memory by the ocbp or ocbwb instruction. then th e all instruction cache area corresponding to the modified codes should be invalidated by the icbi instruction. the ocbp, ocbwb and icbi instruction should be issued to each cache line. one cache line is 32 bytes. note: * processes executed while changing th e instructions on the memory dynamically.
section 3 instruction set rev.1.00 dec. 13, 2005 page 51 of 1286 rej09b0158-0100 section 3 instruction set this lsi's instruction set is implemented with 16-bit fixed-length instructions. this lsi can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. single-precision floating- point data (32 bits) can be moved to and from memory using longword or quadword size. double-precision floating-point data (64 bits) can be moved to and from memory using longword size. when this lsi moves byte-size or word-size data from memory to a register, the data is sign-extended. 3.1 execution environment pc: at the start of instruction execution, the pc in dicates the address of the instruction itself. load-store architecture: this lsi has a load-store architectur e in which operations are basically executed using registers. except for bit-manipulation operations such as logical and that are executed directly in me mory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. delayed branches: except for the two branch instructions bf and bt, this lsi's branch instructions and rte are delayed branches. in a delayed branch, the instruction following the branch is executed before the branch destination instruction. delay slot: this execution slot following a delayed branch is called a delay slot. for example, the bra execution sequence is as follows: table 3.1 execution order of delayed branch instructions instructions execution order bra target (delayed branch instruction) bra add (delay slot) : add : target target-inst (branch dest ination instruction) target-inst a slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. for details, see section 5, exception handling. the instruction following bf/s or bt/s for which the branch is not taken is also a delay slot instruction.
section 3 instruction set rev.1.00 dec. 13, 2005 page 52 of 1286 rej09b0158-0100 t bit: the t bit in sr is used to show the result of a compare operation, and is referenced by a conditional branch instruction. an example of the use of a conditional branch instruction is shown below. add #1, r0 ; t bit is not changed by add operation cmp/eq r1, r0 ; if r0 = r1, t bit is set to 1 bt target ; branches to ta rget if t bit = 1 (r0 = r1) in an rte delay slot, the sr bits are referenced as follows. in instruction access, the md bit is used before modification, and in data access, the md bit is accessed after modifi cation. the other bits?s, t, m, q, fd, bl, and rb?after modification are used for delay slot instruction execution. the stc and stc.l sr instructio ns access all sr bits after modification. constant values: an 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a pc-relative load instruction. mov.w @(disp, pc), rn mov.l @(disp, pc), rn there are no pc-relative load instructions for floati ng-point operations. however, it is possible to set 0.0 or 1.0 by using the fldi0 or fldi1 instruction on a single-precision floating-point register.
section 3 instruction set rev.1.00 dec. 13, 2005 page 53 of 1286 rej09b0158-0100 3.2 addressing modes addressing modes and effective address calculation methods are shown in table 3.2. when a location in virtual memory space is accessed (a t in mmucr = 1), the effective address is translated into a physical memory address. if multiple virtual memory sp ace systems are selected (sv in mmucr = 0), the least signi ficant bit of pteh is also re ferenced as the access asid. for details, see section 7, memory management unit (mmu). table 3.2 addressing modes and effective addresses addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn ea (ea: effective address) register indirect with post- increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn rn 1/2/4/8 + rn + 1/2/4/8 rn ea after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn quadword: rn + 8 rn register indirect with pre- decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. rn 1/2/4/8 rn ? 1/2/4/8 ? rn ? 1/2/4/8 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn quadword: rn ? 8 rn rn ea (instruction executed with rn after calculation)
section 3 instruction set rev.1.00 dec. 13, 2005 page 54 of 1286 rej09b0158-0100 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp ea word: rn + disp 2 ea longword: rn + disp 4 ea indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 ea gbr indirect with displace- ment @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp ea word: gbr + disp 2 ea longword: gbr + disp 4 ea indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0 ea
section 3 instruction set rev.1.00 dec. 13, 2005 page 55 of 1286 rej09b0158-0100 addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8, pc) effective address is pc + 4 with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc h'ffff fffc pc + 4 + disp 2 or pc & h'ffff fffc + 4 + disp 4 + 4 2/4 + & * disp (zero-extended) * with longword operand word: pc + 4 + disp 2 ea longword: pc & h'ffff fffc + 4 + disp 4 ea pc-relative disp:8 effective address is pc + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (sign-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target
section 3 instruction set rev.1.00 dec. 13, 2005 page 56 of 1286 rej09b0158-0100 addressing mode instruction format effective address calculation method calculation formula pc-relative disp:12 effective address is pc + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. 2 + disp (sign-extended) 4 + pc pc + 4 + disp 2 pc + 4 + disp 2 branch- target rn effective address is sum of pc + 4 and rn. pc 4 rn + + pc + 4 + rn pc + 4 + rn branch-target immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for the addressing modes below that use a di splacement (disp), the assembler descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed according to the operand size. this is done to clarify the oper ation of the lsi. refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, gbr) ; gbr i ndirect with displacement @ (disp:8, pc) ; pc-relative with displacement disp:8, disp:1 2 ; pc-relative
section 3 instruction set rev.1.00 dec. 13, 2005 page 57 of 1286 rej09b0158-0100 3.3 instruction set table 3.3 shows the notation used in the sh instruction lists shown in tables 3.4 to 3.13. table 3.3 notation used in instruction list item format description instruction mnemonic op.sz src, dest op: operation code sz: size src: source operand dest: source and/or destination operand rm: source register rn: destination register imm: immediate data disp: displacement operation notation , transfer direction (xx) memory operand m/q/t sr flag bits & logical and of individual bits | logical or of individual bits logical exclusive-or of individual bits ~ logical not of individual bits <>n n-bit shift instruction code msb ? lsb mmmm: register number (rm, frm) nnnn: register number (rn, frn) 0000: r0, fr0 0001: r1, fr1 : 1111: r15, fr15 mmm: register number (drm, xdm, rm_bank) nnn: register number (drn, xdn, rn_bank) 000: dr0, xd0, r0_bank 001: dr2, xd2, r1_bank : 111: dr14, xd14, r7_bank mm: register number (fvm) nn: register number (fvn) 00: fv0 01: fv4 10: fv8 11: fv12 iiii: immediate data dddd: displacement
section 3 instruction set rev.1.00 dec. 13, 2005 page 58 of 1286 rej09b0158-0100 item format description privileged mode "privileged" means the instruction can only be executed in privileged mode. t bit value of t bit after instruction execution ?: no change new ? "new" means the instruction which is newly added in this lsi. note: scaling ( 1, 2, 4, or 8) is executed according to the size of the instruction operand.
section 3 instruction set rev.1.00 dec. 13, 2005 page 59 of 1286 rej09b0158-0100 table 3.4 fixed-point transfer instructions instruction operation instruction code privileged t bit new mov #imm,rn imm sign extension rn 1110nnnniiiiiiii ? ? ? mov.w @(disp * ,pc),rn (disp 2 + pc + 4) sign extension rn 1001nnnndddddddd ? ? ? mov.l @(disp * ,pc),rn (disp 4 + pc & h'ffff fffc + 4) rn 1101nnnndddddddd ? ? ? mov rm,rn rm rn 0110nnnnmmmm0011 ? ? ? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 ? ? ? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 ? ? ? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 ? ? ? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 ? ? ? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 ? ? ? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 ? ? ? mov.b rm,@-rn rn-1 rn, rm (rn) 0010nnnnmmmm0100 ? ? ? mov.w rm,@-rn rn-2 rn, rm (rn) 0010nnnnmmmm0101 ? ? ? mov.l rm,@-rn rn-4 rn, rm (rn) 0010nnnnmmmm0110 ? ? ? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 ? ? ? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 ? ? ? mov.l @rm+,rn (rm) rn, rm + 4 rm 0110nnnnmmmm0110 ? ? ? mov.b r0,@(disp * ,rn) r0 (disp + rn) 10000000nnnndddd ? ? ? mov.w r0,@(disp * ,rn) r0 (disp 2 + rn) 10000001nnnndddd ? ? ? mov.l rm,@(disp * ,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd ? ? ? mov.b @(disp * ,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd ? ? ? mov.w @(disp * ,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd ? ? ? mov.l @(disp * ,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd ? ? ? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 ? ? ? mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 ? ? ? mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 ? ? ? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 60 of 1286 rej09b0158-0100 instruction operation instruction code privileged t bit new mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 ? ? ? mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 ? ? ? mov.b r0,@(disp * ,gbr) r0 (disp + gbr) 11000000dddddddd ? ? ? mov.w r0,@(disp * ,gbr) r0 (disp 2 + gbr) 11000001dddddddd ? ? ? mov.l r0,@(disp * ,gbr) r0 (disp 4 + gbr) 11000010dddddddd ? ? ? mov.b @(disp * ,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd ? ? ? mov.w @(disp * ,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd ? ? ? mov.l @(disp * ,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd ? ? ? mova @(disp * ,pc),r0 disp 4 + pc & h'ffff fffc + 4 r0 11000111dddddddd ? ? ? movco.l r0,@rn ldst t if (t == 1) r0 (rn) 0 ldst 0000nnnn01110011 ? ldst new movli.l @rm,r0 1 ldst (rm) r0 when interrupt/exception occurred 0 ldst 0000mmmm01100011 ? ? new movua.l @rm,r0 (rm) r0 load non-boundary alignment data 0100mmmm10101001 ? ? new movua.l @rm+,r0 (rm) r0, rm + 4 rm load non-boundary alignment data 0100mmmm11101001 ? ? new movt rn t rn 0000nnnn00101001 ? ? ? swap.b rm,rn rm swap lower 2 bytes rn 0110nnnnmmmm1000 ? ? ? swap.w rm,rn rm swap upper/lower words rn 0110nnnnmmmm1001 ? ? ? xtrct rm,rn rm:rn middle 32 bits rn 0010nnnnmmmm1101 ? ? ? note: * the assembler of renesas uses the value after scaling ( 1, 2, or 4) as the displacement (disp).
section 3 instruction set rev.1.00 dec. 13, 2005 page 61 of 1286 rej09b0158-0100 table 3.5 arithmetic operation instructions instruction operation instruction code privileged t bit new add rm,rn rn + rm rn 0011nnnnmmmm1100 ? ? ? add #imm,rn rn + imm rn 0111nnnniiiiiiii ? ? ? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 ? carry ? addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 ? overflow ? cmp/eq #imm,r0 when r0 = imm, 1 t otherwise, 0 t 10001000iiiiiiii ? comparison result ? cmp/eq rm,rn when rn = rm, 1 t otherwise, 0 t 0011nnnnmmmm0000 ? comparison result ? cmp/hs rm,rn when rn rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0010 ? comparison result ? cmp/ge rm,rn when rn rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0011 ? comparison result ? cmp/hi rm,rn when rn > rm (unsigned), 1 t otherwise, 0 t 0011nnnnmmmm0110 ? comparison result ? cmp/gt rm,rn when rn > rm (signed), 1 t otherwise, 0 t 0011nnnnmmmm0111 ? comparison result ? cmp/pz rn when rn 0, 1 t otherwise, 0 t 0100nnnn00010001 ? comparison result ? cmp/pl rn when rn > 0, 1 t otherwise, 0 t 0100nnnn00010101 ? comparison result ? cmp/str rm,rn when any bytes are equal, 1 t otherwise, 0 t 0010nnnnmmmm1100 ? comparison result ? div1 rm,rn 1-step division (rn rm) 0011nnnnmmmm0100 ? calculation result ? div0s rm,rn msb of rn q, msb of rm m, m^q t 0010nnnnmmmm0111 ? calculation result ? div0u 0 m/q/t 0000000000011001 ? 0 ? dmuls.l rm,rn signed, rn rm mac, 32 32 64 bits 0011nnnnmmmm1101 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 62 of 1286 rej09b0158-0100 instruction operation instruction code privileged t bit new dmulu.l rm,rn unsigned, rn rm mac, 32 32 64 bits 0011nnnnmmmm0101 ? ? ? dt rn rn ? 1 rn; when rn = 0, 1 t when rn 0, 0 t 0100nnnn00010000 ? comparison result ? exts.b rm,rn rm sign-extended from byte rn 0110nnnnmmmm1110 ? ? ? exts.w rm,rn rm sign-extended from word rn 0110nnnnmmmm1111 ? ? ? extu.b rm,rn rm zero-extended from byte rn 0110nnnnmmmm1100 ? ? ? extu.w rm,rn rm zero-extended from word rn 0110nnnnmmmm1101 ? ? ? mac.l @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 4 rn, rm + 4 rm 32 32 + 64 64 bits 0000nnnnmmmm1111 ? ? ? mac.w @rm+,@rn+ signed, (rn) (rm) + mac mac rn + 2 rn, rm + 2 rm 16 16 + 64 64 bits 0100nnnnmmmm1111 ? ? ? mul.l rm,rn rn rm macl 32 32 32 bits 0000nnnnmmmm0111 ? ? ? muls.w rm,rn signed, rn rm macl 16 16 32 bits 0010nnnnmmmm1111 ? ? ? mulu.w rm,rn unsigned, rn rm macl 16 16 32 bits 0010nnnnmmmm1110 ? ? ? neg rm,rn 0 ? rm rn 0110nnnnmmmm1011 ? ? ? negc rm,rn 0 ? rm ? t rn, borrow t 0110nnnnmmmm1010 ? borrow ? sub rm,rn rn ? rm rn 0011nnnnmmmm1000 ? ? ? subc rm,rn rn ? rm ? t rn, borrow t 0011nnnnmmmm1010 ? borrow ? subv rm,rn rn ? rm rn, underflow t 0011nnnnmmmm1011 ? underflow ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 63 of 1286 rej09b0158-0100 table 3.6 logic operation instructions instruction operation instruction code privileged t bit new and rm,rn rn & rm rn 0010nnnnmmmm1001 ? ? ? and #imm,r0 r0 & imm r0 11001001iiiiiiii ? ? ? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii ? ? ? not rm,rn ~rm rn 0110nnnnmmmm0111 ? ? ? or rm,rn rn | rm rn 0010nnnnmmmm1011 ? ? ? or #imm,r0 r0 | imm r0 11001011iiiiiiii ? ? ? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii ? ? ? tas.b @rn when (rn) = 0, 1 t otherwise, 0 t in both cases, 1 msb of (rn) 0100nnnn00011011 ? test result ? tst rm,rn rn & rm; when result = 0, 1 t otherwise, 0 t 0010nnnnmmmm1000 ? test result ? tst #imm,r0 r0 & imm; when result = 0, 1 t otherwise, 0 t 11001000iiiiiiii ? test result ? tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; when result = 0, 1 t otherwise, 0 t 11001100iiiiiiii ? test result ? xor rm,rn rn rm rn 0010nnnnmmmm1010 ? ? ? xor #imm,r0 r0 imm r0 11001010iiiiiiii ? ? ? xor.b #imm,@(r0,gbr) (r0 + gbr) imm (r0 + gbr) 11001110iiiiiiii ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 64 of 1286 rej09b0158-0100 table 3.7 shift instructions instruction operation instruction code privileged t bit new rotl rn t rn msb 0100nnnn00000100 ? msb ? rotr rn lsb rn t 0100nnnn00000101 ? lsb ? rotcl rn t rn t 0100nnnn00100100 ? msb ? rotcr rn t rn t 0100nnnn00100101 ? lsb ? shad rm,rn when rm 0, rn << rm rn when rm < 0, rn >> rm [msb rn] 0100nnnnmmmm1100 ? ? ? shal rn t rn 0 0100nnnn00100000 ? msb ? shar rn msb rn t 0100nnnn00100001 ? lsb ? shld rm,rn when rm 0, rn << rm rn when rm < 0, rn >> rm [0 rn] 0100nnnnmmmm1101 ? ? ? shll rn t rn 0 0100nnnn00000000 ? msb ? shlr rn 0 rn t 0100nnnn00000001 ? lsb ? shll2 rn rn << 2 rn 0100nnnn00001000 ? ? ? shlr2 rn rn >> 2 rn 0100nnnn00001001 ? ? ? shll8 rn rn << 8 rn 0100nnnn00011000 ? ? ? shlr8 rn rn >> 8 rn 0100nnnn00011001 ? ? ? shll16 rn rn << 16 rn 0100nnnn00101000 ? ? ? shlr16 rn rn >> 16 rn 0100nnnn00101001 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 65 of 1286 rej09b0158-0100 table 3.8 branch instructions instruction operation instruction code privileged t bit new bf label when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001011dddddddd ? ? ? bf/s label delayed branch; when t = 0, disp 2 + pc + 4 pc when t = 1, nop 10001111dddddddd ? ? ? bt label when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001001dddddddd ? ? ? bt/s label delayed branch; when t = 1, disp 2 + pc + 4 pc when t = 0, nop 10001101dddddddd ? ? ? bra label delayed branch, disp 2 + pc + 4 pc 1010dddddddddddd ? ? ? braf rn delayed branch, rn + pc + 4 pc 0000nnnn00100011 ? ? ? bsr label delayed branch, pc + 4 pr, disp 2 + pc + 4 pc 1011dddddddddddd ? ? ? bsrf rn delayed branch, pc + 4 pr, rn + pc + 4 pc 0000nnnn00000011 ? ? ? jmp @rn delayed branch, rn pc 0100nnnn00101011 ? ? ? jsr @rn delayed branch, pc + 4 pr, rn pc 0100nnnn00001011 ? ? ? rts delayed branch, pr pc 0000000000001011 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 66 of 1286 rej09b0158-0100 table 3.9 system control instructions instruction operation instruction code privileged t bit new clrmac 0 mach, macl 0000000000101000 ? ? ? clrs 0 s 0000000001001000 ? ? ? clrt 0 t 0000000000001000 ? 0 ? icbi @rn invalidates instruction cache block indicated by virtual address 0000nnnn11100011 ? ? new ldc rm,sr rm sr 0100mmmm00001110 privileged lsb ? ldc rm,gbr rm gbr 0100mmmm00011110 ? ? ? ldc rm,vbr rm vbr 0100mmmm00101110 privileged ? ? ldc rm,sgr rm sgr 0100mmmm00111010 privileged ? new ldc rm,ssr rm ssr 0100mmmm00111110 privileged ? ? ldc rm,spc rm spc 0100mmmm01001110 privileged ? ? ldc rm,dbr rm dbr 0100mmmm11111010 privileged ? ? ldc rm,rn_bank rm rn_bank (n = 0 to 7) 0100mmmm1nnn1110 privileged ? ? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 privileged lsb ? ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 ? ? ? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 privileged ? ? ldc.l @rm+,sgr (rm) sgr, rm + 4 rm 0100mmmm00110110 privileged ? new ldc.l @rm+,ssr (rm) ssr, rm + 4 rm 0100mmmm00110111 privileged ? ? ldc.l @rm+,spc (rm) spc, rm + 4 rm 0100mmmm01000111 privileged ? ? ldc.l @rm+,dbr (rm) dbr, rm + 4 rm 0100mmmm11110110 privileged ? ? ldc.l @rm+,rn_bank (rm) rn_bank, rm + 4 rm 0100mmmm1nnn0111 privileged ? ? lds rm,mach rm mach 0100mmmm00001010 ? ? ? lds rm,macl rm macl 0100mmmm00011010 ? ? ? lds rm,pr rm pr 0100mmmm00101010 ? ? ? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 ? ? ? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 ? ? ? lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 ? ? ? ldtlb pteh/ptel tlb 0000000000111000 privileged ? ? movca.l r0,@rn r0 (rn) (without fetching cache block) 0000nnnn11000011 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 67 of 1286 rej09b0158-0100 instruction operation instruction code privileged t bit new nop no operation 0000000000001001 ? ? ? ocbi @rn invalidates operand cache block 0000nnnn10010011 ? ? ? ocbp @rn writes back and invalidates operand cache block 0000nnnn10100011 ? ? ? ocbwb @rn writes back operand cache block 0000nnnn10110011 ? ? ? pref @rn (rn) operand cache 0000nnnn10000011 ? ? ? prefi @rn reads 32-byte instruction block into instruction cache 0000nnnn11010011 ? ? new rte delayed branch, ssr/spc sr/pc 0000000000101011 privileged ? ? sets 1 s 0000000001011000 ? ? ? sett 1 t 0000000000011000 ? 1 ? sleep sleep 0000000000011011 privileged ? ? stc sr,rn sr rn 0000nnnn00000010 privileged ? ? stc gbr,rn gbr rn 0000nnnn00010010 ? ? ? stc vbr,rn vbr rn 0000nnnn00100010 privileged ? ? stc ssr,rn ssr rn 0000nnnn00110010 privileged ? ? stc spc,rn spc rn 0000nnnn01000010 privileged ? ? stc sgr,rn sgr rn 0000nnnn00111010 privileged ? ? stc dbr,rn dbr rn 0000nnnn11111010 privileged ? ? stc rm_bank,rn rm_bank rn (m = 0 to 7) 0000nnnn1mmm0010 privileged ? ? stc.l sr,@-rn rn ? 4 rn, sr (rn) 0100nnnn00000011 privileged ? ? stc.l gbr,@-rn rn ? 4 rn, gbr (rn) 0100nnnn00010011 ? ? ? stc.l vbr,@-rn rn ? 4 rn, vbr (rn) 0100nnnn00100011 privileged ? ? stc.l ssr,@-rn rn ? 4 rn, ssr (rn) 0100nnnn00110011 privileged ? ? stc.l spc,@-rn rn ? 4 rn, spc (rn) 0100nnnn01000011 privileged ? ? stc.l sgr,@-rn rn ? 4 rn, sgr (rn) 0100nnnn00110010 privileged ? ? stc.l dbr,@-rn rn ? 4 rn, dbr (rn) 0100nnnn11110010 privileged ? ? stc.l rm_bank,@-rn rn ? 4 rn, rm_bank (rn) (m = 0 to 7) 0100nnnn1mmm0011 privileged ? ? sts mach,rn mach rn 0000nnnn00001010 ? ? ? sts macl,rn macl rn 0000nnnn00011010 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 68 of 1286 rej09b0158-0100 instruction operation instruction code privileged t bit new sts pr,rn pr rn 0000nnnn00101010 ? ? ? sts.l mach,@-rn rn ? 4 rn, mach (rn) 0100nnnn00000010 ? ? ? sts.l macl,@-rn rn ? 4 rn, macl (rn) 0100nnnn00010010 ? ? ? sts.l pr,@-rn rn ? 4 rn, pr (rn) 0100nnnn00100010 ? ? ? synco prevents the next instruction from being issued until instructions issued before this instruction have been completed. 0000000010101011 ? ? new trapa #imm pc + 2 spc, sr ssr, #imm << 2 tra, h'160 expevt, vbr + h'0100 pc 11000011iiiiiiii ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 69 of 1286 rej09b0158-0100 table 3.10 floating -point single-precision instructions instruction operation instruction code privileged t bit new fldi0 frn h'0000 0000 frn 1111nnnn10001101 ? ? ? fldi1 frn h'3f80 0000 frn 1111nnnn10011101 ? ? ? fmov frm,frn frm frn 1111nnnnmmmm1100 ? ? ? fmov.s @rm,frn (rm) frn 1111nnnnmmmm1000 ? ? ? fmov.s @(r0,rm),frn (r0 + rm) frn 1111nnnnmmmm0110 ? ? ? fmov.s @rm+,frn (rm) frn, rm + 4 rm 1111nnnnmmmm1001 ? ? ? fmov.s frm,@rn frm (rn) 1111nnnnmmmm1010 ? ? ? fmov.s frm,@-rn rn-4 rn, frm (rn) 1111nnnnmmmm1011 ? ? ? fmov.s frm,@(r0,rn) frm (r0 + rn) 1111nnnnmmmm0111 ? ? ? fmov drm,drn drm drn 1111nnn0mmm01100 ? ? ? fmov @rm,drn (rm) drn 1111nnn0mmmm1000 ? ? ? fmov @(r0,rm),drn (r0 + rm) drn 1111nnn0mmmm0110 ? ? ? fmov @rm+,drn (rm) drn, rm + 8 rm 1111nnn0mmmm1001 ? ? ? fmov drm,@rn drm (rn) 1111nnnnmmm01010 ? ? ? fmov drm,@-rn rn-8 rn, drm (rn) 1111nnnnmmm01011 ? ? ? fmov drm,@(r0,rn) drm (r0 + rn) 1111nnnnmmm00111 ? ? ? flds frm,fpul frm fpul 1111mmmm00011101 ? ? ? fsts fpul,frn fpul frn 1111nnnn00001101 ? ? ? fabs frn frn & h'7fff ffff frn 1111nnnn01011101 ? ? ? fadd frm,frn frn + frm frn 1111nnnnmmmm0000 ? ? ? fcmp/eq frm,frn when frn = frm, 1 t otherwise, 0 t 1111nnnnmmmm0100 ? comparis on result ? fcmp/gt frm,frn when frn > frm, 1 t otherwise, 0 t 1111nnnnmmmm0101 ? comparis on result ? fdiv frm,frn frn/frm frn 1111nnnnmmmm0011 ? ? ? float fpul,frn (float) fpul frn 1111nnnn00101101 ? ? ? fmac fr0,frm,frn fr0 * frm + frn frn 1111nnnnmmmm1110 ? ? ? fmul frm,frn frn * frm frn 1111nnnnmmmm0010 ? ? ? fneg frn frn h'8000 0000 frn 1111nnnn01001101 ? ? ? fsqrt frn frn frn 1111nnnn01101101 ? ? ? fsub frm,frn frn ? frm frn 1111nnnnmmmm0001 ? ? ? ftrc frm,fpul (long) frm fpul 1111mmmm00111101 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 70 of 1286 rej09b0158-0100 table 3.11 floating-point do uble-precision instructions instruction operation instruction code privileged t bit new fabs drn drn & h'7fff ffff ffff ffff drn 1111nnn001011101 ? ? ? fadd drm,drn drn + drm drn 1111nnn0mmm00000 ? ? ? fcmp/eq drm,drn when drn = drm, 1 t otherwise, 0 t 1111nnn0mmm00100 ? comparison result ? fcmp/gt drm,drn when drn > drm, 1 t otherwise, 0 t 1111nnn0mmm00101 ? comparison result ? fdiv drm,drn drn /drm drn 1111nnn0mmm00011 ? ? ? fcnvds drm,fpul double_to_ float(drm) fpul 1111mmm010111101 ? ? ? fcnvsd fpul,drn float_to_ double (fpul) drn 1111nnn010101101 ? ? ? float fpul,drn (float)fpul drn 1111nnn000101101 ? ? ? fmul drm,drn drn * drm drn 1111nnn0mmm00010 ? ? ? fneg drn drn ^ h'8000 0000 0000 0000 drn 1111nnn001001101 ? ? ? fsqrt drn drn drn 1111nnn001101101 ? ? ? fsub drm,drn drn ? drm drn 1111nnn0mmm00001 ? ? ? ftrc drm,fpul (long) drm fpul 1111mmm000111101 ? ? ? table 3.12 floating-point control instructions instruction operation instruction code privileged t bit new lds rm,fpscr rm fpscr 0100mmmm01101010 ? ? ? lds rm,fpul rm fpul 0100mmmm01011010 ? ? ? lds.l @rm+,fpscr (rm) fpscr, rm+4 rm 0100mmmm01100110 ? ? ? lds.l @rm+,fpul (rm) fpul, rm+4 rm 0100mmmm01010110 ? ? ? sts fpscr,rn fpscr rn 0000nnnn01101010 ? ? ? sts fpul,rn fpul rn 0000nnnn01011010 ? ? ? sts.l fpscr,@-rn rn ? 4 rn, fpscr (rn) 0100nnnn01100010 ? ? ? sts.l fpul,@-rn rn ? 4 rn, fpul (rn) 0100nnnn01010010 ? ? ?
section 3 instruction set rev.1.00 dec. 13, 2005 page 71 of 1286 rej09b0158-0100 table 3.13 floating-point grap hics acceleration instructions instruction operation instruction code privileged t bit new fmov drm,xdn drm xdn 1111nnn1mmm01100 ? ? ? fmov xdm,drn xdm drn 1111nnn0mmm11100 ? ? ? fmov xdm,xdn xdm xdn 1111nnn1mmm11100 ? ? ? fmov @rm,xdn (rm) xdn 1111nnn1mmmm1000 ? ? ? fmov @rm+,xdn (rm) xdn, rm + 8 rm 1111nnn1mmmm1001 ? ? ? fmov @(r0,rm),xdn (r0 + rm) xdn 1111nnn1mmmm0110 ? ? ? fmov xdm,@rn xdm (rn) 1111nnnnmmm11010 ? ? ? fmov xdm,@-rn rn ? 8 rn, xdm (rn) 1111nnnnmmm11011 ? ? ? fmov xdm,@(r0,rn) xdm (r0 + rn) 1111nnnnmmm10111 ? ? ? fipr fvm,fvn inner_product (fvm, fvn) fr[n+3] 1111nnmm11101101 ? ? ? ftrv xmtrx,fvn transform_vector (xmtrx, fvn) fvn 1111nn0111111101 ? ? ? frchg ~fpscr.fr fpscr.fr 1111101111111101 ? ? ? fschg ~fpscr.sz fpscr.sz 1111001111111101 ? ? ? fpchg ~fpscr.pr fpscr.pr 1111011111111101 ? ? new fsrra frn 1/sqrt (frn) * frn 1111nnnn01111101 ? ? new fsca fpul,drn sin(fpul) frn cos(fpul) fr[n + 1] 1111nnn011111101 ? ? new note: * sqrt (frn) is the square root of frn.
section 3 instruction set rev.1.00 dec. 13, 2005 page 72 of 1286 rej09b0158-0100
section 4 pipelining rev.1.00 dec. 13, 2005 page 73 of 1286 rej09b0158-0100 section 4 pipelining this lsi is a 2-ilp (instruction-level-paralle lism) superscalar pipelining microprocessor. instruction execution is pipelined, and two instructions can be executed in parallel. 4.1 pipelines figure 4.1 shows the basic pipelines. normally, a pipeline consists of seven stages: instruction sfetch (i1/i2), decode and register read (id), execution (e1/e2/e3), an d write-back (wb). an instruction is executed as a co mbination of basic pipelines. 1. general pipeline - instruction fetch - instruction decode - issue - register read - write-back - operation - forwarding - address calculation i1 i2 id e1 e2 e3 wb 2. general load/store pipeline 3. special pipeline 4. special load/store pipeline 5. floating-point pipeline 6. floating-point extended pipeline - instruction fetch - instruction decode - issue - operation - write-back - operation - operation - register read - forwarding i1 i2 id fs1 fs2 fs4 fs3 fs - operation - instruction fetch -instruction decode -issue -register read -forwarding - operation - operation - operation - operation - operation - operation - write-back i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fs - instruction fetch - instruction decode - issue - register read - write-back - memory data access i1 i2 id e1 e2 e3 wb - forwarding - instruction fetch - instruction decode - issue - register read - write-back - operation i1 i2 id e1 e2 e3 wb - instruction fetch - instruction decode - issue - register read i1 i2 id e1 e2 e3 wb figure 4.1 basic pipelines
section 4 pipelining rev.1.00 dec. 13, 2005 page 74 of 1286 rej09b0158-0100 figure 4.2 shows the instruction execution patterns. representations in figure 4.2 and their descriptions are listed in table 4.1. table 4.1 representations of instruction execution patterns representation description e1 e2 e3 wb cpu ex pipe is occupied s1 s2 s3 wb cpu ls pipe is occupied (with memory access) s1 s2 s3 wb cpu ls pipe is occupied (without memory access) e1/s1 either cpu ex pipe or cpu ls pipe is occupied e1s1 e1s1 , both cpu ex pipe and cpu ls pipe are occupied m2 m3 ms cpu mult operation unit is occupied fe1 fe2 fe3 fe4 fe5 fe6 fs fpu-ex pipe is occupied fs1 fs2 fs3 fs4 fs fpu-ls pipe is occupied id id stage is locked both cpu and fpu pipes are occupied
section 4 pipelining rev.1.00 dec. 13, 2005 page 75 of 1286 rej09b0158-0100 (1-1) bf, bf/s, bt, bt/s, bra, bsr: 1 issue cycle + 0 to 2 branch cycles i1 i2 (i1) (id) id e1/s1 e2/s2 e3/s3 wb (i2) (1-2) jsr, jmp, braf, bsrf: 1 issue cycle + 3 branch cycles i1 i2 id e1/s1 e2/s2 e3/s3 wb (branch destination instruction) (1-3) rts: 1 issue cycle + 0 to 3 branch cycles i1 i2 id e1/s1 e2/s2 e3/s3 wb (1-4) rte: 4 issue cycles + 1 branch cycles (1-5) trapa: 8 issue cycles + 5 cycles + 1 branch cycle it is not constant cycles to the clock halted period. (1-6) sleep: 2 issue cycles (i1) (id) (i2) (branch destination instruction) (branch destination instruction) (i1) (id) (i2) (branch destination instruction) note: note: i1 i2 id s1 s2 s3 wb e2s2 id e3s3 id wb id (i1) (id) (i2) e1s1 i1 i2 id s1 s2 s3 wb e1s1 e3s3 e2s2 e1s1 e1s1 e1s1 e1s1 e2s2 e2s2 e2s2 e2s2 e3s3 e3s3 e3s3 e3s3 wb wb wb wb e2s2 e3s3 wb e2s2 e3s3 wb e1s1 e1s1 (i1) (id) (i2) id id id id id id id wb i1 i2 id s1 s2 s3 wb e1s1 e2s2 e3s3 wb id note: note: the number of branch cycles may be 0 by prefetching instruction. in branch instructions that are categorized as (1-1), the number of branch cycles may be reduced by prefetching. it is 14 cycles to the id stage in the first instruction of exception handler. figure 4.2 instructio n execution patterns (1)
section 4 pipelining rev.1.00 dec. 13, 2005 page 76 of 1286 rej09b0158-0100 (2-1) 1-step operation (ex type): 1 issue cycle i1 i2 id e1 e2 e3 wb i1 i2 id s1 s2 s3 wb i1 i2 id wb i1 i2 id e1/s1 e2/s2 e3/s3 e1/s1 e2/s2 e3/s3 wb (2-2) 1-step operation (ls type): 1 issue cycle (2-3) 1-step operation (mt type): 1 issue cycle (2-4) mov (mt type): 1 issue cycle ext[su].[bw], movt, swap, xtrct, add * , cmp * , div * , dt, neg * , sub * , and, and#, not, or, or#, tst, tst#, xor, xor#, rot * , sha * , shl * , clrs, clrt, sets, sett mov#, nop mova mov note: except for and#, or#, tst#, and xor# instructions using gbr relative addressing mode figure 4.2 instructio n execution patterns (2)
section 4 pipelining rev.1.00 dec. 13, 2005 page 77 of 1286 rej09b0158-0100 (3-1) load/store: 1 issue cycle i1 i2 id s1 s2 s3 wb i1 i2 id s1 s2 s3 wb (3-2) and.b, or.b, xor.b, tst.b: 3 issue cycles i1 i2 id s1 s2 s3 wb (3-3) tas.b: 4 issue cycles (3-4) pref, ocbi, ocbp, ocbwb, movca.l, synco: 1 issue cycle mov.[bwl], mov.[bwl] @(d,gbr) i1 i2 id s1 s2 s3 wb e2s2 e3s3 e1s1 (3-5) ldtlb: 1 issue cycle i1 i2 id wb (3-6) icbi: 8 issue cycles + 5 cycles + 3 branch cycle (3-7) prefi: 5 issue cycles + 5 cycles + 3 branch cycle (3-8) movli.l: 1 issue cycle i1 i2 id s1 s2 s3 wb (3-9) movco.l: 1 issue cycle i1 i2 id s1 s2 s3 wb (3-10) movua.l: 2 issue cycles i1 i2 id s1 s2 s3 wb s1 s2 s3 wb (branch to the next instruction of icbi.) e2s2 e3s3 wb e1s1 id id e2s2 e3s3 wb e1s1 e2s2 e3s3 wb e1s1 id id id i1 i2 id s1 s2 s3 wb e1s1 e1s1 e1s1 e2s2 e2s2 e2s2 e3s3 e3s3 e3s3 wb wb wb (i1) (id) (i2) id id id id id id id 5 cycles (min.) i1 i2 id s1 s2 s3 wb e1s1 e2s2 e3s3 wb id e1s1 e1s1 e1s1 e2s2 e2s2 e2s2 e3s3 e3s3 e3s3 wb wb wb (i1) (id) (i2) id id id (branch to the next instruction of prefi.) 5 cycles (min.) figure 4.2 instructio n execution patterns (3)
section 4 pipelining rev.1.00 dec. 13, 2005 page 78 of 1286 rej09b0158-0100 (4-1) ldc to rp_bank/ssr/spc/vbr: 1 issue cycle i1 i2 id s1 s2 s3 wb (4-2) ldc to dbr/sgr: 4 issue cycles i1 i2 id s1 s2 s3 wb (4-3) ldc to gbr: 1 issue cycle (4-4) ldc to sr: 4 issue cycles + 3 branch cycles id id id i1 i2 id s1 s2 s3 wb i1 i2 id s1 s2 s3 wb (4-5) ldc.l to rp_bank/ssr/spc/vbr: 1 issue cycle i1 i2 id e1s1 e2s2 e3s3 wb id id id (4-6) ldc.l to dbr/sgr: 4 issue cycles (4-7) ldc.l to gbr: 1 issue cycle i1 i2 id s1 s2 s3 wb id id id i1 i2 id e1s1 e2s2 e3s3 wb id id id id id i1 i2 id s1 s2 s3 wb (4-8) ldc.l to sr: 6 issue cycles + 3 branch cycles (i1) (id) (i2) (branch to the next instruction.) (branch to the next instruction.) (i1) (id) (i2) figure 4.2 instructio n execution patterns (4)
section 4 pipelining rev.1.00 dec. 13, 2005 page 79 of 1286 rej09b0158-0100 (4-9) stc from dbr/gbr/rp_bank/ssr/spc/vbr/sgr: 1 issue cycle i1 i2 id s1 s2 s3 wb (4-10) stc from sr: 1 issue cycle (4-11) stc.l from dbr/gbr/rp_bank/ssr/spc/vbr/sgr: 1 issue cycle i1 i2 id wb i1 i2 id s1 s2 s3 e1s1 e2s2 e3s3 wb (4-12) stc.l from sr: 1 issue cycle (4-13) lds to pr: 1 issue cycle i1 i2 id wb i1 i2 id s1 s2 s3 e1s1 e2s2 e3s3 wb i1 i2 id s1 s2 s3 wb (4-14) lds.l to pr: 1 issue cycle i1 i2 id s1 s2 s3 wb (4-15) sts from pr: 1 issue cycle i1 i2 id s1 s2 s3 wb (4-16) sts.l from pr: 1 issue cycle (i1) (i2) (id) (??1) (??2) (??3) (wb) (4-17) bsrf, bsr, jsr delay slot instructions (pr set): 0 issue cycle the value of pr is changed in the e3 stage of delay slot instruction. when the sts and sts.l instructions from pr are used as delay slot instructions, changed pr value is used. notes: figure 4.2 instructio n execution patterns (5)
section 4 pipelining rev.1.00 dec. 13, 2005 page 80 of 1286 rej09b0158-0100 (5-1) lds to mach/l: 1 issue cycle i1 i2 id s1 s2 s3 wb ms (5-2) lds.l to mach/l: 1 issue cycle (5-3) sts from mach/l: 1 issue cycle (5-4) sts.l from mach/l: 1 issue cycle i1 i2 id e1 m2 m3 e1 m2 m3 ms e1 m2 m3 ms m2 m3 ms (5-5) muls.w, mulu.w: 1 issue cycle (5-6) dmuls.l, dmulu.l, mul.l: 1 issue cycle (5-7) clrmac: 1 issue cycle i1 i2 id i1 i2 id s1 s2 s3 wb s1 s2 s3 wb i1 i2 id (5-8) mac.w: 2 issue cycle (5-9) mac.l: 2 issue cycle i1 i2 id s1 s2 s3 wb ms i1 i2 id s1 s2 s3 wb ms i1 i2 id s1 s2 s3 wb ms m2 m3 ms m2 m3 ms m2 m3 i1 i2 id s1 s2 s3 wb s1 s2 s3 wb id id figure 4.2 instructio n execution patterns (6)
section 4 pipelining rev.1.00 dec. 13, 2005 page 81 of 1286 rej09b0158-0100 (6-1) lds to fpul: 1 issue cycle i1 i2 id s1 s2 s3 s1 s2 s3 wb s1 s2 s3 wb fs1 fs2 fs3 fs4 fs1 fs2 fs3 fs4 fs fs1 fs2 fs3 fs4 fs1 fs2 fs3 fs4 fs1 fs2 fs3 fs4 fs fs1 fs2 fs3 fs4 fs fs1 fs2 fs3 fs4 fs1 fs2 fs3 fs4 fs fs1 fs2 fs3 fs4 fs (6-2) sts from fpul: 1 issue cycle (6-3) lds.l to fpul: 1 issue cycle (6-4) sts.l from fpul: 1 issue cycle (6-5) lds to fpscr: 1 issue cycle (6-6) sts from fpscr: 1 issue cycle (6-7) lds.l to fpscr: 1 issue cycle (6-8) sts.l from fpscr: 1 issue cycle (6-9) fpu load/store instruction fmov: 1 issue cycle i1 i2 id i1 i2 id s1 s2 s3 wb s1 s2 s3 s1 s2 s3 wb i1 i2 id s1 s2 s3 i1 i2 id wb s1 s2 s3 wb fs3 s1 s2 s3 wb fs1 fs2 fs3 fs4 fs s1 s2 s3 wb i1 i2 id (6-10) flds: 1 issue cycle i1 i2 id i1 i2 id i1 i2 id (6-11) fsts: 1 issue cycle i1 i2 id i1 i2 id fs1 fs2 fs4 fs s1 s2 s3 figure 4.2 instructio n execution patterns (7)
section 4 pipelining rev.1.00 dec. 13, 2005 page 82 of 1286 rej09b0158-0100 (6-12) single-precision fabs, fneg/double-precision fabs, fneg: 1 issue cycle i1 i2 id s1 s2 s3 fs1 fs2 fs3 fs4 fs (6-13) fldi0, fldi1: 1 issue cycle (6-14) single-precision floating-point computation: 1 issue cycle (6-15) single-precision fdiv/fsqrt: 1 issue cycle (6-16) double-precision floating-point computation: 1 issue cycle (6-17) double-precision floating-point computation: 1 issue cycle (6-18) double-precision fdiv/fsqrt: 1 issue cycle i1 i2 id s1 s2 s3 fs1 fs2 fs3 fs4 i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fs feds (divider occupied cycle) fs fcmp/eq, fcmp/gt, fadd, float, fmac, fmul, fsub, ftrc, frchg, fschg, fpchg fcmp/eq, fcmp/gt, fadd, float, fsub, ftrc, fcnvsd, fcnvds fmul feds (divider occupied cycle) i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fs i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fs fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fe3 fe4 fe5 fe6 fs fe3 fe4 fe5 fe6 fs i1 i2 id fs figure 4.2 instructio n execution patterns (8)
section 4 pipelining rev.1.00 dec. 13, 2005 page 83 of 1286 rej09b0158-0100 (6-19) fipr: 1 issue cycle (6-20) ftrv: 1 issue cycle (6-21) fsrra: 1 issue cycle (6-22) fsca: 1 issue cycle function computing unit occupied cycle function computing unit occupied cycle i1 i2 id fe1 fe2 fe3 fe4 fe5 fe6 fs i1 i2 id fe1 fe2 fe1 fe2 fe3 fe4 fe5 fe6 fs fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs i1 i2 id fe1 fe2 fe3 fepl fe4 fe5 fe6 fs fepl i1 i2 id fe1 fe2 fe1 fe2 fe3 fe4 fe5 fe6 fs fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs figure 4.2 instructio n execution patterns (9)
section 4 pipelining rev.1.00 dec. 13, 2005 page 84 of 1286 rej09b0158-0100 4.2 parallel-executability instructions are categorized into six groups according to the inte rnal function bl ocks used, as shown in table 4.2. table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. for example, add in the ex group and bra in the br group can be executed in parallel. table 4.2 instruction groups instruction group instruction ex add addc addv and #imm,r0 and rm,rn clrmac clrs clrt cmp div0s div0u div1 dmus.l dmulu.l dt exts extu movt mul.l muls.w mulu.w neg negc not or #imm,r0 or rm,rn rotcl rotcr rotl rotr sets sett shad shal shar shld shll shll2 shll8 shll16 shlr shlr2 shlr8 shlr16 sub subc subv swap tst #imm,r0 tst rm,rn xor #imm,r0 xor rm,rn xtrct mt mov #imm,rn mov rm,rn nop br bf bf/s bra braf bsr bsrf bt bt/s jmp jsr rts ls fabs fneg fldi0 fldi1 flds fmov @adr,fr fmov fr,@adr fmov fr,fr fmov.s @adr,fr fmov.s fr,@adr fsts ldc rm,cr1 ldc.l @rm+,cr1 lds rm,sr1 lds rm,sr2 lds.l @adr,sr2 lds.l @rm+,sr1 lds.l @rm+,sr2 mov.[bwl] @adr,r mov.[bwl] r,@adr mova movca.l movua ocbi ocbp ocbwb pref stc cr2,rn stc.l cr2,@-rn sts sr2,rn sts.l sr2,@-rn sts sr1,rn sts.l sr1,@-rn
section 4 pipelining rev.1.00 dec. 13, 2005 page 85 of 1286 rej09b0158-0100 instruction group instruction fe fadd fsub fcmp (s/d) fcnvds fcnvsd fdiv fipr float fmac fmul frchg fschg fsqrt ftrc ftrv fsca fsrra fpchg co and.b #imm,@(r0,gbr) icbi ldc rm,dbr ldc rm, sgr ldc rm,sr ldc.l @rm+,dbr ldc.l @rm+,sgr ldc.l @rm+,sr ldtlb mac.l mac.w movco movli or.b #imm,@(r0,gbr) prefi rte sleep stc sr,rn stc.l sr,@-rn synco tas.b trapa tst.b #imm,@(r0,gbr) xor.b #imm,@(r0,gbr) [legend] r: rm/rn @adr: address sr1: mach/macl/pr sr2: fpul/fpscr cr1: gbr/rp_bank/spc/ssr/vbr cr2: cr1/dbr/sgr fr: frm/frn/drm/drn/xdm/xdn the parallel execution of two instructions can be carried out under following conditions. 1. both addr (preceding instruction) and addr + +
section 4 pipelining rev.1.00 dec. 13, 2005 page 86 of 1286 rej09b0158-0100 table 4.3 combination of precedin g and following instructions preceding instruction (addr) ex mt br ls fe co ex no yes yes yes yes no mt yes yes yes yes yes no following instruction (addr + 2) br yes yes no yes yes no ls yes yes yes no yes no fe yes yes yes yes no no co no no no no no no note: the following table shows the parallel-executabili ty of pairs of instructions in this lsi. it is different from table 4.3. preceding instruction (addr) ex mt br ls flsr flsm fe co ex no yes yes yes yes yes yes no mt yes yes yes yes yes yes yes no following instruction (addr + 2) br yes yes no yes yes yes yes no ls yes yes yes no yes no yes no flsr yes yes yes yes no no * no no flsm yes yes yes no no * no yes no fe yes yes yes yes no yes no no co no no no no no no no no [legend] flsr: fabs, fneg, fldi0, fl di1, flds, fsts, fmov fr,fr flsm: fmov[.s] @adr,fr, fmov[.s] fr ,@adr, lds rm,sr2, lds.l @rm+,sr2, sts sr2,rn, sts.l sr2,@-rn ls: original ls instructions except flsr and flsm note: * the cpu can issue these two instructi ons simultaneously, but they are stalled in the fpu.
section 4 pipelining rev.1.00 dec. 13, 2005 page 87 of 1286 rej09b0158-0100 4.3 issue rates and execution cycles instruction execution cycles ar e summarized in table 4.4. inst ruction group in the table 4.4 corresponds to the category in th e table 4.2. penalty cycles due to a pipeline stall are not considered in the issue rates and ex ecution cycles in this section. 1. issue rate i1 i2 id s1 s2 s3 wb issue rate: 3 e2s2 e3s3 wb issue rates indicates the issue period between one instruction and next instruction. e.g. and.b instruction e1s1 i1 i2 id s1 s2 s3 wb ms s2 s3 wb s1 id id id (i1) (id) (i2) next instruction m3 m2 issue rate: 2 (i1) (id) (i2) e.g. mac.w instruction execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules. cpu instruction e.g. and.b instruction i1 i2 id s1 s2 s3 wb execution cycles: 3 e2s2 e3s3 wb e1s1 id id i1 i2 id s1 s2 s3 wb ms s2 s3 wb s1 id m3 m2 e.g. mac.w instruction execution cycles: 4 2. execution cycles next instruction fpu instruction e.g. fmul instruction execution cycles: 14 e.g. fdiv instruction fe1 fe2 fe3 fe4 fe5 fe6 fe1 fe2 fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs fe1 fe2 fe3 fe4 fe5 fe6 fs i1 i2 id i1 i2 id divider occupation cycle fs fe3 fe4 fe5 fe6 fs execution cycles: 3
section 4 pipelining rev.1.00 dec. 13, 2005 page 88 of 1286 rej09b0158-0100 table 4.4 issue rates and execution cycles functional category no. instruction instruction group issue rate execution cycles execution pattern 1 exts.b rm,rn ex 1 1 2-1 2 exts.w rm,rn ex 1 1 2-1 3 extu.b rm,rn ex 1 1 2-1 4 extu.w rm,rn ex 1 1 2-1 5 mov rm,rn mt 1 1 2-4 6 mov #imm,rn mt 1 1 2-3 7 mova @(disp,pc),r0 ls 1 1 2-2 8 mov.w @(disp,pc),rn ls 1 1 3-1 9 mov.l @(disp,pc),rn ls 1 1 3-1 10 mov.b @rm,rn ls 1 1 3-1 11 mov.w @rm,rn ls 1 1 3-1 12 mov.l @rm,rn ls 1 1 3-1 13 mov.b @rm+,rn ls 1 1 3-1 14 mov.w @rm+,rn ls 1 1 3-1 15 mov.l @rm+,rn ls 1 1 3-1 16 mov.b @(disp,rm),r0 ls 1 1 3-1 17 mov.w @(disp,rm),r0 ls 1 1 3-1 18 mov.l @(disp,rm),rn ls 1 1 3-1 19 mov.b @(r0,rm),rn ls 1 1 3-1 20 mov.w @(r0,rm),rn ls 1 1 3-1 21 mov.l @(r0,rm),rn ls 1 1 3-1 22 mov.b @(disp,gbr),r0 ls 1 1 3-1 23 mov.w @(disp, gbr),r0 ls 1 1 3-1 24 mov.l @(disp, gbr),r0 ls 1 1 3-1 25 mov.b rm,@rn ls 1 1 3-1 26 mov.w rm,@rn ls 1 1 3-1 27 mov.l rm,@rn ls 1 1 3-1 28 mov.b rm,@-rn ls 1 1 3-1 data transfer instructions 29 mov.w rm,@-rn ls 1 1 3-1
section 4 pipelining rev.1.00 dec. 13, 2005 page 89 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 30 mov.l rm,@-rn ls 1 1 3-1 31 mov.b r0,@(disp,rn) ls 1 1 3-1 32 mov.w r0,@(disp,rn) ls 1 1 3-1 33 mov.l rm,@(disp,rn) ls 1 1 3-1 34 mov.b rm,@(r0,rn) ls 1 1 3-1 35 mov.w rm,@(r0,rn) ls 1 1 3-1 36 mov.l rm,@(r0,rn) ls 1 1 3-1 37 mov.b r0,@(disp,gbr) ls 1 1 3-1 38 mov.w r0,@(disp,gbr) ls 1 1 3-1 39 mov.l r0,@(disp,gbr) ls 1 1 3-1 40 movca.l r0,@rn ls 1 1 3-4 41 movco.l r0,@rn co 1 1 3-9 42 movli.l @rm,r0 co 1 1 3-8 43 movua.l @rm,r0 ls 2 2 3-10 44 movua.l @rm+,r0 ls 2 2 3-10 45 movt rn ex 1 1 2-1 46 ocbi @rn ls 1 1 3-4 47 ocbp @rn ls 1 1 3-4 48 ocbwb @rn ls 1 1 3-4 49 pref @rn ls 1 1 3-4 50 swap.b rm,rn ex 1 1 2-1 51 swap.w rm,rn ex 1 1 2-1 data transfer instructions 52 xtrct rm,rn ex 1 1 2-1 53 add rm,rn ex 1 1 2-1 54 add #imm,rn ex 1 1 2-1 55 addc rm,rn ex 1 1 2-1 56 addv rm,rn ex 1 1 2-1 57 cmp/eq #imm,r0 ex 1 1 2-1 58 cmp/eq rm,rn ex 1 1 2-1 59 cmp/ge rm,rn ex 1 1 2-1 fixed-point arithmetic instructions 60 cmp/gt rm,rn ex 1 1 2-1
section 4 pipelining rev.1.00 dec. 13, 2005 page 90 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 61 cmp/hi rm,rn ex 1 1 2-1 62 cmp/hs rm,rn ex 1 1 2-1 63 cmp/pl rn ex 1 1 2-1 64 cmp/pz rn ex 1 1 2-1 65 cmp/str rm,rn ex 1 1 2-1 66 div0s rm,rn ex 1 1 2-1 67 div0u ex 1 1 2-1 68 div1 rm,rn ex 1 1 2-1 69 dmuls.l rm,rn ex 1 2 5-6 70 dmulu.l rm,rn ex 1 2 5-6 71 dt rn ex 1 1 2-1 72 mac.l @rm+,@rn+ co 2 5 5-9 73 mac.w @rm+,@rn+ co 2 4 5-8 74 mul.l rm,rn ex 1 2 5-6 75 muls.w rm,rn ex 1 1 5-5 76 mulu.w rm,rn ex 1 1 5-5 77 neg rm,rn ex 1 1 2-1 78 negc rm,rn ex 1 1 2-1 79 sub rm,rn ex 1 1 2-1 80 subc rm,rn ex 1 1 2-1 fixed-point arithmetic instructions 81 subv rm,rn ex 1 1 2-1 82 and rm,rn ex 1 1 2-1 83 and #imm,r0 ex 1 1 2-1 84 and.b #imm,@(r0,gbr) co 3 3 3-2 85 not rm,rn ex 1 1 2-1 86 or rm,rn ex 1 1 2-1 87 or #imm,r0 ex 1 1 2-1 88 or.b #imm,@(r0,gbr) co 3 3 3-2 89 tas.b @rn co 4 4 3-3 90 tst rm,rn ex 1 1 2-1 logical instructions 91 tst #imm,r0 ex 1 1 2-1
section 4 pipelining rev.1.00 dec. 13, 2005 page 91 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 92 tst.b #imm,@(r0,gbr) co 3 3 3-2 93 xor rm,rn ex 1 1 2-1 94 xor #imm,r0 ex 1 1 2-1 logical instructions 95 xor.b #imm,@(r0,gbr) co 3 3 3-2 96 rotl rn ex 1 1 2-1 97 rotr rn ex 1 1 2-1 98 rotcl rn ex 1 1 2-1 99 rotcr rn ex 1 1 2-1 100 shad rm,rn ex 1 1 2-1 101 shal rn ex 1 1 2-1 102 shar rn ex 1 1 2-1 103 shld rm,rn ex 1 1 2-1 104 shll rn ex 1 1 2-1 105 shll2 rn ex 1 1 2-1 106 shll8 rn ex 1 1 2-1 107 shll16 rn ex 1 1 2-1 108 shlr rn ex 1 1 2-1 109 shlr2 rn ex 1 1 2-1 110 shlr8 rn ex 1 1 2-1 shift instructions 111 shlr16 rn ex 1 1 2-1 112 bf disp br 1+0 to 2 1 1-1 113 bf/s disp br 1+0 to 2 1 1-1 114 bt disp br 1+0 to 2 1 1-1 115 bt/s disp br 1+0 to 2 1 1-1 116 bra disp br 1+0 to 2 1 1-1 117 braf rm br 1+3 1 1-2 118 bsr disp br 1+0 to 2 1 1-1 119 bsrf rm br 1+3 1 1-2 120 jmp @rn br 1+3 1 1-2 121 jsr @rn br 1+3 1 1-2 branch instructions 122 rts br 1+0 to 3 1 1-3
section 4 pipelining rev.1.00 dec. 13, 2005 page 92 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 123 nop mt 1 1 2-3 124 clrmac ex 1 1 5-7 125 clrs ex 1 1 2-1 126 clrt ex 1 1 2-1 127 icbi @rn co 8+5+3 13 3-6 128 sets ex 1 1 2-1 129 sett ex 1 1 2-1 130 prefi co 5+5+3 10 3-7 131 synco @rn co undefined undefined 3-4 132 trapa #imm co 8+5+1 13 1-5 133 rte co 4+1 4 1-4 134 sleep co undefined undefined 1-6 135 ldtlb co 1 1 3-5 136 ldc rm,dbr co 4 4 4-2 137 ldc rm,sgr co 4 4 4-2 138 ldc rm,gbr ls 1 1 4-3 139 ldc rm,rp_bank ls 1 1 4-1 140 ldc rm,sr co 4+3 4 4-4 141 ldc rm,ssr ls 1 1 4-1 142 ldc rm,spc ls 1 1 4-1 143 ldc rm,vbr ls 1 1 4-1 144 ldc.l @rm+,dbr co 4 4 4-6 145 ldc.l @rm+,sgr co 4 4 4-6 146 ldc.l @rm+,gbr ls 1 1 4-7 147 ldc.l @rm+,rp_bank ls 1 1 4-5 148 ldc.l @rm+,sr co 6+3 4 4-8 149 ldc.l @rm+,ssr ls 1 1 4-5 150 ldc.l @rm+,spc ls 1 1 4-5 151 ldc.l @rm+,vbr ls 1 1 4-5 152 lds rm,mach ls 1 1 5-1 system control instructions 153 lds rm,macl ls 1 1 5-1
section 4 pipelining rev.1.00 dec. 13, 2005 page 93 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 154 lds rm,pr ls 1 1 4-13 155 lds.l @rm+,mach ls 1 1 5-2 156 lds.l @rm+,macl ls 1 1 5-2 157 lds.l @rm+,pr ls 1 1 4-14 158 stc dbr,rn ls 1 1 4-9 159 stc sgr,rn ls 1 1 4-9 160 stc gbr,rn ls 1 1 4-9 161 stc rp_bank,rn ls 1 1 4-9 162 stc sr,rn co 1 1 4-10 163 stc ssr,rn ls 1 1 4-9 164 stc spc,rn ls 1 1 4-9 165 stc vbr,rn ls 1 1 4-9 166 stc.l dbr,@-rn ls 1 1 4-11 167 stc.l sgr,@-rn ls 1 1 4-11 168 stc.l gbr,@-rn ls 1 1 4-11 169 stc.l rp_bank,@-rn ls 1 1 4-11 170 stc.l sr,@-rn co 1 1 4-12 171 stc.l ssr,@-rn ls 1 1 4-11 172 stc.l spc,@-rn ls 1 1 4-11 173 stc.l vbr,@-rn ls 1 1 4-11 174 sts mach,rn ls 1 1 5-3 175 sts macl,rn ls 1 1 5-3 176 sts pr,rn ls 1 1 4-15 177 sts.l mach,@-rn ls 1 1 5-4 178 sts.l macl,@-rn ls 1 1 5-4 system control instructions 179 sts.l pr,@-rn ls 1 1 4-16 180 fldi0 frn ls 1 1 6-13 181 fldi1 frn ls 1 1 6-13 182 fmov frm,frn ls 1 1 6-9 183 fmov.s @rm,frn ls 1 1 6-9 single- precision floating-point instructions 184 fmov.s @rm+,frn ls 1 1 6-9
section 4 pipelining rev.1.00 dec. 13, 2005 page 94 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 185 fmov.s @(r0,rm),frn ls 1 1 6-9 186 fmov.s frm,@rn ls 1 1 6-9 187 fmov.s frm,@-rn ls 1 1 6-9 188 fmov.s frm,@(r0,rn) ls 1 1 6-9 189 flds frm,fpul ls 1 1 6-10 190 fsts fpul,frn ls 1 1 6-11 191 fabs frn ls 1 1 6-12 192 fadd frm,frn fe 1 1 6-14 193 fcmp/eq frm,frn fe 1 1 6-14 194 fcmp/gt frm,frn fe 1 1 6-14 195 fdiv frm,frn fe 1 14 6-15 196 float fpul,frn fe 1 1 6-14 197 fmac fr0,frm,frn fe 1 1 6-14 198 fmul frm,frn fe 1 1 6-14 199 fneg frn ls 1 1 6-12 200 fsqrt frn fe 1 30 6-15 201 fsub frm,frn fe 1 1 6-14 202 ftrc frm,fpul fe 1 1 6-14 203 fmov drm,drn ls 1 1 6-9 204 fmov @rm,drn ls 1 1 6-9 205 fmov @rm+,drn ls 1 1 6-9 206 fmov @(r0,rm),drn ls 1 1 6-9 207 fmov drm,@rn ls 1 1 6-9 208 fmov drm,@-rn ls 1 1 6-9 single- precision floating-point instructions 209 fmov drm,@(r0,rn) ls 1 1 6-9 210 fabs drn ls 1 1 6-12 211 fadd drm,drn fe 1 1 6-16 212 fcmp/eq drm,drn fe 1 1 6-16 213 fcmp/gt drm,drn fe 1 1 6-16 214 fcnvds drm,fpul fe 1 1 6-16 double- precision floating-point instructions 215 fcnvsd fpul,drn fe 1 1 6-16
section 4 pipelining rev.1.00 dec. 13, 2005 page 95 of 1286 rej09b0158-0100 functional category no. instruction instruction group issue rate execution cycles execution pattern 216 fdiv drm,drn fe 1 14 6-18 217 float fpul,drn fe 1 1 6-16 218 fmul drm,drn fe 1 3 6-17 219 fneg drn ls 1 1 6-12 220 fsqrt drn fe 1 30 6-18 221 fsub drm,drn fe 1 1 6-16 double- precision floating-point instructions 222 ftrc drm,fpul fe 1 1 6-16 223 lds rm,fpul ls 1 1 6-1 224 lds rm,fpscr ls 1 1 6-5 225 lds.l @rm+,fpul ls 1 1 6-3 226 lds.l @rm+,fpscr ls 1 1 6-7 227 sts fpul,rn ls 1 1 6-2 228 sts fpscr,rn ls 1 1 6-6 229 sts.l fpul,@-rn ls 1 1 6-4 fpu system control instructions 230 sts.l fpscr,@-rn ls 1 1 6-8 231 fmov drm,xdn ls 1 1 6-9 232 fmov xdm,drn ls 1 1 6-9 233 fmov xdm,xdn ls 1 1 6-9 234 fmov @rm,xdn ls 1 1 6-9 235 fmov @rm+,xdn ls 1 1 6-9 236 fmov @(r0,rm),xdn ls 1 1 6-9 237 fmov xdm,@rn ls 1 1 6-9 238 fmov xdm,@-rn ls 1 1 6-9 239 fmov xdm,@(r0,rn) ls 1 1 6-9 240 fipr fvm,fvn fe 1 1 6-19 241 frchg fe 1 1 6-14 242 fschg fe 1 1 6-14 243 fpchg fe 1 1 6-14 244 fsrra frn fe 1 1 6-21 245 fsca fpul,drn fe 1 3 6-22 graphics acceleration instructions 246 ftrv xmtrx,fvn fe 1 4 6-20
section 4 pipelining rev.1.00 dec. 13, 2005 page 96 of 1286 rej09b0158-0100
section 5 exception handling rev.1.00 dec. 13, 2005 page 97 of 1286 rej09b0158-0100 section 5 exception handling 5.1 summary of exception handling exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. for example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. the process of generating an exception handling request in response to abnormal termination, and passing control to a user- written exception handling routine, in order to support such functions, is given the generic name of exception handling. the exception handling in this lsi is of three kinds: resets, general exceptions, and interrupts. 5.2 register descriptions table 5.1 lists the configuration of registers related exception handling. table 5.1 register configuration register name abbreviation r/w p4 address * area 7 address * access size trapa exception register tra r/w h'ff00 0020 h'1f00 0020 32 exception event register expevt r/w h'ff00 0024 h'1f00 0024 32 interrupt event register intevt r/w h'ff00 0028 h'1f00 0028 32 note: * p4 is the address when virtual address space p4 area is used. area 7 is the address when physical address space area 7 is accessed by using the tlb. table 5.2 states of regist er in each operating mode register name abbreviation power-on reset manual reset sleep trapa exception register tra undefined undefined retained exception event register expevt h'0000 0000 h'0000 0020 retained interrupt event register intevt undefined undefined retained
section 5 exception handling rev.1.00 dec. 13, 2005 page 98 of 1286 rej09b0158-0100 5.2.1 trapa exception register (tra) the trapa exception register (tra) consists of 8-bit immediate data (imm) for the trapa instruction. tra is set automatically by hardware when a trapa instruction is executed. tra can also be modified by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 00 initial value: rrrrrrrrrrrrrrrr r/w r/w r/w tracode r/w r/w r/w r r r/w: bit: initial value: r/w: 1514131211109876543210 000000 rrrrrrr/w r/w bit bit name initial value r/w description 31 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 to 2 tracode undefined r/w trapa code 8-bit immediate data of trapa instruction is set 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 5 exception handling rev.1.00 dec. 13, 2005 page 99 of 1286 rej09b0158-0100 5.2.2 exception event register (expevt) the exception event register (expevt) consists of a 12-bit exception code. the exception code set in expevt is that for a reset or general exception event. the exception code is set automatically by hardware when an exception occurs. expevt can also be modified by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 0000000/100000 initial value: rrrrrrrrrrrrrrrr r/w r/w expcode r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 0000 r r r r r/w r/w r/w r/w bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 expcode h'000 or h'020 r/w exception code the exception code for a reset or general exception is set. for details, see table 5.3.
section 5 exception handling rev.1.00 dec. 13, 2005 page 100 of 1286 rej09b0158-0100 5.2.3 interrupt even t register (intevt) the interrupt event register (intevt) consists of a 14-bit exception code. the exception code is set automatically by hardware when an excep tion occurs. intevt can also be modified by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 initial value: rrrrrrrrrrrrrrrr r/w intcode r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 00 r r r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 to 0 intcode undefined r/w exception code the exception code for an interrupt is set. for details, see table 5.3.
section 5 exception handling rev.1.00 dec. 13, 2005 page 101 of 1286 rej09b0158-0100 5.3 exception handling functions 5.3.1 exception handling flow in exception handling, the contents of the program counter (pc), status register (sr), and r15 are saved in the saved program counter (spc), saved status register (ssr), and saved general register15 (sgr), and the cpu starts executi on of the appropriate exception handling routine according to the vector address. an exception handling routine is a program written by the user to handle a specific exception. the ex ception handling routine is terminated and control returned to the original program by executing a return-from- exception instruction (rte). this instruction restores the pc and sr contents and returns control to the normal processing routine at the point at which the exception occurred. the sgr contents are not written back to r15 with an rte instruction. the basic processing flow is as follows. for the meaning of the sr bits, see section 2, programming model. 1. the pc, sr, and r15 contents are sa ved in spc, ssr, and sgr, respectively. 2. the block bit (bl) in sr is set to 1. 3. the mode bit (md) in sr is set to 1. 4. the register bank bit (rb) in sr is set to 1. 5. in a reset, the fpu disable b it (fd) in sr is cleared to 0. 6. the exception code is written to bits 11 to 0 of the exception event register (expevt) or interrupt event register (intevt). 7. the cpu branches to the determined except ion handling vector address, and the exception handling routine begins. 5.3.2 exception handling vector addresses the reset vector address is fixed at h'a00000 00. exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (vbr). in the case of the tlb miss exception, for example, the offset is h'00000400, so if h'9c080000 is set in vbr, the exception handling vector address will be h'9c080400. if a further exception occurs at the exception handling vector address, a duplicate exception will result, an d recovery will be difficult; theref ore, addresses that are not to be converted (in p1 and p2 areas) should be specified for vector addresses.
section 5 exception handling rev.1.00 dec. 13, 2005 page 102 of 1286 rej09b0158-0100 5.4 exception types and priorities table 5.3 shows the types of exceptions, with th eir relative priorities, vector addresses, and exception/interrupt codes. table 5.3 exceptions exception transition direction * 3 exception category execution mode exception priority level * 2 priority order * 2 vector address offset exception code * 4 power-on reset 1 1 h'a000 0000 ? h'000 manual reset 1 2 h'a000 0000 ? h'020 h-udi reset 1 1 h'a000 0000 ? h'000 instruction tlb multiple-hit exception 1 3 h'a000 0000 ? h'140 reset abort type data tlb multiple-hit exception 1 4 h'a000 0000 ? h'140 user break before instruction execution * 1 2 0 (vbr/dbr) h'100/? h'1e0 instruction address error 2 1 (vbr) h'100 h'0e0 instruction tlb miss exception 2 2 (vbr) h'400 h'040 instruction tlb protection violation exception 2 3 (vbr) h'100 h'0a0 general illegal instruction exception 2 4 (vbr) h'100 h'180 slot illegal instruction exception 2 4 (vbr) h'100 h'1a0 general fpu disable exception 2 4 (vbr) h'100 h'800 slot fpu disable exception 2 4 (vbr) h'100 h'820 data address error (read) 2 5 (vbr) h'100 h'0e0 data address error (write) 2 5 (vbr) h'100 h'100 data tlb miss exception (read) 2 6 (vbr) h'400 h'040 data tlb miss exception (write) 2 6 (vbr) h'400 h'060 data tlb protection violation exception (read) 2 7 (vbr) h'100 h'0a0 data tlb protection violation exception (write) 2 7 (vbr) h'100 h'0c0 fpu exception 2 8 (vbr) h'100 h'120 general exception re- execution type initial page write exception 2 9 (vbr) h'100 h'080
section 5 exception handling rev.1.00 dec. 13, 2005 page 103 of 1286 rej09b0158-0100 exception transition direction * 3 exception category execution mode exception priority level * 2 priority order * 2 vector address offset exception code * 4 unconditional trap (trapa) 2 4 (vbr) h'100 h'160 general exception completion type user break after instruction execution * 1 2 10 (vbr/dbr) h'100/? h'1e0 nonmaskable interrupt 3 ? (vbr) h'600 h'1c0 interrupt completion type general interrupt request 4 ? (vbr) h'600 ? notes: 1. when ubde in cbcr = 1, pc = dbr. in other cases, pc = vbr + h'100. 2. priority is first assigned by priority le vel, then by priority order within each level (the lowest number represents the highest priority). 3. control passes to h'a000 0000 in a rese t, and to [vbr + offset] in other cases. 4. stored in expevt for a reset or general exception, and in intevt for an interrupt.
section 5 exception handling rev.1.00 dec. 13, 2005 page 104 of 1286 rej09b0158-0100 5.5 exception flow 5.5.1 exception flow figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. for the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt). register settings in the event of an exception are shown only for ssr, spc, sgr, ex pevt/intevt, sr, and pc. however, other registers may be set automatically by hardware, depending on the exception. for details, see section 5.6, description of exceptions. also, see section 5.6.4, priority order with multiple exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, or in the case of instructions in which two data accesses are performed.
section 5 exception handling rev.1.00 dec. 13, 2005 page 105 of 1286 rej09b0158-0100 execute next instruction is highest- priority exception re-exception type? cancel instruction execution result yes yes yes no no no no yes ssr sr spc pc sgr r15 expevt/intevt exception code sr.{md,rb,bl} 111 sr.imask received interuupt level ( * ) pc (cbcr.ubde=1 && user_break? dbr: (vbr + offset)) interrupt requested? general exception requested? reset requested? expevt exception code sr. {md, rb, bl, fd, imask} 11101111 pc h'a000 0000 note: * when the exception of the highest priority is an interrupt. whether imask is updated or not can be set by software. figure 5.1 instruction execution and exception handling
section 5 exception handling rev.1.00 dec. 13, 2005 page 106 of 1286 rej09b0158-0100 5.5.2 exception source acceptance a priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. five of the general exceptions?general illegal instruction exception, slot illegal instructio n exception, general fpu disable exception, slot fpu disable exception, and unconditional trap exception?are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. these exceptions therefore all have the same priority. general exceptions are detected in the order of instruction execution. however, exception handling is performed in the order of instruction flow (program order). thus, an exceptio n for an earlier instruction is accepted before that for a later instruction. an example of the order of acceptance for general ex ceptions is shown in figure 5.2. i1 i1 id id e3 wb wb tlb miss (data access) pipeline flow: order of detection: instruction n instruction n + 1 general illegal instruction exception (instruction n + 1) and tlb miss (instruction n + 2) are detected simultaneously order of exception handling: tlb miss (instruction n) program order 1 instruction n + 2 general illegal instruction exception i1 id wb i2 id wb tlb miss (instruction access) 2 3 4 i1, i2 : instruction fetch id : instruction decode e1, e2, e3 : instruction execution (e2, e3: memory access) wb : write-back instruction n + 3 tlb miss (instruction n) re-execution of instruction n general illegal instruction exception (instruction n + 1) re-execution of instruction n + 1 tlb miss (instruction n + 2) re-execution of instruction n + 2 execution of instruction n + 3 [legend] e3 e3 e2 e2 e1 e1 i2 i2 e1 e1 e2 e2 e3 i2 i1 figure 5.2 example of general exception acceptance order
section 5 exception handling rev.1.00 dec. 13, 2005 page 107 of 1286 rej09b0158-0100 5.5.3 exception requests and bl bit when the bl bit in sr is 0, excep tions and interrupts are accepted. when the bl bit in sr is 1 and an exception other than a user break is generated, the cpu's internal registers and the registers of the other mo dules are set to their st ates following a manual reset, and the cpu branches to the same address as in a reset (h'a000000 0). for the operation in the event of a user break, see section 29, user break controller (ubc). if an ordinary interrupt occurs, the interrupt request is he ld pending and is accepted after the bl bit has been cleared to 0 by software. if a nonmaskable interrupt (nmi) occurs, it can be held pending or accepted according to the setting made by software. thus, normally, spc and ssr are saved and then th e bl bit in sr is cleared to 0, to enable multiple exception state acceptance. 5.5.4 return from exception handling the rte instruction is used to return from exception handling. when the rte instruction is executed, the spc contents are restored to pc and the ssr contents to sr, and the cpu returns from the exception handling routine by branching to the spc address. if spc and ssr were saved to external memory, set the bl bit in sr to 1 before restoring the spc and ssr contents and issuing the rte instruction.
section 5 exception handling rev.1.00 dec. 13, 2005 page 108 of 1286 rej09b0158-0100 5.6 description of exceptions the various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processo r operation when a transition is made. 5.6.1 resets power-on reset: ? ? ? ? ? ? ?
section 5 exception handling rev.1.00 dec. 13, 2005 page 109 of 1286 rej09b0158-0100 instruction tlb multip le-hit exception: ? ? ? ? ? ?
section 5 exception handling rev.1.00 dec. 13, 2005 page 110 of 1286 rej09b0158-0100 5.6.2 general exceptions data tlb miss exception: ? ? ? data_tlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'0000 0040 : h'0000 0060; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0400; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 111 of 1286 rej09b0158-0100 instruction tlb miss exception: ? ? ? itlb_miss_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'0000 0040; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0400; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 112 of 1286 rej09b0158-0100 initial page write exception: ? ? ? initial_write_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'0000 0080; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 113 of 1286 rej09b0158-0100 data tlb protection violation exception: ? pr privileged mo de user mode 00 only read access possible access not possible 01 read/write access possible access not possible 10 only read access possible only read access possible 11 read/write access possible read/write access possible ? ? data_tlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access ? h'0000 00a0 : h'0000 00c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 114 of 1286 rej09b0158-0100 instruction tlb protection violation exception: ? pr privileged mo de user mode 0 access possible access not possible 1 access possible access possible ? ? itlb_protection_violation_exception() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'0000 00a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 115 of 1286 rej09b0158-0100 data address error: ? ? ? ? ? ? ? data_address_error() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = read_access? h'0000 00e0: h'0000 0100; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 116 of 1286 rej09b0158-0100 instruction address error: ? ? ? ? ? instruction_address_error() { tea = exception_address; pteh.vpn = page_number; spc = pc; ssr = sr; sgr = r15; expevt = h'0000 00e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 117 of 1286 rej09b0158-0100 unconditional trap: ? ? ? trapa_exception() { spc = pc + 2; ssr = sr; sgr = r15; tra = imm << 2; expevt = h'0000 0160; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 118 of 1286 rej09b0158-0100 general illegal instruction exception: ? ? ? ? ? general_illegal_instruction_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'0000 0180; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 119 of 1286 rej09b0158-0100 slot illegal instruction exception: ? ? ? ? ? ? ? slot_illegal_instruction_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'0000 01a0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 120 of 1286 rej09b0158-0100 general fpu disable exception: ? ? ? general_fpu_disable_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'0000 0800; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 121 of 1286 rej09b0158-0100 slot fpu disa ble exception: ? ? ? slot_fpu_disable_exception() { spc = pc - 2; ssr = sr; sgr = r15; expevt = h'0000 0820; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 122 of 1286 rej09b0158-0100 pre-execution user break/post-execution user break: ? ? ? user_break_exception() { spc = (pre_execution break? pc : pc + 2); ssr = sr; sgr = r15; expevt = h'0000 01e0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = (brcr.ubde==1 ? dbr : vbr + h'0000 0100); }
section 5 exception handling rev.1.00 dec. 13, 2005 page 123 of 1286 rej09b0158-0100 fpu exception: ? ? ? fpu_exception() { spc = pc; ssr = sr; sgr = r15; expevt = h'0000 0120; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0100; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 124 of 1286 rej09b0158-0100 5.6.3 interrupts nmi (nonmaskable interrupt): ? ? ? nmi() { spc = pc; ssr = sr; sgr = r15; intevt = h'0000 01c0; sr.md = 1; sr.rb = 1; sr.bl = 1; pc = vbr + h'0000 0600; }
section 5 exception handling rev.1.00 dec. 13, 2005 page 125 of 1286 rej09b0158-0100 general interrupt request: ? ? ? module_interruption() { spc = pc; ssr = sr; sgr = r15; intevt = h'0000 0400 ~ h'0000 3fe0; sr.md = 1; sr.rb = 1; sr.bl = 1; if (cond) sr.imask = level_of accepted_interrupt (); pc = vbr + h'0000 0600; } 5.6.4 priority order wi th multiple exceptions with some instructions , such as instructions that ma ke two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. care is required in these cases, as the exception priority order differs from the normal order.
section 5 exception handling rev.1.00 dec. 13, 2005 page 126 of 1286 rej09b0158-0100 ? ?
section 5 exception handling rev.1.00 dec. 13, 2005 page 127 of 1286 rej09b0158-0100 5.7 usage notes 1. return from exception handling a. check the bl bit in sr with software. if spc and ssr have been saved to memory, set the bl bit in sr to 1 before restoring them. b. issue an rte instruction. when rte is ex ecuted, the spc contents are saved in pc, the ssr contents are saved in sr, and branch is made to the spc address to return from the exception handling routine. 2. if an exception or interrupt occurs when bl bit in sr = 1 a. exception when an exception other than a user break o ccurs, a manual reset is executed. the value in expevt at this time is h'00000020; th e spc and ssr contents are undefined. b. interrupt if an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the bl bit in sr has been cleared to 0 by software. if a nonmaskable interrupt (nmi) occurs, it can be held pending or accepted acco rding to the setting made by software. in sleep mode, however, an interrupt is accepted even if the bl bit in sr is set to 1. 3. spc when an exception occurs a. re-execution type exception the pc value for the instructio n at which the exception occu rred is set in spc, and the instruction is re-executed after returning from the exception handling routine. if an exception occurs in a delay slot instruction, however, the pc value for the delayed branch instruction is saved in spc regardless of whet her or not the preceding delay slot instruction condition is satisfied. b. completion type exception or interrupt the pc value for the instructio n following that at which the exception occurred is set in spc. if an exception occurs in a branch inst ruction with delay slot, however, the pc value for the branch destination is saved in spc. 4. rte instruction delay slot a. the instruction in the delay slot of the rte instruction is executed only after the value saved in ssr has been restored to sr. the acceptance of the exce ption related to the instruction access is determined depending on sr before restoring, while the acceptance of other exceptions is determined depending on the processing mode by sr after restoring or the bl bit. the completion ty pe exception is accepted before branching to the destination of rte instruction. however, if the re-execution type exception is occurred, the operation cannot be guaranteed. b. the user break is not accepted by the instruction in the delay slot of the rte instruction.
section 5 exception handling rev.1.00 dec. 13, 2005 page 128 of 1286 rej09b0158-0100 5. changing the sr register value and accepting exception a. when the md or bl bit in the sr regist er is changed by the ldc instruction, the acceptance of the exception is determined by th e changed sr value, starting from the next instruction.* in the completion type exceptio n, an exception is accepted after the next instruction has been executed. however, an interrupt of completion type exception is accepted before the next instruction is executed. note: * when the ldc instruction for sr is executed, following instructions are fetched again and the instruction fetch exception is evaluated again by the changed sr.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 129 of 1286 rej09b0158-0100 section 6 floating-point unit (fpu) 6.1 features the fpu has the following features. ? conforms to ieee754 standard ? 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) ? two rounding modes: round to nearest and round to zero ? two denormalization modes: flush to zero and treat denormalized number ? six exception sources: fpu error, invalid operation, divide by zero, overflow, underflow, and inexact ? comprehensive instructions: single-precision, double-precision, graphics support, and system control ? following three instructions are added in the sh-4a fsrra, fsca, and fpchg when the fd bit in sr is set to 1, the fpu ca nnot be used, and an attempt to execute an fpu instruction will cause an fpu disable exception (general fpu disable exception or slot fpu disable exception).
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 130 of 1286 rej09b0158-0100 6.2 data formats 6.2.1 floating-point format a floating-point number consists of the following three fields: ? sign bit (s) ? exponent field (e) ? fraction field (f) the sh-4a can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 31 se f 30 23 22 0 figure 6.1 format of single -precision floati ng-point number 63 se f 62 52 51 0 figure 6.2 format of double -precision floating-point number the exponent is expressed in biased form, as follows: e = e + bias the range of unbiased exponent e is e min ? 1 to e max + 1. the two values e min ? 1 and e max + 1 are distinguished as follows. e min ? 1 indicates zero (both positive and negative sign) and a denormalized number, and e max + 1 indicates positive or negative infinity or a non-number (nan). table 6.1 shows floating-point formats and parameters.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 131 of 1286 rej09b0158-0100 table 6.1 floating-point number formats and parameters parameter single-preci sion double-precision total bit width 32 bits 64 bits sign bit 1 bit 1 bit exponent field 8 bits 11 bits fraction field 23 bits 52 bits precision 24 bits 53 bits bias +127 +1023 e max +127 +1023 e min ?126 ?1022 floating-point number value v is determined as follows: if e = e max + 1 and f 0, v is a non-number (nan) irrespective of sign s if e = e max + 1 and f = 0, v = (?1) s (infinity) [positive or negative infinity] if e min e e max , v = (?1) s 2 e (1.f) [normalized number] if e = e min ? 1 and f 0, v = (?1) s 2 emin (0.f) [denormalized number] if e = e min ? 1 and f = 0, v = (?1) s 0 [positive or negative zero] table 6.2 shows the ranges of the various numbers in hexadecimal notation. for the signaling non- number and quiet non-number, see section 6.2.2, non-numbers (nan). for the denormalized number, see section 6.2.3, denormalized numbers.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 132 of 1286 rej09b0158-0100 table 6.2 floating-point ranges type single-precision double-precision signaling non- number h'7fff ffff to h'7fc0 0000 h'7fff ffff ffff ffff to h'7ff8 0000 0000 0000 quiet non-number h'7fbf ffff to h'7f80 0001 h'7ff7 ffff ffff ffff to h'7ff0 0000 0000 0001 positive infinity h'7f80 0000 h'7ff0 0000 0000 0000 positive normalized number h'7f7f ffff to h'0080 0000 h'7fef ffff ffff ffff to h'0010 0000 0000 0000 positive denormalized number h'007f ffff to h'0000 0001 h'000f ffff ffff ffff to h'0000 0000 0000 0001 positive zero h'0000 0000 h'0000 0000 0000 0000 negative zero h'8000 0000 h'8000 0000 0000 0000 negative denormalized number h'8000 0001 to h'807f ffff h' 8000 0000 0000 0001 to h'800f ffff ffff ffff negative normalized number h'8080 0000 to h'ff7f ffff h' 8010 0000 0000 0000 to h'ffef ffff ffff ffff negative infinity h'ff 80 0000 h'fff0 0000 0000 0000 quiet non-number h'ff80 0001 to h'ffbf ffff h'fff0 0000 0000 0001 to h'fff7 ffff ffff ffff signaling non-number h'ffc0 0000 to h 'ffff ffff h'fff8 0000 0000 0000 to h'ffff ffff ffff ffff
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 133 of 1286 rej09b0158-0100 6.2.2 non-numbers (nan) figure 6.3 shows the bit pattern of a non-number (nan). a value is nan in the following case: ? sign bit: don't care ? exponent field: all bits are 1 ? fraction field: at least one bit is 1 the nan is a signaling nan (snan) if the msb of the fraction field is 1, and a quiet nan (qnan) if the msb is 0. 31 30 23 22 0 x n = 1:snan n = 0:qnan 11111111 nxxxxxxxxxxxxxxxxxxxxxx figure 6.3 single-precision nan bit pattern an snan is assumed to be the input data in an operation, except the transfer instructions between registers, fabs, and fneg, that generates a floating-point value. ? when the en.v bit in fpscr is 0, the operation result (output) is a qnan. ? when the en.v bit in fpscr is 1, an invalid operation exception will be generated. in this case, the contents of the operation de stination register are unchanged. following three instructions are used as transfer instructions between registers. ? fmov frm,frn ? flds frm,fpul ? fsts fpul,frn if a qnan is input in an operation that generates a floating-point value, and an snan has not been input in that operation, the output will always be a qnan irrespective of the setting of the en.v bit in fpscr. an exception will not be generated in this case. the qnan values as operation results will be as follows: ? single-precision qnan: h'7fbf ffff ? double-precision qnan: h'7ff7 ffff ffff ffff
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 134 of 1286 rej09b0158-0100 see sh-4a software manual for details of floating-point operations when a non-number (nan) is input. 6.2.3 denormalized numbers for a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. when the dn bit in fpscr of the fpu is 1, a de normalized number (sourc e operand or operation result) is always positive or negative zero in a floating-point operation that generates a value (an operation other than transfer instructions between registers, fneg, or fabs). when the dn bit in fpscr is 0, a denormalized number (source operand or operation result) is processed as it is. see sh-4a software manual for details of floating-point operations when a denormalized number is input.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 135 of 1286 rej09b0158-0100 6.3 register descriptions 6.3.1 floating-point registers figure 6.4 shows the floating-point register configuration. there are thirty-two 32-bit floating- point registers comprised with two banks: fpr0_bank0 to fpr15_bank0, and fpr0_bank1 to fpr15_bank1. these thirty-two regist ers are referenced as fr0 to fr15, dr0/2/4/6/8/10/12/14, fv0/4/8/12, xf0 to xf15, xd0/2/4/6/8/10/12/14, and xmtrx. corresponding registers to fpr0_bank0 to fpr15_bank0, and fpr0_bank1 to fpr15_bank1 are determined according to the fr bit of fpscr. 1. floating-point registers, fpri_bankj (32 registers) fpr0_bank0 to fpr15_bank0 fpr0_bank1 to fpr15_bank1 2. single-precision floating-point registers, fri (16 registers) when fpscr.fr = 0, fr0 to fr15 are a llocated to fpr0_bank0 to fpr15_bank0; when fpscr.fr = 1, fr0 to fr15 are a llocated to fpr0_bank1 to fpr15_bank1. 3. double-precision floating-point registers, dri (8 registers): a dr register comprises two fr registers. dr0 = {fr0, fr1}, dr2 = {fr2, fr3}, dr4 = {fr4, fr5}, dr6 = {fr6, fr7}, dr8 = {fr8, fr9}, dr10 = {fr10, fr11}, dr12 = {fr12, fr13}, dr14 = {fr14, fr15} 4. single-precision floating-point vector registers, fvi (4 registers): an fv register comprises four fr registers. fv0 = {fr0, fr1, fr2, fr3}, fv4 = {fr4, fr5, fr6, fr7}, fv8 = {fr8, fr9, fr10, fr11}, fv 12 = {fr12, fr13, fr14, fr15} 5. single-precision floating-point extended registers, xfi (16 registers) when fpscr.fr = 0, xf0 to xf15 are a llocated to fpr0_bank1 to fpr15_bank1; when fpscr.fr = 1, xf0 to xf15 are a llocated to fpr0_bank0 to fpr15_bank0. 6. double-precision floating-point extended registers, xdi (8 registers): an xd register comprises two xf registers. xd0 = {xf0, xf1}, xd2 = {xf2, xf3}, xd4 = {xf4, xf5}, xd6 = {xf6, xf7}, xd8 = {xf8, xf9}, xd10 = {xf10, xf11}, xd12 = {xf12, xf13}, xd14 = {xf14, xf15}
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 136 of 1286 rej09b0158-0100 7. single-precision floating-point extended register matrix, xmtrx: xmtrx comprises all 16 xf registers. xmtrx = xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 fpr0 bank0 fpr1 bank0 fpr2 bank0 fpr3 bank0 fpr4 bank0 fpr5 bank0 fpr6 bank0 fpr7 bank0 fpr8 bank0 fpr9 bank0 fpr10 bank0 fpr11 bank0 fpr12 bank0 fpr13 bank0 fpr14 bank0 fpr15 bank0 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpr0 bank1 fpr1 bank1 fpr2 bank1 fpr3 bank1 fpr4 bank1 fpr5 bank1 fpr6 bank1 fpr7 bank1 fpr8 bank1 fpr9 bank1 fpr10 bank1 fpr11 bank1 fpr12 bank1 fpr13 bank1 fpr14 bank1 fpr15 bank1 xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 fv0 fv4 fv8 fv12 xd0 xmtrx xd2 xd4 xd6 xd8 xd10 xd12 xd14 fpscr.fr = 0 fpscr.fr = 1 figure 6.4 floating-point registers
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 137 of 1286 rej09b0158-0100 6.3.2 floating-point status/control register (fpscr) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000100 initial value: rrrrrrrrrrr/wr/wr/wr/wr/wr/w r/w: 1514131211109876543210 bit: 0000000000000001 initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w: enable (en) fr sz pr dn flag rm cause cause bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 fr 0 r/w floating-point register bank 0: fpr0_bank0 to fpr15_bank0 are assigned to fr0 to fr15 and fpr0_bank1 to fpr15_bank1 are assigned to xf0 to xf15 1: fpr0_bank0 to fpr15_bank0 are assigned to xf0 to xf15 and fpr0_bank1 to fpr15_bank1 are assigned to fr0 to fr15 20 sz 0 r/w transfer size mode 0: data size of fmov instruction is 32-bits 1: data size of fmov instruction is a 32-bit register pair (64 bits) for relations between endian and the sz and pr bits, see figure 6.5. 19 pr 0 r/w precision mode 0: floating-point instruct ions are executed as single-precision operations 1: floating-point instruct ions are executed as double-precision operations (graphics support instructions are undefined) for relations between endian and the sz and pr bits, see figure 6.5. 18 dn 1 r/w denormalization mode 0: denormalized number is treated as such 1: denormalized number is treated as zero
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 138 of 1286 rej09b0158-0100 bit bit name initial value r/w description 17 to 12 cause all 0 r/w 11 to 7 enable all 0 r/w 6 to 2 flag all 0 r/w fpu exception cause field fpu exception enable field fpu exception flag field each time an fpu operation instruction is executed, the fpu exception cause field is cleared to 0. when an fpu exception occurs, the bits corresponding to fpu exception cause field and flag field are set to 1. the fpu exception flag field remains set to 1 until it is cleared to 0 by software. for bit allocations of each field, see table 6.3. 1 0 rm1 rm0 0 1 r/w r/w rounding mode these bits select the rounding mode. 00: round to nearest 01: round to zero 10: reserved 11: reserved
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 139 of 1286 rej09b0158-0100 dr (2i) fr (2i) fr (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 floating-point register memory area 63 0 floating-point register memory area dr (2i) fr (2i) fr (2i+1) 4n 4m 4n+3 4m+3 63 0 63 32 31 0 dr (2i) fr (2i+1) fr (2i) 8n+4 8n+7 8n+3 8n 63 0 63 32 31 0 (1) sz = 0 (2) sz = 1, pr = 0 63 0 63 0 dr (2i) fr (2i+1) fr (2i) 8n 8n+3 8n+7 8n+4 63 0 63 32 31 0 (3) sz = 1, pr = 1 63 0 * 1, * 2 * 2 notes: * 1. in the case of sz = 0 and pr = 0, dr register can not be used. * 2. the bit-location of dr register is used for double precision format when pr = 1. (in the case of (2), it is used when pr is changed from 0 to 1.) figure 6.5 relation between sz bit and endian
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 140 of 1286 rej09b0158-0100 table 6.3 bit allocation for fpu exception handling field name fpu error (e) invalid operation (v) division by zero (z) overflow (o) underflow (u) inexact (i) cause fpu exception cause field bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 enable fpu exception enable field none bit 11 bit 10 bit 9 bit 8 bit 7 flag fpu exception flag field none bit 6 bit 5 bit 4 bit 3 bit 2 6.3.3 floating-point communication register (fpul) information is transferred between the fpu and cp u via fpul. fpul is a 32-bit system register that is accessed from the cpu side by means of lds and sts instructions. for example, to convert the integer stored in general register r1 to a single-precision floating-point number, the processing flow is as follows: r1 (lds instruction) fpul (single-precision float instruction) fr1
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 141 of 1286 rej09b0158-0100 6.4 rounding in a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. therefore, the result of combination instructions such as fmac, ftrv, and fipr will differ from the result when using a basic instructio n such as fadd, fsub, or fmul. rounding is performed once in fmac, but twice in fadd, fsub, and fmul. which of the two rounding methods is to be used is determined by the rm bits in fpscr. fpscr.rm[1:0] = 00: round to nearest fpscr.rm[1:0] = 01: round to zero round to nearest: the operation result is rounded to the nearest expressible value. if there are two nearest expressible values, the on e with an lsb of 0 is selected. if the unrounded value is 2 emax (2 ? 2 ?p ) or more, the result will be infinity with the same sign as the unrounded value. the values of emax and p, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. round to zero: the digits below the round bit of the unrounded value are discarded. if the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressibl e absolute value w ith the same sign as unrounded value.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 142 of 1286 rej09b0158-0100 6.5 floating-point exceptions 6.5.1 general fpu disabl e exceptions and slot fpu disable exceptions fpu-related exceptions are occurred when an fpu instruction is executed with sr.fd set to 1. when the fpu instruction is in other than delayed slot, the general fpu disable exception is occurred. when the fpu instruction is in the delay slot, the slot fpu disable exception is occurred. 6.5.2 fpu exception sources the exception sources are as follows: ? fpu error (e): when fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): in case of an invalid operation, such as nan input ? division by zero (z): division with a zero divisor ? overflow (o): when the operation result overflows ? underflow (u): when the operation result underflows ? inexact exception (i): when overflow, underflow, or rounding occurs the fpu exception cause field in fp scr contains bits corresponding to all of above sources e, v, z, o, u, and i, and the fpu exception flag and en able fields in fpscr contain bits corresponding to sources v, z, o, u, and i, but not e. thus, fpu errors cannot be disabled. when an fpu exception occurs, the corresponding bit in the fpu exception cause field is set to 1, and 1 is added to the corresponding bit in the fpu exception flag field. when an fpu exception does not occur, the corresponding bit in the fpu exception cause field is cleared to 0, but the corresponding bit in the fpu exceptio n flag field remains unchanged. 6.5.3 fpu exception handling fpu exception handling is initiated in the following cases: ? fpu error (e): fpscr.dn = 0 and a denormalized number is input ? invalid operation (v): fpscr.enab le.v = 1 and (instruction = ftrv or invalid operation) ? division by zero (z): fpscr.enable.z = 1 and division with a zero divisor or the input of fsrra is zero ? overflow (o): fpscr.enable.o = 1 and instruction with possibility of operation result overflow
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 143 of 1286 rej09b0158-0100 ? underflow (u): fpscr.enable.u = 1 and instruction with possibility of operation result underflow ? inexact exception (i): fpscr.enable .i = 1 and instruction with possibility of inexact operation result all exception events that originate in the fpu are assigned as the same exception event. the meaning of an exception is determined by software by reading from fpscr and interpreting the information it contains. also, the destination register is not changed by any fpu exception handling operation. if the fpu exception sources except for above are generated, the bit corresponding to source v, z, o, u, or i is set to 1, and a default value is generated as the operation result. ? invalid operation (v): qnan is generated as the result. ? division by zero (z): infinity with the same sign as the unrounded value is generated. ? overflow (o): when rounding mode = rz, the maximum norma lized number, with th e same sign as the unrounded value, is generated. when rounding mode = rn, infinity with the same sign as the unrounded value is generated. ? underflow (u): when fpscr.dn = 0, a denormalized number with the same sign as th e unrounded value, or zero with the same sign as the unrounded value, is generated. when fpscr.dn = 1, zero with the same sign as the unrounded value, is generated. ? inexact exception (i): an inexact result is generated.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 144 of 1286 rej09b0158-0100 6.6 graphics support functions the sh-4a supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision tran sfer instructions that enable high-speed data transfer. 6.6.1 geometric operation instructions geometric operation instructions perform approximate-value computations. to enable high-speed computation with a minimum of hardware, the sh-4a ignores comparatively small values in the partial computation results of four multiplications. consequently, the error shown below is produced in the result of the computation: maximum error = max (individ ual multiplication result 2 ?min (number of multiplier significant digits?1, number of multiplicand significant digits?1) ) + max (result value 2 ?23 , 2 ?149 ) the number of significant digits is 24 for a norm alized number and 23 fo r a denormalized number (number of leading zeros in the fractional part). in a future version of the sh series, the above error is guarant eed, but the same result between different processor cores is not guaranteed. fipr fvm, fvn (m, n: 0, 4, 8, 12): this instruction is basically used for the following purposes: ? inner product (m n): this operation is generally us ed for surface/rear surface determ ination for polygon surfaces. ? sum of square of elements (m = n): this operation is generally used to find the length of a vector. since an inexact exception is not de tected by an fipr instruction, the inexact exception (i) bit in both the fpu exception cause field and flag field are always set to 1 when an fipr instruction is executed. therefore, if the i bit is set in the fpu exception enable field, fpu exception handling will be executed. ftrv xmtrx, fvn (n: 0, 4, 8, 12): this instruction is basically used for the following purposes: ? matrix (4 4) ? vector (4): this operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimen sional). since affine transfor mation processing for angle + parallel movement basically requires a 4 4 matrix, the sh-4a supports 4-dimensional operations.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 145 of 1286 rej09b0158-0100 ? matrix (4 4) matrix (4 4): this operation requires the execution of four ftrv instructions. since an inexact exception is not detected by an firv in struction, the inexact exception (i) bit in both the fpu exception cause field and flag field are always set to 1 when an ftrv instruction is executed. therefore, if the i bit is set in the fpu exception enable field, fpu exception handling will be executed. it is not possible to check all data types in the registers beforehand when executing an ftrv instruction. if the v bit is set in the fpu exception enable field, fpu exception handling will be executed. frchg: this instruction modifies banked registers. for example, when the ftrv instruction is executed, matrix elements must be set in an arra y in the background bank. however, to create the actual elements of a translation matrix, it is easie r to use registers in the foreground bank. when the lds instruction is used on fpscr, this instruction takes four to five cycles in order to maintain the fpu state. with the frchg instruc tion, the fr bit in fpscr can be changed in one cycle. 6.6.2 pair single-precision data transfer in addition to the powerful new geometric operation instructions, the sh-4a also supports high- speed data transfer instructions. when the sz bit is 1, the sh-4a can perform data transfer by means of pair single-precision data transfer instructions. ? fmov drm/xdm, drn/xdrn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) ? fmov drm/xdm, @rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15) these instructions enable two single-precision (2 32-bit) data items to be transferred; that is, the transfer performance of thes e instructions is doubled. ? fschg this instruction changes the value of the sz bit in fpscr, enabling fast switching between use and non-use of pair single-precision data transfer.
section 6 floating-point unit (fpu) rev.1.00 dec. 13, 2005 page 146 of 1286 rej09b0158-0100
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 147 of 1286 rej09b0158-0100 section 7 memory management unit (mmu) this lsi supports an 8- bit address space id entifier, a 32-bit virtual address space, and a 29-bit physical address space. address translation from vi rtual addresses to physical addresses is enabled by the memory management unit (mmu) in this lsi. the mmu performs high-speed address translation by caching user-created address translation table inform ation in an address translation buffer (translation lookaside buffer: tlb). this lsi has four instruction tlb (itlb) entries and 64 unif ied tlb (utlb) entries. utlb copies are stored in the itlb by hardware. a paging system is used for address translation, with four page sizes (1, 4, and 64 kbytes, and 1 mbyte) supported. it is possible to set the virtual address space access right and implement memory protection independently for privileged mode and user mode. 7.1 overview of mmu the mmu was conceived as a means of making ef ficient use of physical memory. as shown in (0) in figure 7.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory , it becomes necessary to divide the process into smaller parts, and map the parts requiring executio n onto physical memory as occas ion arises ((1) in figure 7.1). having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. the virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2) in figure 7.1). with a virtual memory system, the size of the available virtual memory is much larger than the actua l physical memory, and processes are mapped onto this virtual memory. thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally managed by the os, and physical memory switching is carried out so as to enable the virtual memory required by a process to be mapped smoothly onto physical memory. physical memory switching is performed via secondary storage, etc. the virtual memory system that cam e into being in this way works to best effect in a time sharing system (tss) that allows a number of processes to run simultaneously ((3) in figure 7.1). running a number of processes in a tss did not increase efficiency since each pro cess had to take account of physical memory mapping. effici ency is improved and the load on each process reduced by the use of a virtual memory system ((4) in figure 7.1). in this virtual memory system, virtual memory is allocated to each pro cess. the task of the mmu is to map a number of virtual memory areas onto physical memory in an efficient manner. it is also provided with memory protection functions to prevent a process from inadvertently acce ssing another process' s physical memory.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 148 of 1286 rej09b0158-0100 when address translation from virtual memory to physical memory is performed using the mmu, it may happen that the translation information has not been recorded in the mmu, or the virtual memory of a different process is accessed by mist ake. in such cases, the mmu will generate an exception, change the physical memory mappi ng, and record the new address translation information. although the functions of the mmu could be implemented by software alone, having address translation performed by software each time a pr ocess accessed physical memory would be very inefficient. for this reason, a buffer for address translation (the translat ion lookaside buffer: tlb) is provided by hardware, and frequently used address translation information is placed here. the tlb can be described as a cache for address transl ation information. howeve r, unlike a cache, if address translation fails?that is, if an exception occurs?switching of the address translation information is normally performed by software. thus memory management can be performed in a flexible manner by software. there are two methods by which the mmu can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space called a page. in the following descriptions, the address space in virtual memory in this lsi is referred to as virtual address space, and the ad dress space in physical memory as physical address space.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 149 of 1286 rej09b0158-0100 mmu mmu process 1 physical memory (1) (0) (2) (3) (4) physical memory physical memory physical memory virtual memory virtual memory physical memory process 1 process 1 process 2 process 3 process 1 process 1 process 2 process 3 figure 7.1 role of mmu 7.1.1 address spaces virtual address space: this lsi supports a 32-bit virtua l address space, and can access a 4- gbyte address space. the virtual address space is divided into a number of areas, as shown in figures 7.2 and 7.3. in privileged mode, the 4-g byte space from the p0 area to the p4 area can be accessed. in user mode, a 2-gbyte space in the u0 area can be accessed. when the sqmd bit in the mmu control register (mmucr) is 0, a 64-m byte space in the stor e queue area can be accessed. when the rmd bit in th e on-chip memory control regist er (ramcr) is 1, a 16-mbyte space in on-chip memory area can be accessed. a ccessing areas other than the u0 area, store queue area, and on-chip memory area in user mode will cause an address error. when the at bit in mmucr is set to 1 and the mmu is enabled, the p0, p3, and u0 areas can be mapped onto any physical address space in 1-, 4-, or 64-kbyte, or 1-mbyte page units. by using an 8-bit address space identifier, the p0, p3, and u0 areas can be increased to a maximum of 256.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 150 of 1286 rej09b0158-0100 mapping from the virtual address space to the 29-b it physical address spac e is carried out using the tlb. h'0000 0000 h'8000 0000 h'e000 0000 h'e400 0000 h'e500 0000 h'e600 0000 h'ffff ffff h'0000 0000 h'8000 0000 h'ffff ffff h'a000 0000 h'c000 0000 h'e000 0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 physical address space address error address error address error on-chip memory area store queue area user mode privileged mode p1 area cacheable p0 area cacheable p2 area non-cacheable p3 area cacheable p4 area non-cacheable u0 area cacheable figure 7.2 virtual addres s space (at in mmucr = 0)
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 151 of 1286 rej09b0158-0100 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 physical address space 256 256 u0 area cacheable address translation possible address error address error on-chip memory area address error store queue area p0 area cacheable address translation possible user mode privileged mode p1 area cacheable address translation not possible p2 area non-cacheable address translation not possible p3 area cacheable address translation possible p4 area non-cacheable address translation not possible h'0000 0000 h'8000 0000 h'e000 0000 h'e400 0000 h'e500 0000 h'e600 0000 h'ffff ffff h'ffff ffff h'0000 0000 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 figure 7.3 virtual addres s space (at in mmucr = 1)
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 152 of 1286 rej09b0158-0100 ? ? ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 153 of 1286 rej09b0158-0100 h'e000 0000 h'e400 0000 h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'f500 0000 h'f600 0000 h'f700 0000 h'f800 0000 h'fc00 0000 h'ffff ffff store queue reserved area on-chip memory area instruction cache address array instruction cache data array instruction tlb address array instruction tlb data array operand cache address array operand cache data array unified tlb and pmb address array unified tlb and pmb data array reserved area reserved area control register area h'e500 0000 h'e600 0000 figure 7.4 p4 area the area from h'e000 0000 to h'e3ff ffff comp rises addresses for accessing the store queues (sqs). in user mode, the access right is specified by the sqmd bit in mm ucr. for details, see section 8.7, store queues. the area from h'e500 0000 to h'e5ff ffff comprises addresses for accessing the on-chip memory. in user mode, the access right is specified by the rmd bi t in ramcr. for details, see section 9, l memory. the area from h'f000 0000 to h'f0ff ffff is used for dir ect access to the instruction cache address array. for details, see s ection 8.6.1, ic address array. the area from h'f100 0000 to h' f1ff ffff is used for direct access to the instruction cache data array. for details, see section 8.6.2, ic data array. the area from h'f200 0000 to h'f2ff ffff is used for direct access to the instruction tlb address array. for details, see sec tion 7.6.1, itlb address array. the area from h'f300 0000 to h' f37f ffff is used for direct access to instruction tlb data array. for details, see section 7.6.2, itlb data array.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 154 of 1286 rej09b0158-0100 the area from h'f400 0000 to h' f4ff ffff is used for direct access to the operand cache address array. for details, see section 8.6.3, oc address array. the area from h'f500 0000 to h' f5ff ffff is used for direct access to the operand cache data array. for details, see section 8.6.4, oc data array. the area from h'f600 0000 to h' f60f ffff is used for direct access to the unified tlb address array. for details, see section 7.6.3, utlb address array. the area from h'f700 0000 to h' f70f ffff is used for direct access to unified tlb data array. for details, see section 7.6.4, utlb data array. the area from h'f610 0000 to h' f61f ffff is used for direct access to the pmb address array. for details, see section 7.7.5, memory-mapped pmb configuration. the area from h'f710 0000 to h' f71f ffff is used for direct access to the pmb data array. for details, see section 7.7.5, memory-mapped pmb configuration. the area from h'fc00 0000 to h'ffff ffff is the on-chip peripheral module control register area. for details, see register descriptions in each section. physical address space: this lsi supports a 29-bit physical ad dress space. the physical address space is divided into eight areas as shown in figure 7.5. area 7 is a reserved area. only when area 7 in the physical address spa ce is accessed using the tlb, addresses h'1c00 0000 to h'1fff ffff of area 7 are not designated as a reserved area, but are equivalent to the control register area in the p4 area in the virtual address space. h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'1fff ffff area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 (reserved area) figure 7.5 physical address space
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 155 of 1286 rej09b0158-0100 address translation: when the mmu is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. the address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. fast address translation is achieved by caching the contents of the address tr anslation table located in external memory into the tlb. in this lsi, basically, the itlb is us ed for instruction accesses and the utlb for data accesses. in the event of an access to an area othe r than the p4 area, the a ccessed virtual address is translated to a physical address. if the virtual ad dress belongs to the p1 or p2 area, the physical address is uniquely dete rmined without accessing th e tlb. if the virtual addr ess belongs to the p0, u0, or p3 area, the tlb is searched using the virtual address, and if the virtual address is recorded in the tlb, a tlb hit is made and the corresponding physical address is read from the tlb. if the accessed virtual address is not recorded in th e tlb, a tlb miss exception is generated and processing switches to the tlb miss exception handling routine. in the tlb miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the tlb. after the return from the exception handling routine, the instruction which caused the tlb miss exception is re-executed. single virtual memory mode and multiple virtual memory mode: there are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the sv bit in mmucr. in the singl e virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. in the multiple virtual memory system, a number of pro cesses run while sharing the virtua l address space, and particular virtual addresses may be translated into different physical addresses depending on the process. the only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the tlb address comparison method (see section 7.3.3, address translation method). address space identifier (asid): in multiple virtual memory mode, an 8-bit address space identifier (asid) is used to distinguish between multiple processes running simultaneously while sharing the virtual address space. software can set the 8-bit asid of the currently executing process in pteh in the mmu. the tlb does not have to be purged when processes are switched by means of asid. in single virtual memory mode, asid is used to provide memory protection for multiple processes running simultaneously while using the virtua l address space on an exclusive basis. note: two or more entries with the same virtual page number (vpn) but different asid must not be set in the tlb simultaneously in single virtual memory mode.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 156 of 1286 rej09b0158-0100 7.2 register descriptions the following registers are related to mmu processing. table 7.1 register configuration register name abbreviation r/w p4 address * area 7 address * access size page table entry high register pteh r/w h'ff00 0000 h'1f00 0000 32 page table entry low register ptel r/w h'ff00 0004 h'1f00 0004 32 translation table base register ttb r/w h'ff00 0008 h'1f00 0008 32 tlb exception address register tea r/w h'ff00 000c h'1f00 000c 32 mmu control register mmucr r/w h'ff00 0010 h'1f00 0010 32 physical address space control register pascr r/w h'ff00 0070 h'1f00 0070 32 instruction re-fetch inhibit control register irmcr r/w h'ff00 0078 h'1f00 0078 32 note: * these p4 addresses are for the p4 area in the virtual address space. these area 7 addresses are accessed from area 7 in the physical address space by means of the tlb. table 7.2 register states in each processing state register name abbreviation power-on reset manual reset sleep page table entry high register pteh undefined undefined retained page table entry low register ptel undefined undefined retained translation table base register ttb undefined undefined retained tlb exception address register tea undefined retained retained mmu control register mmucr h'0000 0000 h'0000 0000 retained physical address space control register pascr h'0000 0000 h'0000 0000 retained instruction re-fetch inhibit control r egister irmcr h'0000 0000 h'0000 0000 retained
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 157 of 1286 rej09b0158-0100 7.2.1 page table entry high register (pteh) pteh consists of the virtual page number (vpn ) and address space identi fier (asid). when an mmu exception or address error exception occurs, the vpn of the virtual address at which the exception occurred is set in the vpn bit by hardwa re. vpn varies according to the page size, but the vpn set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the ex ception. vpn setting can also be ca rried out by software. the number of the currently executing process is set in the asid bit by software. asid is not updated by hardware. vpn and asid are recorded in the utlb by means of th e ldtlb instruction. after the asid field in pteh has been updated, execute one of the following three methods before an access (including an inst ruction fetch) to the p0, p3, or u0 area that uses the updated asid value is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be the p0, p3, or u0 area. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the r2 bit in irmcr is 0 (initial value) before updating the asid field, the specific instruction does not need to be executed. however, note that the cpu processing performance will be lowered because the instruction fetch is performed again for the next instruction after the asid field has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 asid vpn vpn bit: initial value: r/w: bit: initial value: r/w: 151413121110987654321 0 00 r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 158 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 10 vpn ? r/w virtual page number 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 asid ? r/w address space identifier 7.2.2 page table entr y low register (ptel) ptel is used to hold the physical page number and page management information to be recorded in the utlb by means of the ld tlb instruction. the contents of this register are not changed unless a software directive is issued. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 000 0 initial value: r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ppn ppn v sz1 pr1 pr0 sz0 c d sh wt r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 r r/w r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 31 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 28 to 10 ppn ? r/w physical page number 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 159 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 v ? r/w 7 sz1 ? r/w 6 pr1 ? r/w 5 pr0 ? r/w 4 sz0 ? r/w 3 c ? r/w 2 d ? r/w 1 sh ? r/w 0 wt ? r/w page management information the meaning of each bit is same as that of corresponding bit in common tlb (utlb). for details, see section 7.3, tlb functions. 7.2.3 translation table base register (ttb) ttb is used to store the base addr ess of the currently used page table, and so on. the contents of ttb are not changed unless a software directive is issued. this register can be used freely by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ttb ttb r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 r/w r/w r/w r/w r/w r/w r/w r/w 7.2.4 tlb exception address register (tea) after an mmu exception or addr ess error exception occurs, the virtual address at which the exception occurred is stored. the contents of this register can be changed by software. 31 30 29 28 27 26 25 24 virtual address at which mmu exception or address error occurred virtual address at which mmu exception or address error occurred 23 22 21 20 19 18 17 16 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 r/w r/w r/w r/w r/w r/w r/w r/w tea tea
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 160 of 1286 rej09b0158-0100 7.2.5 mmu control register (mmucr) the individual bits perform mmu settings as shown below. therefore, mmucr rewriting should be performed by a program in the p1 or p2 area. after mmucr has been updated, execute one of the following three methods before an access (including an instruction fetch) to the p0, p3, u0, or store queue area is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be the p0, p3, or u0 area. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the r2 bit in irmcr is 0 (initial value) before updating mmucr, the specific instruction does not need to be executed. however, note that the cpu processing performance will be lowered because the instruction fetch is perfo rmed again for the next instruction after mmucr has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. mmucr contents can be changed by software. however, the lrui and urc bits may also be updated by hardware. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 initial value: r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r r rrr ti urb lrui urc sqmd sv at r r r/w r r/w r/w: bit: initial value: r/w: 1514131211109876543210 0000000000000 000 r/w r/w r/w r/w r/w r/w r/w r/w
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 161 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 26 lrui all 0 r/w least recently used itlb these bits indicate the itlb entry to be replaced. the lru (least recently used) method is used to decide the itlb entry to be replac ed in the event of an itlb miss. the entry to be purge d from the itlb can be confirmed using the lrui bits. lrui is updated by means of the algorithm shown below. x means that updating is not performed. 000xxx: itlb entry 0 is used 1xx00x: itlb entry 1 is used x1x1x0: itlb entry 2 is used xx1x11: itlb entry 3 is used xxxxxx: other than above when the lrui bit settings are as shown below, the corresponding itlb entry is updated by an itlb miss. ensure that values for which "setting prohibited" is indicated below are not set at the discretion of software. after a power-on or manual reset, the lrui bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. x means "don't care". 111xxx: itlb entry 0 is updated 0xx11x: itlb entry 1 is updated x0x0x1: itlb entry 2 is updated xx0x00: itlb entry 3 is updated other than above: setting prohibited 25, 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 to 18 urb all 0 r/w utlb replace boundary these bits indicate the ut lb entry boundary at which replacement is to be performed. valid only when urb 0.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 162 of 1286 rej09b0158-0100 bit bit name initial value r/w description 17, 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 10 urc all 0 r/w utlb replace counter these bits serve as a random counter for indicating the utlb entry for which replacement is to be performed with an ldtlb instruction. this bit is incremented each time the utlb is accessed. if urb > 0, urc is cleared to 0 when the condition urc = urb is satisfied. also note that if a value is written to urc by software which results in the condition of urc > urb, incrementing is first performed in excess of urb until urc = h'3f. urc is not incremented by an ldtlb instruction. 9 sqmd 0 r/w store queue mode bit specifies the right of access to the store queues. 0: user/privileged access possible 1: privileged access possible (address error exception in case of user access) 8 sv 0 r/w single virtual memory mode/multiple virtual memory mode switching bit when this bit is changed, ensure that 1 is also written to the ti bit. 0: multiple virtual memory mode 1: single virtual memory mode 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ti 0 r/w tlb invalidate bit writing 1 to this bit invalidates (clears to 0) all valid utlb/itlb bits. this bit is always read as 0.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 163 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 at 0 r/w address translation enable bit these bits enable or disable the mmu. 0: mmu disabled 1: mmu enabled mmu exceptions are not generated when the at bit is 0. in the case of software that does not use the mmu, the at bit should be cleared to 0.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 164 of 1286 rej09b0158-0100 7.2.6 physical address space control register (pascr) pascr controls the operation in the physical ad dress space. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 00000000 000000 00000000 initial value: rrrrrrrrrrrrrrrr r/w ub r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 00 000000 00 rrrrrrr r bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ub all 0 r/w buffered write control for each area (64 mbytes) when writing is performed wit hout using the cache or in the cache write-through mode, these bits specify whether the next bus access from the cpu waits for the end of writing for each area. 0: the cpu does not wait for the end of writing bus access and starts the next bus access 1: the cpu waits for the end of writing bus access and starts the next bus access ub[7]: corresponding to the control register area ub[6]: corresponding to area 6 ub[5]: corresponding to area 5 ub[4]: corresponding to area 4 ub[3]: corresponding to area 3 ub[2]: corresponding to area 2 ub[1]: corresponding to area 1 ub[0]: corresponding to area 0
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 165 of 1286 rej09b0158-0100 7.2.7 instruction re-fetch in hibit control register (irmcr) when the specific resource is changed, irmcr cont rols whether the instruction fetch is performed again for the next instruction. th e specific resource means the part of control registers, tlb, and cache. in the initial state, the instruction fetch is performed again for the next instruction after changing the resource. however, the cpu processing performance will be lowered because the instruction fetch is performed again for the next instruction every time the resource is changed. therefore, it is recommended that each bit in irmcr is set to 1 and the specific instru ction should be executed after all necessary resources have been changed prior to executi on of the program which uses changed resources. for details on the specific sequence, see descriptions in each resource. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 00000000 000000 00000000 initial value: rrrrrrrrrrrrrrrr r r2 r1 lt mt mc r r r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 1514131211109876543210 00 000000 00 rrrrrrr r bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 r2 0 r/w re-fetch inhibit 2 after register change when mmucr, pascr, ccr, pteh, or ramcr is changed, this bit controls whether re-fetch is performed for the next instruction. 0: re-fetch is performed 1: re-fetch is not performed 3 r1 0 r/w re-fetch inhibit 1 after register change when a register allocated in addresses h'ff200000 to h'ff2fffff is changed, this bit controls whether re- fetch is performed for the next instruction. 0: re-fetch is performed 1: re-fetch is not performed
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 166 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 lt 0 r/w re-fetch inhibit after ldtlb execution this bit controls whether re-fetch is performed for the next instruction after the ldtlb instruction has been executed. 0: re-fetch is performed 1: re-fetch is not performed 1 mt 0 r/w re-fetch inhibit after writing memory-mapped tlb this bit controls whether re-fetch is performed for the next instruction after writing memory-mapped itlb/utlb while the at bit in mmucr is set to 1. 0: re-fetch is performed 1: re-fetch is not performed 0 mc 0 r/w re-fetch inhibit after writing memory-mapped ic this bit controls whether re-fetch is performed for the next instruction after writ ing memory-mapped ic while the ice bit in ccr is set to 1. 0: re-fetch is performed 1: re-fetch is not performed
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 167 of 1286 rej09b0158-0100 7.3 tlb functions 7.3.1 unified tlb (utlb) configuration the utlb is used for the following two purposes: 1. to translate a virtual address to a physical address in a data access 2. as a table of address translation information to be recorded in the itlb in the event of an itlb miss the utlb is so called because of its use for th e above two purposes. information in the address translation table located in exte rnal memory is cached into th e utlb. the address translation table contains virtual page numbers and address sp ace identifiers, and corresponding physical page numbers and page management information. figure 7.6 shows the utlb configuration. the utlb consists of 64 fully-associative type entries. figure 7.7 shows the relationship between the page size and address format. ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] asid [7:0] vpn [31:10] v entry 63 d wt figure 7.6 utlb configuration [legend] ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 168 of 1286 rej09b0158-0100 ? ? ? ? ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 169 of 1286 rej09b0158-0100 1: cacheable when the control register area is mapped, this bit must be cleared to 0. ? ? 31 1-kbyte page 10 9 0 virtual address 31 4-kbyte page 12 11 0 virtual address 31 64-kbyte page 16 15 0 virtual address 31 1-mbyte page 20 19 0 virtual address vpn offset vpn offset vpn offset vpn offset 28 10 9 0 physical address 28 12 11 0 physical address 28 16 15 0 physical address 28 20 19 0 physical address ppn offset ppn offset ppn offset ppn offset figure 7.7 relationship between page size and address format
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 170 of 1286 rej09b0158-0100 7.3.2 instruction tlb (itlb) configuration the itlb is used to translate a virtual address to a physical ad dress in an instruction access. information in the address translation table located in the utlb is cached into the itlb. figure 7.8 shows the itlb configuration. the itlb consists of four fully-associative type entries. ppn [28:10] ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sz [1:0] sh sh sh sh c c c c pr pr pr pr asid [7:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] vpn [31:10] v v v v entry 0 entry 1 entry 2 entry 3 notes: 1. the d and wt bits are not supported. 2. there is only one pr bit, corresponding to the upper bit of the pr bits in the utlb. figure 7.8 itlb configuration
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 171 of 1286 rej09b0158-0100 7.3.3 address translation method figure 7.9 shows a flowchart of a memory access using the utlb. sr.md? r/w? r/w? yes yes no no no yes yes yes no pr? pr? d? r/w? w w w r r r r w r/w? wt? 1 1 0 0 00 or 01 10 11 01 or 11 00 or 10 yes no internal resource access 1 0 ccr.oce? 1 0 ccr.cb? 0 1 ccr.wt? 1 0 ccr.oce? no data access to virtual address (va) va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match, asids match, and v = 1 only one entry matches 1 (privileged) data tlb multiple hit exception data tlb protection violation exception data tlb miss exception 0 (user) vpns match and v = 1 data tlb protection violation exception initial page write exception cache access in copy-back mode cache access in write-through mode memory access (non-cacheable) c = 1 and ccr.oce = 1 figure 7.9 flowchart of memory access using utlb
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 172 of 1286 rej09b0158-0100 figure 7.10 shows a flowchart of a memory access using the itlb. yes yes no no no yes yes yes no internal resource access 1 0 1 0 ccr.ice? yes no no yes no instruction access to virtual address (va) va is in p4 area va is in p2 area va is in p1 area va is in p0, u0, or p3 area mmucr.at = 1 sh = 0 and (mmucr.sv = 0 or sr.md = 0) vpns match and v = 1 vpns match, asids match, and v = 1 only one entry matches sr.md? instruction tlb multiple hit exception 0 (user) 1 (privileged) pr? c = 1 and ccr.ice = 1 cache access memory access (non-cacheable) instruction tlb protection violation exception instruction tlb miss exception hardware itlb miss handling search utlb match? record in itlb figure 7.10 flowchart of memory access using itlb
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 173 of 1286 rej09b0158-0100 7.4 mmu functions 7.4.1 mmu hardware management this lsi supports the following mmu functions. 1. the mmu decodes the virtual address to be accessed by software, and performs address translation by controlling the utlb/itlb in accordance with the mmucr settings. 2. the mmu determines the cache access status on the basis of the page management information read during address translation (c and wt bits). 3. if address translation cannot be performed normally in a data access or instruction access, the mmu notifies software by m eans of an mmu exception. 4. if address translation information is not recorded in the itlb in an instruction access, the mmu searches the utlb. if the necessary address translation in formation is recorded in the utlb, the mmu copies this in formation into the itlb in accordance with the lrui bit setting in mmucr. 7.4.2 mmu software management software processing for the mm u consists of the following: 1. setting of mmu-related registers. some registers are also partially updated by hardware automatically. 2. recording, deletion, and reading of tlb entries. there are two methods of recording utlb entries: by using the ldtlb instruction, or by writing directly to the memory-mapped utlb. itlb entries can only be recorded by writing directly to the memory-mapped itlb. deleting or reading utlb/itlb entries is enabled by accessing the memory -mapped utlb/itlb. 3. mmu exception handling. when an mmu exception occurs, processing is performed based on information set by hardware.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 174 of 1286 rej09b0158-0100 7.4.3 mmu instruction (ldtlb) a tlb load instruction (ldtlb) is provided for recording utlb entries. when an ldtlb instruction is issued, this lsi copies the contents of pteh and ptel to the utlb entry indicated by the urc bit in mmucr. itlb entries are not updated by the ldtlb instruction, and therefore address translation information purged from the utlb entry may still remain in the itlb entry. as the ldtlb instruction changes address translation information, ensure that it is issued by a program in the p1 or p2 area. after the ldtlb instruction has been executed, execute one of the following three methods before an access (include an instruction fetch) th e area where tlb is used to translate the address is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be the area where tlb is used to translate the address. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the lt bit in irmcr is 0 (initial value) before executing the ldtlb instruction, the specific instruction does not need to be execut ed. however, note that the cpu processing performance will be lowered because the instru ction fetch is performe d again for the next instruction after mmucr has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. the operation of the ldtlb instruction is shown in figure 7.11.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 175 of 1286 rej09b0158-0100 ppn [28:10] ppn [28:10] ppn [28:10] sz [1:0] sz [1:0] sz [1:0] sh sh sh c c c pr [1:0] pr [1:0] pr [1:0] asid [7:0] asid [7:0] asid [7:0] vpn [31:10] vpn [31:10] vpn [31:10] v v v entry 0 entry 1 entry 2 d d d wt wt wt ppn [28:10] sz [1:0] sh c pr [1:0] asid [7:0] vpn [31:10] v entry 63 d wt 31 29 28 9 8 76 5 4 3 2 1 0 ?? v sz1 pr[1:0] sz0 cdsh wt ptel write utlb 31 10 9 87 0 ? asid pteh mmucr vpn 10 ppn entry specification 31 2625 2423 1817 1615 10 9 87 3 2 1 0 lrui ? urb ? urc sv ? ti ? at sqmd figure 7.11 operation of ldtlb instruction 7.4.4 hardware itlb miss handling in an instruction access, this lsi searches the itlb. if it cannot find the necessary address translation information (itlb miss occurred), the utlb is searched by hardware, and if the necessary address translation inform ation is present, it is recorded in the itlb. this procedure is known as hardware itlb miss handling. if the necessary address translation information is not found in the utlb search, an in struction tlb miss exception is generated and processing passes to software.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 176 of 1286 rej09b0158-0100 7.4.5 avoiding synonym problems when 1- or 4-kbyte pages are recorded in tl b entries, a synonym problem may arise. the problem is that, when a number of virtual addres ses are mapped onto a single physical address, the same physical address data is r ecorded in a number of cache entr ies, and it becomes impossible to guarantee data integrity. this problem does not occur with the instruction tlb and instruction cache because data is only read in these cases. in this lsi, entry specificat ion is performed using bits 12 to 5 of the virtual address in order to achieve fast operand cache operation. however, bits 12 to 10 of the virtual address in the case of a 1-kbyte page, and bit 12 of the virtual address in the case of a 4-kbyte page, are subject to address transla tion. as a result, bits 12 to 10 of the physical address after translation may differ from bits 12 to 10 of the virtual address. consequently, the following restrictions apply to the recording of address translation information in utlb entries. ? ? ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 177 of 1286 rej09b0158-0100 7.5 mmu exceptions there are seven mmu exceptions: instruction tlb multiple hit exception, instruction tlb miss exception, instruction tlb protection violation exception, data tlb multiple hit exception, data tlb miss exception, data tlb protection violation exception, and initial page write exception. refer to figures 7.9 and 7.10 for the conditions under which each of these exceptions occurs. 7.5.1 instruction tlb mu ltiple hit exception an instruction tlb multiple hit exception occurs when more than one itlb entry matches the virtual address to which an inst ruction access has been made. if multiple hits occur when the utlb is searched by hardware in hardware itlb miss handling, an instruction tlb multiple hit exception will result. when an instruction tlb multiple hit exception oc curs, a reset is executed and cache coherency is not guaranteed. hardware processing: in the event of an instruction tlb mu ltiple hit exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000). software processing (reset routine): the itlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 178 of 1286 rej09b0158-0100 7.5.2 instruction tlb miss exception an instruction tlb miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in th e utlb entries by the hardware itlb miss handling routine. the instruction tlb miss exception pro cessing carried out by hardware and software is shown below. this is the same as the processing for a data tlb miss exception. hardware processing: in the event of an instruction tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the instruction tlb miss exception handling routine. software processi ng (instruction tlb miss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following processing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address translation table. 2. when the entry to be replaced in entry replacement is specified by software, write that value to the urc bits in mmucr. if urc is greater th an urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 3. execute the ldtlb instruction and write th e contents of pteh and ptel to the tlb. 4. finally, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 179 of 1286 rej09b0158-0100 7.5.3 instruction tlb protection violation exception an instruction tlb protection violation exception occurs when, even though an itlb entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitte d by the access right speci fied by the pr bit. the instruction tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of an instruction tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the instruction tlb protection violation exception handling routine. software processing (instruc tion tlb protection violation exception handling routine): resolve the instruction tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, an d return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 180 of 1286 rej09b0158-0100 7.5.4 data tlb multiple hit exception a data tlb multiple hit exception occurs when more than one utlb entry matches the virtual address to which a data access has been made. when a data tlb multiple hit exception occurs, a reset is executed, and cache coherency is not guaranteed. the contents of ppn in the utlb prior to the exception may also be corrupted. hardware processing: in the event of a data tlb multiple hit exception, hardware carries out the following processing: 1. sets the virtual address at which the exception occurred in tea. 2. sets exception code h'140 in expevt. 3. branches to the reset handling routine (h'a000 0000). software processing (reset routine): the utlb entries which caused the multiple hit exception are checked in the reset handling routine. this exception is intended for use in program debugging, and should not normally be generated. 7.5.5 data tlb miss exception a data tlb miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the utlb entries. the data tlb miss exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb miss exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'040 in the case of a re ad, or h'060 in the case of a write in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 181 of 1286 rej09b0158-0100 9. branches to the address obtained by adding of fset h'0000 0400 to the contents of vbr, and starts the data tlb miss exception handling routine. software processing (data tlb mi ss exception handling routine): software is responsible for searching the external memory page table and assigning the necessary page table entry. software should carry out the following processing in order to find and assign the necessary page table entry. 1. write to ptel the values of the ppn, pr, sz, c, d, sh, v, and wt bits in the page table entry recorded in the external memory address translation table. 2. when the entry to be replaced in entry replacement is specified by software, write that value to the urc bits in mmucr. if urc is greater th an urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 3. execute the ldtlb instruction and write th e contents of pteh and ptel to the utlb. 4. finally, execute the exception handling retu rn instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 7.5.6 data tlb protection violation exception a data tlb protection violation exception occurs when, even though a utlb entry contains address translation information ma tching the virtual address to which a data access is made, the actual access type is not permitted by the access ri ght specified by the pr bit. the data tlb protection violation exception processing carried out by hardware and software is shown below. hardware processing: in the event of a data tlb protection violation exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'0a0 in the case of a re ad, or h'0c0 in the case of a write in expevt (ocbp, ocbwb: read; ocbi, movca.l: write). 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, sets the pc value indicating the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 182 of 1286 rej09b0158-0100 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the data tlb protection violation exception handling routine. software processing (data tlb protection violation exception handling routine): resolve the data tlb protection violation, execute the exception handling return instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 7.5.7 initial page write exception an initial page write exception occurs when the d bit is 0 even though a utlb entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. the initial page write exception proce ssing carried out by hardware and software is shown below. hardware processing: in the event of an initial page write exception, hardware carries out the following processing: 1. sets the vpn of the virtual address at which the exception occurred in pteh. 2. sets the virtual address at which the exception occurred in tea. 3. sets exception code h'080 in expevt. 4. sets the pc value indicating the address of th e instruction at which th e exception occurred in spc. if the exception occurred at a delay slot, se ts the pc value indicat ing the address of the delayed branch instruction in spc. 5. sets the sr contents at the time of the exce ption in ssr. the r15 cont ents at this time are saved in sgr. 6. sets the md bit in sr to 1, and switches to privileged mode. 7. sets the bl bit in sr to 1, and masks subsequent exception requests. 8. sets the rb bit in sr to 1. 9. branches to the address obtained by adding of fset h'0000 0100 to the contents of vbr, and starts the initial page write exception handling routine. software processing (ini tial page write exception handling routine): software is responsible for the following processing: 1. retrieve the necessary page table entry from external memory. 2. write 1 to the d bit in the external memory page table entry. 3. write to ptel the values of the ppn, pr, sz, c, d, wt, sh, and v bits in the page table entry recorded in external memory.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 183 of 1286 rej09b0158-0100 4. when the entry to be replaced in entry replacement is specified by software, write that value to the urc bits in mmucr. if urc is greater th an urb at this time, the value should be changed to an appropriate value af ter issuing an ldtlb instruction. 5. execute the ldtlb instruction and write th e contents of pteh and ptel to the utlb. 6. finally, execute the exception handling retu rn instruction (rte), terminate the exception handling routine, and return control to the normal flow. the rte instruction should be issued at least one instruction after the ldtlb instruction. 7.6 memory-mapped tlb configuration to enable the itlb and utlb to be managed by software, their contents are allowed to be read from and written to by a program in the p2 area with a mov instruction in privileged mode. operation is not guaranteed if access is made from a program in another area. after the memory-mapped tlb has been accessed, execute one of the following three methods before an access (including an inst ruction fetch) to an area other than the p2 area is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be an area other than the p2 area. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the mt bit in irmcr is 0 (initial valu e) before accessing the memory-mapped tlb, the specific instruction does not need to be execut ed. however, note that the cpu processing performance will be lowered because the instru ction fetch is performed again for the next instruction after mmucr has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. the itlb and utlb are allocated to the p4 area in the virtual address space. vpn, v, and asid in the itlb can be accessed as an address array, pp n, v, sz, pr, c, and sh as a data array. vpn, d, v, and asid in the utlb can be accessed as an address array, ppn, v, sz, pr, c, d, wt, and sh as a data array. v and d can be accessed from both the address array side and the data array side. only longword access is possible. instruction fetches cannot be performed in these areas. for reserved bits, a write value of 0 should be specified; their read value is undefined.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 184 of 1286 rej09b0158-0100 7.6.1 itlb address array the itlb address array is allocated to addresses h'f200 0000 to h'f2ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). information for selecting the entry to be accessed is specified in the address field, and vpn, v, and asid to be wr itten to the address array are specified in the data field. in the address field, bits [31:24] have the value h'f2 indicating the itlb address array and the entry is specified by bits [9:8 ]. as only longword access is used, 0 should be specified for address field bits [1:0]. in the data field, bits [31:10] indicate vpn, bit [8] indicates v, and bits [7:0] indicate asid. the following two kinds of operation can be used on the itlb address array: 1. itlb address array read vpn, v, and asid are read into the data field from the itlb entry corr esponding to the entry set in the address field. 2. itlb address array write vpn, v, and asid specified in the data field are written to th e itlb entry corresponding to the entry set in the address field. address field 31 23 0 11110 000 10 e data field 31 10 9 0 v vpn vpn: v: e: * : 24 virtual page number validity bit entry don't care 10 9 8 7 2 1 98 7 asid asid: : address space identifier reserved bits (write value should be 0, and read value is undefined ) * * * * * * * * * * * * * * * * * * * figure 7.12 memory-mapped itlb address array
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 185 of 1286 rej09b0158-0100 7.6.2 itlb data array the itlb data array is allocated to addresses h'f3 00 0000 to h'f37f ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification (when writing). informa tion for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, and sh to be written to the data array are specified in the data field. in the address field, bits [31:23] have the value h'f30 indicating itlb data array and the entry is specified by bits [9:8]. in the data field, bits [28:10] indicate ppn, bit [8] indicates v, bits [7] and [4] indicate sz, bit [6] indicates pr, bit [3] indicates c, and bit [1] indicates sh. the following two kinds of operation can be used on itlb data array: 1. itlb data array read ppn, v, sz, pr, c, and sh are read into the data field from the itlb entry corresponding to the entry set in the address field. 2. itlb data array write ppn, v, sz, pr, c, and sh specified in the data field are written to the itlb entry corresponding to the entry set in the address field. address field 31 23 0 11110 000 0 11 e data field ppn: v: e: sz[1:0]: * : 24 physical page number validity bit entry page size bits don't care 10 9 8 7 2 1 pr: c: sh: : protection key data cacheability bit share status bit reserved bits (write value should be 0, and read value is undefined ) 31 210 v 10 9 8 7 30 29 28 4 3 65 sz1 sz0 sh pr c ppn * * * * * * * * * * * * * * * * * * figure 7.13 memory-mapped itlb data array
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 186 of 1286 rej09b0158-0100 7.6.3 utlb address array the utlb address array is allocated to addresses h'f600 0000 to h'f60f ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). information for selecting the entry to be accessed is specified in the address field, an d vpn, d, v, and asid to be written to the address array are specified in the data field. in the address field, bits [31:20] have the value h'f60 indicating the utlb address array and the entry is specified by bits [13:8]. bit [7] that is the association bit (a bit) in the address field specifies whether address comparison is perfor med in a write to the utlb address array. in the data field, bits [31:10] indicate vpn, bit [9] indicates d, bit [8] indicates v, and bits [7:0] indicate asid. the following three kinds of operation can be used on the utlb address array: 1. utlb address array read vpn, d, v, and asid are read into the data field from the utlb entry corresponding to the entry set in the address field. in a read, associ ative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. utlb address array write (non-associative) vpn, d, v, and asid specified in the data field are written to the utlb entry corresponding to the entry set in the address field. the a bi t in the address field should be cleared to 0. 3. utlb address array write (associative) when a write is performed with the a bit in the address field set to 1, comparison of all the utlb entries is carried out usi ng the vpn specified in the data field and asid in pteh. the usual address comparison rules are followed, but if a utlb miss occurs, the result is no operation, and an exception is not generated. if the comparison identifies a utlb entry corresponding to the vpn specified in the data field, d and v specified in the data field are written to that entry. this associative operation is simultaneously carried out on the itlb, and if a matching entry is found in the itlb, v is written to that entry. even if the utlb comparison results in no operation, a write to the itlb is performed as long as a matching entry is found in the itlb. if there is a match in both the utlb and itlb, the utlb information is also written to the itlb.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 187 of 1286 rej09b0158-0100 address field data field vpn: v: e: d: *: virtual page number validity bit entry dirty bit don't care asid: a: : address space identifier association bit reserved bits (write value should be 0 and read value is undefined ) 31 0 v d 10 98 7 asid vpn a 87 2 1 31 0 1111011 0000 000 e 19 20 14 13 ***** ***** * figure 7.14 memory-mapped utlb address array 7.6.4 utlb data array the utlb data array is allocated to addresses h'f700 0000 to h'f70f ffff in the p4 area. a data array access requires a 32-bit address field sp ecification (when reading or writing) and a 32- bit data field specification (whe n writing). inform ation for selecting the entry to be accessed is specified in the address field, an d ppn, v, sz, pr, c, d, sh, and wt to be written to data array are specified in the data field. in the address field, bits [31:20] have the value h'f70 indicating utlb data array and the entry is specified by bits [13:8]. in the data field, bits [28:10] indicate ppn, bit [8] indicates v, bits [7] and [4] indicate sz, bits [6:5] indicate pr, bit [3] indicates c, bit [2] indicates d, bit [1] indicates sh, and bit [0] indicates wt. the following two kinds of operation can be used on utlb data array: 1. utlb data array read ppn, v, sz, pr, c, d, sh, and wt are read into the data field from the utlb entry corresponding to the entry set in the address field. 2. utlb data array write ppn, v, sz, pr, c, d, sh, and wt specified in the data field are written to the utlb entry corresponding to the entry set in the address field.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 188 of 1286 rej09b0158-0100 address field data field ppn: v: e: sz: d: * : physical page number validity bit entry page size bits dirty bit don't care pr: c: sh: wt: : protection key data cacheability bit share status bit write-through bit reserved bits (write value should be 0 and read value is undefined ) 31 210 v 10987 29 28 4 3 65 pr c ppn d sz1 sh wt 31 0 1 2 1111011 10 000 e 19 20 8 7 14 13 00 ****** * * **** figure 7.15 memory-mapped utlb data array 7.7 32-bit address extended mode setting the se bit in pascr to 1 changes mode from 29-bit address mode which handles the 29- bit physical address space to 32 -bit address extended mode whic h handles the 32-bit physical address space. p1(0.5gb) p1/p2 (1gb) 0.5gb 4gb u0/p0 (2gb) u0/p0 (2gb) p2(0.5gb) p3(0.5gb) p3(0.5gb) p4(0.5gb) p4(0.5gb) virtual address space 29-bits address space virtual address space 32-bit address space 29-bit physical address space (normal mode) 32-bit physical address space (extended mode) figure 7.16 physical address space (32-bit address extended mode)
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 189 of 1286 rej09b0158-0100 7.7.1 overview of 32-bit address extended mode in 32-bit address extended mode , the privileged space mapping bu ffer (pmb) is introduced. the pmb maps virtual addresses in the p1 or p2 area which are not translated in 29-bit address mode to the 32-bit physical addr ess space. in areas which are target for address translation of the tlb (utlb/itlb), upper three bits in the ppn field of the utlb or itlb are extended and then addresses after the tlb translation can handle the 32-bit physical addresses. as for the cache operation, p1 area is cacheable an d p2 area is non-cacheable in the case of 29-bit address mode, but the cache operation of both p1 and p2 area are determined by the c bit and wt bit in the pmb in the case of 32-bit address mode. 7.7.2 transition to 32-bit address extended mode this lsi enters 29-bit address mode after a power-on reset. transition is made to 32-bit address extended mode by setting the se bit in pascr to 1. in 32-bit address extended mode, the mmu operates as follows. 1. when the at bit in mmucr is 0, virtual addresses in the u0, p0, or p3 area become 32-bit physical addresses. addresses in the p1 or p2 area are translated according to the pmb mapping information. b'10 should be set to the upper 2 bits of virtual page number (vpn[31:30]) in the pmb in order to indicate p1 or p2 area. the operation is not guaranteed when the value except b'10 is set to these bits. 2. when the at bit in mmucr is 1, virtual addre sses in the u0, p0, or p3 area are translated to 32-bit physical addresses according to the tlb conversion information. addresses in the p1 or p2 area are translated according to the pmb mapping information. b'10 should be set to the upper 2 bits of virtual page number (vpn[31:30]) in the pmb in order to indicate p1 or p2 area. the operation is not guaranteed when the value except b'10 is set to these bits. 3. regardless of the setting of the at bit in mmucr, bits 31 to 29 in physical addresses become b'111 in the control register area (addresses h'fc00 0000 to h'ffff ffff). when the control register area is recorded in the utlb and accessed, b'111 should be set to ppn[31:29]. 7.7.3 privileged space mapping buffer (pmb) configuration in 32-bit address extended mode, virtual addresses in the p1 or p2 area are translated according to the pmb mapping information. the pmb has 16 en tries and configuration of each entry is as follows.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 190 of 1286 rej09b0158-0100 ppn [31:24] ppn [31:24] ppn [31:24] sz [1:0] sz [1:0] sz [1:0] c c c ub ub ub vpn [31:24] vpn [31:24] vpn [31:24] v v v entry 0 entry 1 entry 2 wt wt wt ppn [31:24] sz [1:0] c ub vpn [31:24] v entry 15 wt figure 7.17 pmb configuration [legend] ? ? ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 191 of 1286 rej09b0158-0100 with a 512-mbyte page, ppn[31:29] are valid. ? ? ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 192 of 1286 rej09b0158-0100 vpn[31:30] is 10 or not. when an entry from the pmb is recorded in the itlb, h
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 193 of 1286 rej09b0158-0100 address field data field vpn: v: e: physical page number validity bit entry : reserved bits (write value should be 0 and read value is undefined ) 31 0 v 8 8 7 vpn 31 19 20 0 11110 000 11 01 00 e 23 24 12 11 00000 00000 000 0 figure 7.18 memory-mapped pmb address array address field data field ppn: v: e: sz: physical page number validity bit entry page size bits ub : c: wt: : buffered write bit cacheability bit write-through bit reserved bits (write value should be 0 and read value is undefined ) 31 210 v ub 10 9 8 743 65 c ppn 31 0 1111011 10 001 e 23 24 19 20 8 7 12 11 sz wt 00000000 00000000 figure 7.19 memory-m apped pmb data array
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 194 of 1286 rej09b0158-0100 7.7.6 notes on using 32-bit address extended mode when using 32-bit address extended mode, note that the items described in this section are extended or changed as follows. pascr: the se bit is added in bit 31 in the contro l register (pascr). the bits 6 to 0 of the ub in the pascr are invalid (note that the bit 7 of the ub is still valid). when writing to the p1 or p2 area, the ub bit in the pmb controls whether a buffered write is perfo rmed or not. when the mmu is enabled, the ub bit in the tlb controls writing to the p0, p3, or u0 area. when the mmu is disabled, writing to the p0, p3, or u0 ar ea is always performed as a buffered write. bit bit name initial value r/w description 31 se 0 r/w 0: 29-bit address mode 1: 32-bit address extended mode 30 to 8 ? all 0 r reserved for details on reading from or writing to these bits, see description in general precautions on handling of product. 7 to 0 ub all 0 r/w buffered write control for each area (64 mbytes) when writing is performed wit hout using the cache or in the cache write-through mode, these bits specify whether the cpu waits for the end of writing for each area. 0: the cpu does not wait for the end of writing 1: the cpu stalls and wa its for the end of writing ub[7]: corresponding to the control register area ub[6:0]: these bits are invalid in 32-bit address extended mode.
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 195 of 1286 rej09b0158-0100 itlb: the ppn field in the itlb is extended to bits 31 to 10. utlb: the ppn field in the utlb is extended to bits 31 to 10. the same ub bit as that in the pmb is added in each entry of the utlb. ?
section 7 memory management unit (mmu) rev.1.00 dec. 13, 2005 page 196 of 1286 rej09b0158-0100 4. note that the v bit is mapped to both address array and data array in pmb registration. that is, first write 0 to the v bit in one of arrays an d then write 1 to the v bit in another array.
section 8 caches rev.1.00 dec. 13, 2005 page 197 of 1286 rej09b0158-0100 section 8 caches this lsi has an on-chip 32-kbyte instruction cache (ic) for instructions and an on-chip 32-kbyte operand cache (oc) for data. 8.1 features the features of the cache are shown in table 8.1. this lsi supports two 32-byte store queues (sqs) to perform high-speed writes to external memory. the features of the store queues are given in table 8.2. table 8.1 cache features item instruction cache operand cache capacity 32-kbyte cache 32-kbyte cache type 4-way set-associative, virtual address index/physical address tag 4-way set-associative, virtual address index/physical address tag line size 32 bytes 32 bytes entries 256 entries/way 256 entries/way write method ? copy-back/write-through selectable replacement method lru (least-recently-used) algorithm lru (least-recently-used) algorithm table 8.2 store queue features item store queues capacity 32 bytes 2 addresses h'e000 0000 to h'e3ff ffff write store instruct ion (1-cycle write) write-back prefetch instru ction (pref instruction) access right when mmu is disabled: determined by sqmd bit in mmucr when mmu is enabled: determined by pr for each page
section 8 caches rev.1.00 dec. 13, 2005 page 198 of 1286 rej09b0158-0100 the operand cache of this lsi uses the 4-way set-associative, each wa y comprising 256 cache lines. figure 8.1 shows the configuration of the operand cache. the instruction cache is 4-way set- associative, each way is comprisi ng 256 cache lines. figure 8.2 shows the configuration of the instruction cache. comparison 31 54 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits 6 bits mmu [12:5] 255 19 bits 1 bit 1 bit tag u v address array (way 0 to way 3) data array (way 0 to way 3) lru entry selection longword (lw) selection virtual address 3 8 22 19 0 write data read data hit signal (way 0 to way 3) 12 10 0 figure 8.1 configuratio n of operand cache (oc)
section 8 caches rev.1.00 dec. 13, 2005 page 199 of 1286 rej09b0158-0100 31 54 2 lw0 32 bits lw1 32 bits lw2 32 bits lw3 32 bits lw4 32 bits lw5 32 bits lw6 32 bits lw7 32 bits [12:5] 255 19 bits 1 bit tag v address array (way 0 to way 3) data array (way 0 to way 3) entry selection longword (lw) selection virtual address 3 8 22 19 0 read data 13 12 10 0 6 bits lru hit signal (way 0 to way 3) comparison mmu figure 8.2 configuration of instruction cache (ic) ? ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 200 of 1286 rej09b0158-0100 ? ? register name abbreviation r/w p4 address * area 7 address * access size cache control register ccr r/w h ' ff00 001c h ' 1f00 001c 32 queue address control register 0 qacr0 r/w h ' ff00 0038 h ' 1f00 0038 32 queue address control register 1 qacr1 r/w h ' ff00 003c h ' 1f00 003c 32 on-chip memory control register ramcr r/w h ' ff00 0074 h ' 1f00 0074 32 note: * these p4 addresses are for the p4 area in the virtual address space. these area 7 addresses are accessed from area 7 in the physical address space by means of the tlb. table 8.4 register states in each processing state register name abbreviation power-on reset manual reset sleep cache control register ccr h ' 0000 0000 h ' 0000 0000 retained queue address control register 0 qacr0 undefined undefined retained queue address control register 1 qacr1 undefined undefined retained on-chip memory control register ramcr h ' 0000 0000 h ' 0000 0000 retained
section 8 caches rev.1.00 dec. 13, 2005 page 201 of 1286 rej09b0158-0100 8.2.1 cache control register (ccr) ccr controls the cache operating mode, the cach e write mode, and invalidation of all cache entries. ccr modifications must only be made by a progra m in the non-cacheable p2 area. after ccr has been updated, execu te one of the following three met hods before an access (including an instruction fetch) to the cacheable area is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be the cacheable area. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the r2 bit in irmcr is 0 (initial value) before updating ccr, the specific instruction does not need to be executed. however, note that the cpu processing performance will be lowered because the instruction fetch is performed agai n for the next instruction after ccr has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 initial value: rrrrrrrrrrrrrrrr r r r r r/w r r r/w r r r r r/w r/w r/w r/w r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 00 00 000 ici ice oce wt cb oci 0 bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 ici 0 r/w ic invalidation bit when 1 is written to this bit, the v bits of all ic entries are cleared to 0. this bit is always read as 0.
section 8 caches rev.1.00 dec. 13, 2005 page 202 of 1286 rej09b0158-0100 bit bit name initial value r/w description 10, 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 ice 0 r/w ic enable bit selects whether the ic is used. note however when address translation is performed, the ic cannot be used unless the c bit in the page management information is also 1. 0: ic not used 1: ic used 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 oci 0 r/w oc invalidation bit when 1 is written to this bit, the v and u bits of all oc entries are cleared to 0. this bit is always read as 0. 2 cb 0 r/w copy-back bit indicates the p1 area cache write mode. 0: write-through mode 1: copy-back mode 1 wt 0 r/w write-through mode indicates the p0, u0, and p3 area cache write mode. when address translation is pe rformed, the value of the wt bit in the page management information has priority. 0: copy-back mode 1: write-through mode 0 oce 0 r/w oc enable bit selects whether the oc is used. note however when address translation is performed, the oc cannot be used unless the c bit in the page management information is also 1. 0: oc not used 1: oc used
section 8 caches rev.1.00 dec. 13, 2005 page 203 of 1286 rej09b0158-0100 8.2.2 queue address cont rol register 0 (qacr0) qacr0 specifies the area maped which store queue 0 (sq0) is mapped when the mmu is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: initial value: rrrrrrrrrrrrrrrr 0000000000000000 00000000000 00 r r r r r r r r r r r r/w r/w r/w r r r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 area0 bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 to 2 area0 undefined r/w when the mmu is disabled, these bits generate physical address bits [28:26] for sq0. 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 8 caches rev.1.00 dec. 13, 2005 page 204 of 1286 rej09b0158-0100 8.2.3 queue address cont rol register 1 (qacr1) qacr1 specifies the area onto which store queue 1 (sq1) is mapped when the mmu is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: initial value: rrrrrrrrrrrrrrrr 0000000000000000 00000000000 00 r r r r r r r r r r r r/w r/w r/w r r r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 area1 bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 to 2 area1 undefined r/w when the mmu is disabled, these bits generate physical address bits [28:26] for sq1. 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 8 caches rev.1.00 dec. 13, 2005 page 205 of 1286 rej09b0158-0100 8.2.4 on-chip memory control register (ramcr) ramcr controls the number of ways in the ic and oc. ramcr modifications must only be made by a program in the non-cacheable p2 area. after ramcr has been updated, execute one of th e following three methods before an access (including an instruction fetch) to the cacheab le area or the l memory area is performed. 1. execute a branch using the rte instruction. in this case, the branch destination may be the non-cacheable area or the l memory area. 2. execute the icbi instruction for any address (including non-cacheable area). 3. if the r2 bit in irmcr is 0 (initial value) before updating ramcr, the specific instruction does not need to be executed. however, note that the cpu processing performance will be lowered because the instruction fetch is performed again for the next instruction after ramcr has been updated. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: initial value: rrrrrrrrrr rmd rp ic2w oc2w rrrrrr 0000000000000000 0000000000000000 r r r r r r r/w r/w r/w r/w r r r r r r r/w: bit: initial value: r/w: 151413121110987654321 0
section 8 caches rev.1.00 dec. 13, 2005 page 206 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 rmd 0 r/w on-chip memory access mode bit for details, see section 9.4, l memory protective functions. 8 rp 0 r/w on-chip memory protection enable bit for details, see section 9.4, l memory protective functions. 7 ic2w 0 r/w ic two-way mode bit 0: ic is a four-way operation 1: ic is a two-way operation for details, see section 8.4.3, ic two-way mode. 6 oc2w 0 r/w oc two-way mode bit 0: oc is a four-way operation 1: oc is a two-way operation for details, see section 8.3.6, oc two-way mode. 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 8 caches rev.1.00 dec. 13, 2005 page 207 of 1286 rej09b0158-0100 8.3 operand cache operation 8.3.1 read operation when the operand cache (oc) is enabled (oce = 1 in ccr) and data is read from a cacheable area, the cache operates as follows: 1. the tag, v bit, u bit, and lru bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. the tag read from the each way is compared w ith bits [28:10] of the physical address resulting from virtual address translation by the mmu: ? ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 208 of 1286 rej09b0158-0100 5. cache miss (with write-back) the tag and data field of the cache line on the wa y which is selected to replace are saved in the write-back buffer. then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data, and when the corresponding data arrives in the cache, the read data is returned to the cpu. while the re maining one cache line of data is being read, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the phys ical address is recorded in the cache, 1 is written to the v bit, and 0 to the u bit. and the lru bits are updated to in dicate the way is latest one. the data in the write-back buffer is then written back to external memory. 8.3.2 prefetch operation when the operand cache (oc) is enabled (oce = 1 in ccr) and data is prefetched from a cacheable area, the cache operates as follows: 1. the tag, v bit, u bit, and lru bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. the tag, read from each way, is compared with bits [28:10] of the physical ad dress resulting from virtual address translation by the mmu: ? ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 209 of 1286 rej09b0158-0100 5. cache miss (with write-back) the tag and data field of the cache line on the wa y which is selected to replace are saved in the write-back buffer. then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address. data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data. in the prefet ch operation the cpu doesn't wait the data arrives. while the one cache line of data is being read, the cpu can execute the next processing. and the lru bits are updated to indicate the way is latest one. the data in the write-back buffer is then written back to external memory. 8.3.3 write operation when the operand cache (oc) is enabled (oce = 1 in ccr) and data is written to a cacheable area, the cache operates as follows: 1. the tag, v bit, u bit, and lru bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. the tag, read from each way, is compared with bits [28:10] of the physical ad dress resulting from virtual address translation by the mmu: ? ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 210 of 1286 rej09b0158-0100 5. cache miss (copy- back, no write-back) a data write in accordance with the access size is performed for the data of the data field on the hit way which is indexed by virtual address bits [4:0]. then, the data, excluding the cache- missed data which is written already, is read into the cache line on the way which is selected to replace from the physical ad dress space corresponding to the virtual address. data reading is performed, using the wraparound method, in order from the quad-word data (8 bytes) including the cache-missed data. while the remaining data on the cache line is being read, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is written to the v bit and the u bit on the way. then the lru bit is updated to indicate the way is latest one. 6. cache miss (copy- back, with write-back) the tag and data field of the cache line on the wa y which is selected to replace are saved in the write-back buffer. then a data write in accor dance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0]. then, the data, excluding the cache-missed data which is written already, is read into the cache line on the way which is selected to replace from the phy sical address space corres ponding to the virtual address. data reading is performed, using the wraparound method, in order from the quad- word data (8 bytes) including the cache-misse d data. while the remaining data on the cache line is being read, the cpu can execute the next processing. when reading of one line of data is completed, the tag corresponding to the phys ical address is recorded in the cache, 1 is written to the v bit and the u bit on the way. then the lru bit is updated to indicate the way is latest one. then the data in the write-back bu ffer is then written back to external memory. 7. cache miss (write-through) a write of the specified access si ze is performed to the external memory corres ponding to the virtual address. in this case, a write to cache is not performed.
section 8 caches rev.1.00 dec. 13, 2005 page 211 of 1286 rej09b0158-0100 8.3.4 write-back buffer in order to give priority to da ta reads to the cache and improve pe rformance, this lsi has a write- back buffer which holds the releva nt cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. the write -back buffer contains one cache line of data and the physical addr ess of the purge destination. lw7 physical address bits [28:5] lw6 lw5 lw4 lw3 lw2 lw1 lw0 figure 8.3 configuration of write-back buffer 8.3.5 write-through buffer this lsi has a 64-bit buffer for holding write da ta when writing data in write-through mode or writing to a non-cacheable area. this allows the cp u to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. physical address bits [28:0] lw1 lw0 figure 8.4 configuration of write-through buffer 8.3.6 oc two-way mode when the oc2w bit in ramcr is set to 1, oc two-way mode which only uses way 0 and way 1 in the oc is entered. thus, power consumption can be reduced. in this mode, only way 0 and way 1 are used even if a memory-mapped oc access is made. the oc2w bit should be modified by a program in the p2 area. at that time, if the valid line has already been recorded in the oc, data should be written back by software, if necessary, 1 should be written to the oci bit in ccr, and all entries in the oc should be invalid before modifying the oc2w bit.
section 8 caches rev.1.00 dec. 13, 2005 page 212 of 1286 rej09b0158-0100 8.4 instruction cache operation 8.4.1 read operation when the ic is enabled (ice = 1 in ccr) and in struction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. the tag, v bit, u bit and lru bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. the tag, read from each way, is compared with bits [28:10] of the physical ad dress resulting from virtual address translation by the mmu: ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 213 of 1286 rej09b0158-0100 8.4.2 prefetch operation when the ic is enabled (ice = 1 in ccr) and instruction prefetches are performed from a cacheable area, the instruction cache operates as follows: 1. the tag, v bit, ubit and lru bits on each way are read from the cache line indexed by virtual address bits [12:5]. 2. the tag, read from each way, is compared with bits [28:10] of the physical ad dress resulting from virtual address translation by the mmu: ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 214 of 1286 rej09b0158-0100 8.5 cache operation instruction 8.5.1 coherency between ca che and external memory coherency between cache and external memory should be assured by software. in this lsi, the following six instructions are supported for cach e operations. details of these instructions are given in the software manual. ? ? ? ? ? ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 215 of 1286 rej09b0158-0100 purge transaction: when the operand cache is enabled, the purge transaction checks the operand cache and invalidates the hit en try. if the invalidated entry is dirty, the data is written back to the external memory. if the transaction is not hit to the cache, it is no-operation. flush transaction: when the operand cache is enabled, the flush transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory. if the transaction is not hit to the cache or the hit entry is no t dirty, it is no-operation. 8.5.2 prefetch operation this lsi supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. if it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data before hand by means of the prefetch in struction to prevent a cache miss due to the read or write operation, and so improve software performance. if a prefetch instruction is executed for data already held in the cache, or if the prefetch address re sults in a utlb miss or a protection violation, the result is no operation, and an exception is not generated. details of the prefetch instruction are given in the software manual. ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 216 of 1286 rej09b0158-0100 8.6 memory-mapped cache configuration to enable the ic and oc to be managed by software, the ic contents can be read from or written to by a program in the p2 area by means of a mov instruction in privileged mode. operation is not guaranteed if access is made from a program in another area. in this case, execute one of the following three methods for executing a branch to the p0, u0, p1, or p3 area. 1. execute a branch using the rte instruction. 2. execute a branch to the p0, u0, p1, or p3 area after executin g the icbi instruction for any address (including non-cacheable area). 3. if the mc bit in irmcr is 0 (initial value) before making an acces s to the memory-mapped ic, the specific instruction does not need to be executed. however, note that the cpu processing performance will be lowered because the instruction fetch is performed again for the next instruction af ter making an access to the memory-mapped ic. note that the method 3 may not be guaranteed in the future su perh series. therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future superh series. in privileged mode, the oc contents can be read from or written to by a program in the p1 or p2 area by means of a mov instruction. operation is not guaranteed if access is made from a program in another area. the ic and oc are allocat ed to the p4 area in the virtual address space. only data accesses can be used on both the ic address array and data array and the oc address array and data array, and accesses are always longword-size. instruction fetches cannot be performed in these areas. for rese rved bits, a write value of 0 sh ould be specified and the read value is undefined.
section 8 caches rev.1.00 dec. 13, 2005 page 217 of 1286 rej09b0158-0100 8.6.1 ic address array the ic address array is allocated to addresses h' f000 0000 to h'f0ff ffff in the p4 area. an address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the write tag and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f0 indicating the ic address array, and the way is specified by bits [14:13] and the entry by bits [12:5]. the association bit (a bit) [3] in the address field specifies whether or not association is performed when writi ng to the ic address array. as only longword access is used, 0 shoul d be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [ 31:10], and the v bit by bit [0]. as the ic address array tag is 19 bits in length, data field bits [ 31:29] are not used in the case of a write in which association is not performed. data field bits [3 1:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the ic address array: 1. ic address array read the tag and v bit are read into the data field from the ic entry corresponding to the way and entry set in the address field. in a read, asso ciative operation is not performed regardless of whether the association b it specified in the address field is 1 or 0. 2. ic address array write (non-associative) the tag and v bit specified in the data field ar e written to the ic entry corresponding to the way and entry set in the address field. the a bit in the address field should be cleared to 0. 3. ic address array write (associative) when a write is performed with the a bit in th e address field set to 1, the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field. the way numbers of bits [14:13] in the address field are not used. if the mmu is enabled at this time, comparison is performed after th e virtual address specified by data field bits [31:10] has been translated to a physical addr ess using the itlb. if the addresses match and the v bit in the way is 1, the v bit specified in the data field is written into the ic entry. in other cases, no operation is performed. this opera tion is used to invalidat e a specific ic entry. if an itlb miss occurs during address transla tion, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. note: this function may not be supported in the future superh series. therefore, it is recommended that the icbi instruction should be used to operate the ic definitely by handling itlb miss and reporting itlb miss exception.
section 8 caches rev.1.00 dec. 13, 2005 page 218 of 1286 rej09b0158-0100 address field 31 23 12 543210 11110000 0 000 entry a data field 31 10 9 1 0 v tag way v a 24 13 14 15 : validity bit : association bit : reserved bits (write value should be 0 and read value is undefined ) : don't care * ********* figure 8.5 memory-mapped ic address array
section 8 caches rev.1.00 dec. 13, 2005 page 219 of 1286 rej09b0158-0100 8.6.2 ic data array the ic data array is allocated to addresses h'f1 00 0000 to h'f1ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f1 indicating the ic data array, and the way is specified by bits [14:13] and the entry by bits [12:5]. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the ic data array: 1. ic data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the ic entry corre sponding to the way and entry set in the address field. 2. ic data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the ic entry corresponding to the way and entry set in the address field. address field 31 23 12 5 4 2 1 0 11110001 entry l data field 31 0 longword data l * 24 13 14 15 : longword specification bits : don't care way 00 ********* figure 8.6 memory-mapped ic data array
section 8 caches rev.1.00 dec. 13, 2005 page 220 of 1286 rej09b0158-0100 8.6.3 oc address array the oc address array is allocated to addresses h'f400 0000 to h'f4ff ffff in the p4 area. an address array access requires a 32 -bit address field specification (when reading or writing) and a 32-bit data field specification. th e way and entry to be accessed are specified in the address field, and the write tag, u bit, and v bit are specified in the data field. in the address field, bits [31:24] have the value h'f4 indicating the oc address array, and the way is specified by bits [14:13] and the entry by bits [12:5]. the association bit (a bit) [3] in the address field specifies whether or not association is performed when writi ng to the oc address array. as only longword access is used, 0 shoul d be specified for address field bits [1:0]. in the data field, the tag is indicated by bits [31:10], the u bit by bit [1], and the v bit by bit [0]. as the oc address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. the following three kinds of operation can be used on the oc address array: 1. oc address array read the tag, u bit, and v bit are read into the data field from the oc entry corresponding to the way and entry set in the address field. in a read, associative operation is not performed regardless of whether the association bit sp ecified in the address field is 1 or 0. 2. oc address array write (non-associative) the tag, u bit, and v bit specified in the data fi eld are written to the oc entry corresponding to the way and entry set in the address field. the a b it in the address field sh ould be cleared to 0. when a write is performed to a cache line for which the u bit and v bit are both 1, after write- back of that cache line, the ta g, u bit, and v bit specified in the data field are written. 3. oc address array write (associative) when a write is performed with the a bit in th e address field set to 1, the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field. the way numbers of bits [14:13] in the address field are not used. if the mmu is enabled at this time, comparison is performed after th e virtual address specified by data field bits [31:10] has been translated to a physical addr ess using the utlb. if the addresses match and the v bit in the way is 1, the u bit and v bit specified in the data field are written into the oc entry. in other cases, no operation is performed. this operation is used to invalidate a specific oc entry. if the oc entry u bit is 1, and 0 is wri tten to the v bit or to the u bit, write-back is performed. if a utlb miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no op eration is performed, and the write is not executed.
section 8 caches rev.1.00 dec. 13, 2005 page 221 of 1286 rej09b0158-0100 note: this function may not be supported in the future superh series. therefore, it is recommended that the ocbi, ocbp , or ocbwb instruction should be used to operate the oc definitely by reporting data tlb miss exception. address field 31 23 543210 11110100 entry a data field 31 10 9 1 0 v tag 24 13 12 14 15 2 u v u a : validity bit : dirty bit : association bit : reserved bits (write value should be 0 and read value is undefined ) : don't care way 0 000 ********* * figure 8.7 memory-mapped oc address array
section 8 caches rev.1.00 dec. 13, 2005 page 222 of 1286 rej09b0158-0100 8.6.4 oc data array the oc data array is allocated to addresses h'f5 00 0000 to h'f5ff ffff in the p4 area. a data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. the way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. in the address field, bits [31:24] have the value h'f5 indicating the oc data array, and the way is specified by bits [14:13] and the entry by bits [12:5]. address field bits [4:2] are used for the longword data specification in the entry. as only longword access is used, 0 should be specified for address field bits [1:0]. the data field is used for th e longword data specification. the following two kinds of operation can be used on the oc data array: 1. oc data array read longword data is read into the data field from the data specified by the longword specification bits in the address field in the oc entry corresponding to the way and entry set in the address field. 2. oc data array write the longword data specified in th e data field is written for the data specified by the longword specification bits in the address field in the oc entry corresponding to the way and entry set in the address field. this write does not set the u bit to 1 on the address array side. address field 31 23 543210 11110101 entry data field 31 0 longword data 24 1312 14 15 l * : longword specification bits : don't care way 0 l0 ********* figure 8.8 memory-mapped oc data array
section 8 caches rev.1.00 dec. 13, 2005 page 223 of 1286 rej09b0158-0100 8.7 store queues this lsi supports two 32-byte store queues (sqs) to perform high-speed writes to external memory. 8.7.1 sq configuration there are two 32-byte store queues, sq0 and sq1, as shown in figure 8.9. these two store queues can be set independently. sq0 sq0[0] sq0[1] sq0[2] sq0[3] sq0[4] sq0[5] sq0[6] sq0[7] sq1 sq1[0] sq1[1] sq1[2] sq1[3] sq1[4] sq1[5] sq1[6] sq1[7] 4b 4b 4b 4b 4b 4b 4b 4b figure 8.9 store queue configuration 8.7.2 writing to sq a write to the sqs can be performed using a store instruction for addresses h'e000 0000 to h'e3ff fffc in the p4 area. a longword or quadword access size can be used. the meanings of the address bits are as follows: [31:26] : 111000 store queue specification [25:6] : don't care used for exte rnal memory transfer/access right [5] : 0/1 0: sq0 specification 1: sq1 specification [4:2] : lw specification specifies longword position in sq0/sq1 [1:0] : 00 fixed at 0
section 8 caches rev.1.00 dec. 13, 2005 page 224 of 1286 rej09b0158-0100 8.7.3 transfer to external memory transfer from the sqs to external memory can be performed with a prefet ch instruction (pref). issuing a pref instruction for addresses h'e000 0000 to h'e3ff fffc in the p4 area starts a transfer from the sqs to external memory. the transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. while the contents of one sq are being transferred to external memory, the other sq can be written to without a penalty cycle. however, writing to the sq involved in the transfer to external memory is kept waiting until the transfer is completed. the physical address bits [28:0] of the sq transfer destinatio n are specified as shown below, according to whether the mmu is enabled or disabled. ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 225 of 1286 rej09b0158-0100 8.7.4 determination of sq access exception determination of an exception in a write to an sq or transfer to external memory (pref instruction) is performed as follows according to whether the mmu is enabled or disabled. if an exception occurs during a write to an sq, the sq contents before the writ e are retained. if an exception occurs in a data transfer from an sq to external memory, the transfer to external memory will be aborted. ? ?
section 8 caches rev.1.00 dec. 13, 2005 page 226 of 1286 rej09b0158-0100 8.8 notes on using 32-bit address extended mode in 32-bit address extended mode, the items described in this section are extended as follows. 1. the tag bits [28:10] (19 bits) in the ic and oc are extended to bits [31:10] (22 bits). 2. an instruction which operates the ic (a memo ry-mapped ic access and writing to the ici bit in ccr) should be located in the p1 or p2 area. the cacheable bit (c bit) in the corresponding entry in the pmb should be 0. 3. bits [4:2] (3 bits) for the area0 bit in qacr0 and the area1 bit in qacr1 are extended to bits [7:2] (6 bits).
section 9 l memory rev.1.00 dec. 13, 2005 page 227 of 1286 rej09b0158-0100 section 9 l memory this lsi includes on-chip l-memory which stores instructions or data. 9.1 features ? ? ? memory size (two pages total) page 16 kbytes page 0 of l memory h'e500e000 to h'e500ffff page 1 of l memory h' e5010000 to h'e5011fff ? ?
section 9 l memory rev.1.00 dec. 13, 2005 page 228 of 1286 rej09b0158-0100 9.2 register descriptions the following registers are related to l memory. table 9.2 register configuration register name abbreviation r/w p4 address * area 7 address * access size on-chip memory control register ramcr r/w h'ff000074 h'1f000074 32 l memory transfer source address register 0 lsa0 r/w h'ff000050 h'1f000050 32 l memory transfer source address register 1 lsa1 r/w h'ff000054 h'1f000054 32 l memory transfer destination address register 0 lda0 r/w h'ff000058 h'1f000058 32 l memory transfer destination address register 1 lda1 r/w h'ff00005c h'1f00005c 32 note: * the p4 address is the address used when usi ng p4 area in the virtual address space. the area 7 address is the address used when accessing from area 7 in the physical address space using the tlb. table 9.3 register status in each processing state name abbreviation power-on reset manual reset sleep on-chip memory control register ramcr h'00000000 h'00000000 retained l memory transfer source address register 0 lsa0 undefined undefined retained l memory transfer source address register 1 lsa1 undefined undefined retained l memory transfer destination address register 0 lda0 undefined undefined retained l memory transfer destination address register 1 lda1 undefined undefined retained
section 9 l memory rev.1.00 dec. 13, 2005 page 229 of 1286 rej09b0158-0100 9.2.1 on-chip memory control register (ramcr) ramcr controls the protective functions in the l memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit : 0000000000000000 rmd rp ic2w oc2w initial value : rrrrrrrrrrrrrrrr r/w: 151413121110987654321 0 bit : 00000000 0 0000000 initial value : rrrrrrr/wr/wr/wr/wrrrrrr r/w: bit bit name initial value r/w description 31to10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 rmd 0 r/w on-chip memory access mode specifies the right of access to the l memory from the virtual address space. 0: an access in privileged mode is allowed. (an address error exception occurs in user mode.) 1: an access user/privileged mode is allowed. 8 rp 0 r/w on-chip memory protection enable selects whether or not to us e the protective functions using itlb and utlb for accessing the l memory from the virtual address space. 0: protective functions are not used. 1: protective functions are used. for further details, refer to section 9.4, l memory protective functions. 7 ic2w 0 r/w ic two-way mode for further details, refer to section 8.4.3, ic two-way mode. 6 oc2w 0 r/w oc two-way mode for further details, refer to section 8.3.6, oc two-way mode. 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 9 l memory rev.1.00 dec. 13, 2005 page 230 of 1286 rej09b0158-0100 9.2.2 l memory transfer source address register 0 (lsa0) when mmucr.at = 0 or ramcr.rp = 0, the ls a0 specifies the tran sfer source physical address for block transfer to page 0 of the l memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit : 000 initial value : r r r r/w r/w r/w r/w r/w r/w r/w l0sadr l0sadr l0ssz r/w r/w r/w r/w r/w r/w r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : 00 0 0 initial value : r/w r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w: bit bit name initial value r/w description 31 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 28 to 10 l0sadr undefined r/w l memory page 0 block transfer source address when mmucr.at = 0 or ramcr.rp = 0, these bits specify the transfer source physical address for block transfer to page 0 in the l memory. 9 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 9 l memory rev.1.00 dec. 13, 2005 page 231 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 to 0 l0ssz undefined r/w l memory page 0 block transfer source address select when mmucr.at = 0 or ramcr.rp = 0, these bits select whether the operand addresses or l0sadr values are used as bits 15 to 10 of the transfer source physical address for block transfer to the l memory. l0ssz[5:0] correspond to t he transfer source physical addresses[15:10]. 0: the operand address is used as the transfer source physical address. 1: the l0sadr value is used as the transfer source physical address. settable values: 111111: transfer source physical address is specified in 1-kbyte units. 111110: transfer source physical address is specified in 2-kbyte units. 111100: transfer source physical address is specified in 4-kbyte units. 111000: transfer source physical address is specified in 8-kbyte units. 110000: transfer source physical address is specified in 16-kbyte units. 100000: transfer source physical address is specified in 32-kbyte units. 000000: transfer source physical address is specified in 64-kbyte units. settings other than the ones given above are prohibited.
section 9 l memory rev.1.00 dec. 13, 2005 page 232 of 1286 rej09b0158-0100 9.2.3 l memory transfer source address register 1 (lsa1) when mmucr.at = 0 or ramcr.rp = 0, the ls a1 specifies the tran sfer source physical address for block transfer to page 1 in the l memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit : 000 initial value : r r r r/w r/w r/w r/w r/w r/w r/w l1dadr l1dadr l1dsz r/w r/w r/w r/w r/w r/w r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : 00 0 0 initial value : r/w r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w: bit bit name initial value r/w description 31 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 28 to 10 l1sadr undefined r/w l memory page 1 block transfer source address when mmucr.at = 0 or ramcr.rp = 0, these bits specify transfer source physical address for block transfer to page 1 in the l memory. 9 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 9 l memory rev.1.00 dec. 13, 2005 page 233 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 to 0 l1ssz undefined r/w l memory page 1 block transfer source address select when mmucr.at = 0 or ramcr.rp = 0, these bits select whether the operand addresses or l1sadr values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1 in the l memory. l1ssz bits [5:0] correspond to the transfer source physical addresses [15:10]. 0: the operand address is used as the transfer source physical address. 1: the l1sadr value is used as the transfer source physical address. settable values: 111111: transfer source physical address is specified in 1-kbyte units. 111110: transfer source physical address is specified in 2-kbyte units. 111100: transfer source physical address is specified in 4-kbyte units. 111000: transfer source physical address is specified in 8-kbyte units. 110000: transfer source physical address is specified in 16-kbyte units. 100000: transfer source physical address is specified in 32-kbyte units. 000000: transfer source physical address is specified in 64-kbyte units. settings other than the ones given above are prohibited.
section 9 l memory rev.1.00 dec. 13, 2005 page 234 of 1286 rej09b0158-0100 9.2.4 l memory transfer destinat ion address register 0 (lda0) when mmucr.at = 0 or ramcr.rp = 0, lda0 specifies the transfer destination physical address for block transfer to page 0 of the l memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit : 000 initial value : r r r r/w r/w r/w r/w r/w r/w r/w l0sadr l0sadr l0ssz r/w r/w r/w r/w r/w r/w r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : 00 0 0 initial value : r/w r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w: bit bit name initial value r/w description 31 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 28 to 10 l0dadr undefined r/w l memory page 0 block transfer destination address when mmucr.at = 0 or ramcr.rp = 0, these bits specify transfer destination physical address for block transfer to page 0 in the l memory. 9 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 9 l memory rev.1.00 dec. 13, 2005 page 235 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 to 0 l0dsz undefined r/w l memory page 0 block transfer destination address select when mmucr.at = 0 or ramcr.rp = 0, these bits select whether the operand addresses or l0dadr values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0 in the l memory. l0dsz bits [5:0] correspond to the transfer destination physical address bits [15:10]. 0: the operand address is used as the transfer destination physical address. 1: the l0dadr value is used as the transfer destination physical address. settable values: 111111: transfer destination physical address is specified in 1-kbyte units. 111110: transfer destination physical address is specified in 2-kbyte units. 111100: transfer destination physical address is specified in 4-kbyte units. 111000: transfer destination physical address is specified in 8-kbyte units. 110000: transfer destination physical address is specified in 16-kbyte units. 100000: transfer destination physical address is specified in 32-kbyte units. 000000: transfer destination physical address is specified in 64-kbyte units. settings other than the ones given above are prohibited.
section 9 l memory rev.1.00 dec. 13, 2005 page 236 of 1286 rej09b0158-0100 9.2.5 l memory transfer destinat ion address register 1 (lda1) when mmucr.at = 0 or ramcr.rp = 0, lda1 specifies the transfer destination physical address for block transfer to page 1 in the l memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit : 000 initial value : r r r r/w r/w r/w r/w r/w r/w r/w l1sadr l1sadr l1ssz r/w r/w r/w r/w r/w r/w r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : 00 0 0 initial value : r/w r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w: bit bit name initial value r/w description 31 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 28 to 10 l1dadr undefined r/w l memory page 1 block transfer destination address when mmucr.at = 0 or ramcr.rp = 0, these bits specify transfer destination physical address for block transfer to page 1 in the l memory. 9 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 9 l memory rev.1.00 dec. 13, 2005 page 237 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 to 0 l1dsz undefined r/w l memory page 1 block transfer destination address select when mmucr.at = 0 or ramcr.rp = 0, these bits select whether the operand addresses or l1dadr values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1 in the l memory. l1dsz bits [5:0] correspond to the transfer destination physical addresses [15:10]. 0: the operand address is used as the transfer destination physical address. 1: the l1dadr value is used as the transfer destination physical address. settable values: 111111: transfer destination physical address is specified in 1-kbyte units. 111110: transfer destination physical address is specified in 2-kbyte units. 111100: transfer destination physical address is specified in 4-kbyte units. 111000: transfer destination physical address is specified in 8-kbyte units. 110000: transfer destination physical address is specified in 16-kbyte units. 100000: transfer destination physical address is specified in 32-kbyte units. 000000: transfer destination physical address is specified in 64-kbyte units. settings other than the ones given above are prohibited.
section 9 l memory rev.1.00 dec. 13, 2005 page 238 of 1286 rej09b0158-0100 9.3 operation 9.3.1 access from the cpu and fpu l memory access from the cpu and fpu is direct via the instruction bus and operand bus by means of the virtual address. as long as there is no conflict on the page, the l memory is accessed in one cycle. 9.3.2 access from the superhyway bus master module l memory is always accessed by the superhyway bus master mo dule, such as dmac, via the superhyway bus which is a physical address bus. the same addresses as for the virtual addresses must be used. 9.3.3 block transfer high-speed data transfer can be performed through block transfer between the l memory and external memory without cache utilization. data can be transferred from the external memory to the l memory through a prefet ch instruction (pref). block transfer from th e external memory to the l memory begins when the pref instruction is issued to the address in th e l memory area in the virtual address space. data can be transferred from the l memory to the external memory through a write-back instruction (ocbwb). block transfer from the l me mory to the external memory begins when the ocbwb instruction is issu ed to the address in the l memory area in the virtual address space. in either case, transfer rate is fixed to 32 bytes. since the start address is always limited to a 32- byte boundary, the lower five bits of the address in dicated by rn are ignored, and are always dealt with as all 0s. in either case, other pages and cache can be accessed during block transfer, but the cpu will stall if the page which is being tran sferred is accessed before data transfer ends. the physical addresses [28:0] of the external memory perform ing data transfers with the l memory are specified as follows according to whether the mmu is enabled or disabled. when mmu is enabled (mmucr.at = 1) and ramcr.rp = 1: an address of the l memory area is specified to the utlb vpn field, and to th e physical address of the transfer source (in the case of the pref instruction) or the transfer destination (in the cas e of the ocbwb instruction) to the ppn field. the asid, v, sz, sh, pr, and d bits have the same meaning as normal address conversion; however, the c and wt bits have no meaning in this page.
section 9 l memory rev.1.00 dec. 13, 2005 page 239 of 1286 rej09b0158-0100 when the pref instruction is issued to the l me mory area, addres s conversion is performed in order to generate the physical address bits [28:10 ] in accordance with the sz bit specification. the physical address bits [9:5] are generated from the virtual address prior to address conversion. the physical address bits [4:0] are fixed to 0. block transfer is performed to the l memory from the external memory which is specified by these physical addresses. when the ocbwb instruction is issued to the l me mory area, address conver sion is performed in order to generate the physical address bits [28:10 ] in accordance with the sz bit specification. the physical address bits [9:5] are generated from the virtual address prior to address conversion. the physical address bits [4:0] are fixed to 0. block transfer is performed from the l memory to the external memory specified by these physical addresses. in pref or ocbwb instruction execution, an mmu exception is checked as read type. after the mmu execution check, a tlb miss exception or prot ection error exception occurs if necessary. if an exception occurs, the block transfer is inhibited. when mmu is disabled (mmucr.at = 0) or ramcr.rp = 0: the transfer source physical address in block transfer to page 0 in the l me mory is set in the l0sadr bits of the lsa0 register. and the l0ssz bits in the lsa0 register choose either the virtual addresses specified through the prff instruction or the l0sadr values as bits 15 to 10 of the transfer source physical address. in other words, the transfer source area can be specified in units of 1 kbyte to 64 kbytes. the transfer destination physical address in block transfer from page 0 in the l memory is set in the l0dadr bits of the lda0 regi ster. and the l0dsz bits in the lda0 register choose either the virtual addresses specified through the ocbwb instruction or the l0dadr values as bits 15 to 10 of the transfer de stination physical address. in other words, the transfer source area can be specified in units of 1 kbyte to 64 kbytes. block transfer to page 1 in the l memory is set to lsa1 and lda1 as with page 0 in the l memory. when the pref instruction is issued to the l me mory area, the physical ad dress bits [28:10] are generated in accordance with the lsa0 or lsa1 specificat ion. the physical address bits [9:5] are generated from the virtual address. the physical address bits [4:0] are fixed to 0. block transfer is performed from the external me mory specified by these physical addresses to the l memory. when the ocbwb instruction is issued to the l memory area, the physical address bits [28:10] are generated in accordance with the lda0 or lda1 specification. the phys ical address bits [9:5] are generated from the virtual address. the physical address bits [4:0] are fixed to 0. block transfer is performed from the l memory to the external memory specified by these physical addresses.
section 9 l memory rev.1.00 dec. 13, 2005 page 240 of 1286 rej09b0158-0100 9.4 l memory protective functions this lsi implements the following protective functions to the l memory by using the on-chip memory access mode bit (rmd) and the on-chip memo ry protection enable bit (rp) in the on-chip memory control register (ramcr). ? mmucr.at ramcr.rp sr.md ramcr. rmd always occurring exceptions possibly occurring exceptions 0 address error exception ? 0 1 ? ? 0 * 1 * ? ? 0 address error exception ? 0 1 ? ? 0 1 * ? ? 0 address error exception ? 0 1 ? mmu exception 1 1 1 * ? mmu exception note: * : don't care
section 9 l memory rev.1.00 dec. 13, 2005 page 241 of 1286 rej09b0158-0100 9.5 usage notes 9.5.1 page conflict in the event of simultaneous access to the same page from different buses, page conflict occurs. although each access is completed co rrectly, this kind of confli ct tends to lower l memory accessibility. therefore it is advisabl e to provide all possible preven tative software measures. for example, conflicts will not occur if each bus accesses different pages. 9.5.2 l memory coherency in order to allocate instructions in the l memory , write an instruction to the l memory, execute the following sequence, then branch to the rewritten instruction. ? ?
section 9 l memory rev.1.00 dec. 13, 2005 page 242 of 1286 rej09b0158-0100
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 243 of 1286 rej09b0158-0100 section 10 interrupt controller (intc) the interrupt controller (intc) determines the prio rity of interrupt sources and controls the flow of interrupt requests to the cpu (sh-4a). the in tc has registers for setting the priority of each of the interrupts and processing of interrupt requests follows the priority order set in these registers by the user. 10.1 features sh-4 compatible specifications ? fifteen levels of external interrupt priority can be set by setting the interrupt priority registers, the pr iorities of external interrupts can be selected from 15 levels for individual request sources. ? nmi noise canceler function an nmi input-level bit indicates the nmi pin state. the bit can be read within the interrupt exception handling routine to confirm the pin state and thus achieve a form of noise cancellation. ? nmi request masking when the block bit (bl) in the status register (sr) is set to 1 masking or non-masking of nmi requests when the bl bit in sr is set to 1 can be selected. extended functions for the sh-4a ? automatically updates the imask bit in sr according to the accepted interrupt level ? thirty priority levels for in terrupts from on-chip modules by setting the interrupt priority registers (i nt2pri0 to int2pri7) for the on-chip module interrupts, any of 30 priority levels can be assigned to the individual requesting sources. ? user-mode interrupt disabling function an interrupt mask level in the user interrupt mask level register (userimask) can be specified to disable interrupts which do not have higher priority than the specified mask level. this setting can be made in user mode. figure 10.1 shows a block diagram of the intc.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 244 of 1286 rej09b0158-0100 8 nmi irq/ irl7 to irq/ irl0 irq/ irl7 and gpio port e6 are multiplexed gpio port e6 to e0 h1, h0 j0 k5, k4 irqout 12 * sr.imask nmi input control (noise canseler, detection) output control comparator comparator irl irq intpri gpio interrupt request priority determination userimask.uimask cpu exception handling interrupt acceptance icr0, icr1 bus interface priority determination bus interface peripheral bus pcic peripheral module on-chip module note: the following modules can issue peripheral module interrupts: wdt, rtc, tmu, scif, cmt, hac, siof, hspi, mmcif, ssi, flctl, h-udi dmac interrupt requests interrupt requests interrupt requests int2gpic int2pri0 to int2pri7 int2prii intc [legend] cmt: dmac: flctl: hac: hspi: h-udi: icr0, icr1: intpri: int2pri0 to int2pri7: int2gpic: compare match timer (timer/counter ) direct memory access controller nand flash memory controller audio codec interface serial protocol interface user debugging interface interrupt control register 0, 1 interrupt priority level setting register interrupt priority register 0 to 7 gpio interrupt set register mmcif: pcic: rtc: scif: siof: sr.imask: ssi: tmu: userimask. uimask: wdt: multimedia card interface pci controller realtime clock serial communication interface with fifo serial i/o with fifo status register. imask bit serial sound interface timer unit user interrupt mask level register. uimask bit watch dog timer figure 10.1 block diagram of intc
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 245 of 1286 rej09b0158-0100 10.1.1 interrupt method the basic flow of exception handling for interrupts is as follows. in interrupt exception handling, the contents of the program counter (pc), status register (sr), and r15 are saved in the saved program counter (spc), saved status register (ssr), and saved general register15 (sgr), and the cpu star ts execution of the interrupt exception handling routine at the corresponding vector address. an interrupt exception handling routine is a program written by the user to handle a specific exception. the interrupt exception handling routine is terminated and control returned to the original program by ex ecuting a return-from-exception instruction (rte). this instruction restores the contents of pc and sr and returns control to the normal processing routine at the point at which th e exception occurred. the contents of sgr are not written back to r15 by the rte instruction. 1. the contents of the pc, sr and r15 ar e saved in spc, ssr and sgr, respectively. 2. the block (bl) bit in sr is set to 1. 3. the mode (md) bit in sr is set to 1. 4. the register bank (rb) bit in sr is set to 1. 5. in a reset, the fpu disable (f d) bit in sr is cleared to 0. 6. the exception code is written to bits 13 to 0 of the interrupt event register (intevt). 7. processing is made to jump to the start ad dress of the interrupt exception handling routine, vector base register (vbr) + h'600. 8. the flow of processing branches to the address corresponding to the interrupt within the exception handler and processing to handle the interrupt starts up.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 246 of 1286 rej09b0158-0100 10.1.2 interrupt types in intc table 10.1 shows an example of the interrupt types. the intc supports both external interrupts and on-chip module interrupts. external interrupts refer to the interrupts input through the external nmi, irl, and irq pins. the irq and irl interrupts are assigned to the same pins in the sh7780. the pin functions are selected to suit the system configuration. ether level-sense, or the rising or falling edge, can be selected for the detection of irq input. table 10.1 interrupt types source number of sources (max.) priority intevt remarks nmi 1 ? h'1c0 irl[7:4] pin = h'0 external interrupts irl interrupt * 1 2 h'200 irl[3:0] pin = h'0 high irl[7:4] pin = h'1 h'220 irl[3:0] pin = h'1 irl[7:4] pin = h'2 h'240 irl[3:0] pin = h'2 irl[7:4] pin = h'3 h'260 irl[3:0] pin = h'3 irl[7:4] pin = h'4 inverse of values on the input pins (because the signals are active low) for example irl[7:4] pin = h'0 means the external pin input levels are: irl[7] pin = low irl[6] pin = low irl[5] pin = low irl[4] pin = low so the priority level is 15 (h'f) (see table 10.11) h'280 irl[3:0] pin = h'4 irl[7:4] pin = h'5 h'2a0 irl[3:0] pin = h'5 irl[7:4] pin = h'6 h'2c0 irl[3:0] pin = h'6 irl[7:4] pin = h'7 h'2e0 irl[3:0] pin = h'7 irl[7:4] pin = h'8 h'300 irl[3:0] pin = h'8 low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 247 of 1286 rej09b0158-0100 source number of sources (max.) priority intevt remarks h'320 irl[7:4] pin = h'9 irl[3:0] pin = h'9 irl[7:4] pin = h'a external interrupts irl interrupt * 1 2 h'340 irl[3:0] pin = h'a high irl[7:4] pin = h'b h'360 irl[3:0] pin = h'b irl[7:4] pin = h'c h'380 irl[3:0] pin = h'c irl[7:4] pin = h'd h'3a0 irl[3:0] pin = h'd irl[7:4] pin = h'e inverse of values on the input pins (because the signals are active low) for example irl[7:4] pin = h'0 means the external pin input levels are irl[7] pin = low irl[6] pin = low irl[5] pin = low irl[4] pin = low so the priority level is 15 (h'f) (see table 10.11) h'3c0 irl[3:0] pin = h'e low 8 values set in intpri h'240 irq[0] high irq interrupt h'280 irq[1] h'2c0 irq[2] h'300 irq[3] h'340 irq[4] h'380 irq[5] h'3c0 irq[6] h'200 irq[7] low rtc 3 h'480 ati values set in int2pri0 to int2pri7 h'4a0 pri h'4c0 cui wdt 1 h'560 iti * 2 on-chip module interrupts tmu-ch0 1 h'580 tuni0 * 2 tmu-ch1 1 h'5a0 tuni1 * 2 tmu-ch2 2 h'5c0 tuni2 * 2 h'5e0 ticpi2 * 2 h-udi 1 h'600 h-udii
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 248 of 1286 rej09b0158-0100 source number of sources (max.) priority intevt remarks dmac(0) 7(5/7) h'640 dmint0 * 2 h'660 dmint1 * 2 on-chip module interrupts values set in int2pri0 to int2pri7 h'680 dmint2 * 2 h'6a0 dmint3 * 2 h'6c0 dmae * 2 scif-ch0 4 h'700 eri0 * 2 h'720 rxi0 * 2 h'740 bri0 * 2 h'760 txi0 * 2 dmac(0) 7(2/7) h'780 dmint4 * 2 h'7a0 dmint5 * 2 dmac(1) 6(2/6) h'7c0 dmint6 * 2 h'7e0 dmint7 * 2 cmt 1 h'900 cmti hac 1 h'980 haci pcic(0) 1 h'a00 pciserr pcic(1) 1 h'a20 pciinta pcic(2) 1 h'a40 pciintb pcic(3) 1 h'a60 pciintc pcic(4) 1 h'a80 pciintd pcic(5) 5 h'aa0 pcierr h'ac0 pcipwd3 h'ae0 pcipwd2 h'b00 pcipwd1 h'b20 pcipwd0 scif-ch1 4 h'b80 eri1 * 2 h'ba0 rxi1 * 2 h'bc0 bri1 * 2 h'be0 txi1 * 2 siof 1 h'c00 siofi hspi 1 h'c80 spii
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 249 of 1286 rej09b0158-0100 source number of sources (max.) priority intevt remarks mmcif 4 h'd00 fstat h'd20 tran values set in int2pri0 to int2pri7 h'd40 err on-chip module interrupts h'd60 frdy dmac(1) 6 (4/6) h'd80 dmint8 * 2 h'da0 dmint9 * 2 h'dc0 dmint10 * 2 h'de0 dmint11 * 2 tmu-ch3 1 h'e00 tuni3 * 2 tmu-ch4 1 h'e20 tuni4 * 2 tmu-ch5 1 h'e40 tuni5 * 2 ssi 1 h'e80 ssii flctl 4 h'f00 flste * 2 h'f20 fltend * 2 h'f40 fltrq0 * 2 h'f60 fltrq1 * 2 gpio 4 h'f80 gpioi0 (port e0 to e2) h'fa0 gpioi1 (port e3 to e5) h'fc0 gpioi2 (port h0, 1, port j0, port k4) h'fe0 gpioi3 (port e6, port k5) notes: 1. irl[7:4] and irl[3:0] interrupts produce the same intevt codes. when using level- encoded interrupt requests, note that there is no flag to distinguish between interrupt requests on the irl[7:4] and irl[3:0] pins. 2. iti: interval timer interrupt tuni0 to tuni5: tmu chann el 0 to 5 under flow interrupt ticpi2: tmu channel 2 input capture interrupt dmint0 to dmint11: dmac channel 0 to 11 transfer end or half-end interrupt dmae: dmac address error interrupt (channel 0 to 11) eri0, eri1: scif channel 0, 1 receive error interrupt rxi0, rxi1: scif channel 0, 1 receive data full interrupt bri0, bri1: scif channel 0, 1 break interrupt txi0, txi1: scif channel 0, 1 transmission data empty interrupt flste: flctl error interrupt fltend: flctl error interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 250 of 1286 rej09b0158-0100 fltrq0: flctl data fifo transfer request interrupt fltrq1: flctl control code fifo transfer request interrupt 10.2 input/output pins table 10.2 shows the pin configuration. table 10.2 intc pin configuration pin name function i/o description nmi nonmaskable interrupt input pin input nonmaskable interrupt request signal input irq/irl3 to irq/irl0 input interrupt request signal input irl [3:0] 4-bit level-encoded interrupt input when icr0.irlm0 = 0; irq3 to irq0 individual pin interrupt input when icr0.irlm0 = 1 irq/ irl7 to irq/ irl4 * 1 external interrupt input pin input interrupt request signal input irl [7:4] 4-bit level-encoded interrupt input when icr0.irlm1 = 0; irq7 to irq4 individual pin interrupt input when icr0.irlm1 = 1 irqout * 2 interrupt request output output i ndicates that an interrupt request has been generated this pin is asserted even if the cpu does not accept the interrupt request, except if the interrupt is masked, when it is not asserted at all. notes: 1. these pins are multiplexed with the flctl, mode control, and gpio pins. 2. this pin is multiplexed with the dmac, h-udi and gpio pin.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 251 of 1286 rej09b0158-0100 10.3 register descriptions table 10.3 shows the intc register configuration. table 10.4 shows the register states in each operating mode. table 10.3 intc register configuration name abbreviation r/w p4 address area 7 address access size sync. clock interrupt control register 0 icr0 r/w h'ffd0 0000 h'1fd0 0000 32 pck interrupt control register 1 icr1 r/w h'ffd0 001c h'1fd0 001c 32 pck interrupt priority register intpri r/w h'ffd0 0010 h'1fd0 0010 32 pck interrupt source register intreq r/(w) h'ffd0 0024 h'1fd0 0024 32 pck interrupt mask register 0 intmsk0 r/w h'ffd0 0044 h'1fd0 0044 32 pck interrupt mask register 1 intmsk1 r/w h'ffd0 0048 h'1fd0 0048 32 pck interrupt mask register 2 intmsk2 r/w h'ffd4 0080 h'1fd4 0080 32 pck interrupt mask clear register 0 intmskclr0 r/w h'ffd0 0064 h'1fd0 0064 32 pck interrupt mask clear register 1 intmskclr1 r/w h'ffd0 0068 h'1fd0 0068 32 pck interrupt mask clear register 2 intmskclr2 r/w h'ffd4 0084 h'1fd4 0084 32 pck nmi flag control register nmifcr r/(w ) h'ffd0 00c0 h'1fd0 00c0 32 pck user interrupt mask level register userimask r/w h'ffd3 0000 h'1fd3 0000 32 pck int2pri0 r/w h'ffd4 0000 h'1fd4 0000 32 pck int2pri1 r/w h'ffd4 0004 h'1fd4 0004 32 pck on-chip module interrupt priority registers int2pri2 r/w h'ffd4 0008 h'1fd4 0008 32 pck int2pri3 r/w h'ffd4 000c h'1fd4 000c 32 pck int2pri4 r/w h'ffd4 0010 h'1fd4 0010 32 pck int2pri5 r/w h'ffd4 0014 h'1fd4 0014 32 pck int2pri6 r/w h'ffd4 0018 h'1fd4 0018 32 pck int2pri7 r/w h'ffd4 001c h'1fd4 001c 32 pck interrupt source register (not affected by the mask state) int2a0 r h'ffd4 0030 h'1fd4 0030 32 pck
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 252 of 1286 rej09b0158-0100 name abbreviation r/w p4 address area 7 address access size sync. clock interrupt source register (affected by the mask state) int2a1 r h'ffd4 0034 h'1fd4 0034 32 pck interrupt mask register int2mskr r/w h'ffd4 0038 h'1fd4 0038 32 pck interrupt mask clear register int2mskcr r/w h'ffd4 003c h'1fd4 003c 32 pck int2b0 r h'ffd4 0040 h'1fd4 0040 32 pck int2b1 r h'ffd4 0044 h'1fd4 0044 32 pck on-chip module interrupt source registers int2b2 r h'ffd4 0048 h'1fd4 0048 32 pck int2b3 r h'ffd4 004c h'1fd4 004c 32 pck int2b4 r h'ffd4 0050 h'1fd4 0050 32 pck int2b5 r h'ffd4 0054 h'1fd4 0054 32 pck int2b6 r h'ffd4 0058 h'1fd4 0058 32 pck int2b7 r h'ffd4 005c h'1fd4 005c 32 pck gpio interrupt set register int2gpic r/w h'ffd4 0090 h'1fd4 0090 32 pck notes: pck is the peripheral clock. (w) : to clear the flag, 0 can only be written to the corresponding bit.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 253 of 1286 rej09b0158-0100 table 10.4 register states in each operating mode name abbreviation power-on reset by preset pin/wdt/h-udi manual reset by wdt/multiple exception sleep by sleep instruction interrupt control register 0 icr0 h'x000 0000 * h'x000 0000 * retained interrupt control register 1 icr1 h'0000 0000 h'0000 0000 retained interrupt priority register intpri h'0000 0000 h'0000 0000 retained interrupt source register intreq h'0000 0000 h'0000 0000 retained interrupt mask register 0 intmsk0 h'ff00 0000 h'ff00 0000 retained interrupt mask register 1 intmsk1 h'ff00 0000 h'ff00 0000 retained interrupt mask register 2 intmsk2 h'0000 0000 h'0000 0000 retained interrupt mask clear register 0 intmskclr0 h'0000 0000 h'0000 0000 retained interrupt mask clear register 1 intmskclr1 h'0000 0000 h'0000 0000 retained interrupt mask clear register 2 intmskclr2 h'0000 0000 h'0000 0000 retained nmi flag control register nmifcr h'x000 0000 * h'x000 0000 * retained user interrupt mask level register userimask h'0000 0000 h'0000 0000 retained int2pri0 h'0000 0000 h'0000 0000 retained on-chip module interrupt priority registers int2pri1 h'0000 0000 h'0000 0000 retained int2pri2 h'0000 0000 h'0000 0000 retained int2pri3 h'0000 0000 h'0000 0000 retained int2pri4 h'0000 0000 h'0000 0000 retained int2pri5 h'0000 0000 h'0000 0000 retained int2pri6 h'0000 0000 h'0000 0000 retained int2pri7 h'0000 0000 h'0000 0000 retained interrupt source register (not affected by the mask state) int2a0 h'xxxx xxxx h'xxxx xxxx retained interrupt source register (affected by the mask state) int2a1 h'0000 0000 h'0000 0000 retained interrupt mask register int2mskr h'ffff ffff h'ffff ffff retained interrupt mask clear register int2mskcr h'0000 0000 h'0000 0000 retained
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 254 of 1286 rej09b0158-0100 name abbreviation power-on reset by preset pin/wdt/h-udi manual reset by wdt/multiple exception sleep by sleep instruction int2b0 h'xxxx xxxx h'xxxx xxxx retained int2b1 h'xxxx xxxx h'xxxx xxxx retained on-chip module interrupt source registers int2b2 h'xxxx xxxx h'xxxx xxxx retained int2b3 h'xxxx xxxx h'xxxx xxxx retained int2b4 h'xxxx xxxx h'xxxx xxxx retained int2b5 h'xxxx xxxx h'xxxx xxxx retained int2b6 h'xxxx xxxx h'xxxx xxxx retained int2b7 h'xxxx xxxx h'xxxx xxxx retained gpio interrupt set register int2gpic h'0000 0000 h'0000 0000 retained [legend] x: undefined note: the initial values of icr0.nmil and nmifcr. nmil depend on the level input to the nmi pin.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 255 of 1286 rej09b0158-0100 10.3.1 interrupt cont rol register 0 (icr0) icr0 is a 32-bit readable and par tially writable register that sets the input signal detection mode for the external interrupt input pins (irq/irl [7:0]) and nmi pin, and indicates the level being input on the nmi pin. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?0 ? ? ? ? ? ? irlm1 irlm0 nmie nmib ? ? ? ? nmil mai r r r r r r r/w r/w r/w r/w r r r r r r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 nmil undefined r nmi input level indicates the signal level being input on the nmi pin. reading this bit allows the user to know the nmi pin level, and writing is invalid. 0: low level is being input on the nmi pin 1: high level is being input on the nmi pin note: the initial value of this bit depends on the level initially being input on the nmi pin. 30 mai 0 r/w mai (mask all interrupts) interrupt mask specifies whether all interrupts are masked while the nmi pin is at the low level regardless of the setting of the bl bit in sr of the cpu. 0: interrupts remain enabled even when the nmi pin goes low 1: interrupts are disabled when the nmi pin goes low 29 to 26 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 256 of 1286 rej09b0158-0100 bit name initial value r/w description 25 nmib 0 r/w nmi block mode selects whether an nmi interrupt is held until the bl bit in sr is cleared to 0 or detected immediately when the bl bit in sr of the cpu is set to 1. 0: an nmi interrupt is held wh en the bl bit in sr is set to 1 (initial value) 1: an nmi interrupt is not held when the bl bit in sr is set to 1 note: if interrupts are accepted with the bl bit in sr set to 1, information saved for any previous exception (ssr, spc, sgr, and intevt) is lost. 24 nmie 0 r/w nmi edge select selects whether an interrupt request signal to the nmi pin is detected at the risi ng edge or the falling edge. 0: an interrupt request is detected at the falling edge of nmi input (initial value) 1: an interrupt request is det ected at the rising edge of nmi input note: nmi interrupt is not detected for at least six bus clock cycles after modification of this bit. 23 irlm0 0 r/w irl pin mode 0 selects whether irq/ irl3 to irq/ irl0 are used as 4- bit level-encoded interrupt requests or as four independent interrupts. 0: irq/ irl3 to irq/ irl0 are used as the 4-bit level- encoded interrupt requests (irl [3:0] interrupt; initial value) 1: irq/ irl3 to irq/ irl0 are used as four independent interrupt requests (irq [n] interrupt; n = 3 to 0) note: the level-encoded irl interrupt is not detected unless the same pin levels are sampled in four consecutive bus clock cycles.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 257 of 1286 rej09b0158-0100 bit name initial value r/w description 22 irlm1 0 r/w irl pin mode 1 selects whether irq/ irl7 to irq/ irl4 are used as 4- bit level-encoded interrupt requests or as four independent interrupts. 0: irq/ irl7 to irq/ irl4 are used as the 4-bit level- encoded interrupt requests (irl [7:4] interrupt; initial value) 1: irq/ irl7 to irq/ irl4 are used as four independent interrupt requests (irq [n] interrupt; n = 7 to 4) note: the level-encoded irl interrupt is not detected unless the same pin levels are sampled in four consecutive bus clock cycles. 21 lsh 0 r/w irq/ irl level-sense with holding function selects whether or not to use the holding function for level-encoded irl and level-sense irq interrupts. 0: irq level-sense and irl interrupt requests are held (initial value) 1: irq level-sense and irl interrupt requests are not held (compatible with current sh-4 behavior for irq in level-sense mode and irl level-encoded interrupts) note: this setting is only valid for irq/ irl pins used as a 4-bit level-encoded irl interrupt or as level- sense irq interrupts. when using this function, also refer to sections 10.4.2 irq interrupts, 10. 4.3 irl interrupts, and 10.7. usage notes. 20 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 258 of 1286 rej09b0158-0100 10.3.2 interrupt cont rol register 1 (icr1) icr1 is a 32-bit readable/writable register that specifies the individual input signal detection modes of external interrupt input pins irq/ irl7 to irq/ irl0. these settings are only valid for pins configured as individual irq interrupts; that is, for pins for which the irlm0 or irlm1 bit in icr0 is set to 1. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 irq7s irq6s irq5s irq4s irq3s irq2s irq0s irq1s r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31, 30 irq0s 00 r/w 29, 28 irq1s 00 r/w 27, 26 irq2s 00 r/w 25, 24 irq3s 00 r/w 23, 22 irq4s 00 r/w 21, 20 irq5s 00 r/w 19, 18 irq6s 00 r/w 17, 16 irq7s 00 r/w irqn sense select (n = 0 to 7) selects whether the corresponding individual pin interrupt signal on the irq/irl7 to irq/irl0 pins is detected on rising or falling edges, or at the high or low level. 00: the interrupt request is detected on falling edges of the irqn input. 01: the interrupt request is detected on rising edges of the irqn input. 10: the interrupt request is detected when the irqn input is at the low level. 11: the interrupt request is detected when the irqn input is at the low level. note: when either level is selected, the irq level interrupt request is not detected unless the same level is sampled in three consecutive bus- clock cycles. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 259 of 1286 rej09b0158-0100 note: when an irq pin is set for level input (irqns 1 = 1), the interrupt source is held until the cpu accepts the interrupt (this is also true for other interrupts). therefore, even if an interrupt source is disabled before this lsi returns fr om sleep mode, branching of processing to the interrupt handler when this lsi returns from sleep mode is guaranteed. a held interrupt can be cleared by setting the corresponding interrupt mask bit (the im bit in the interrupt mask register) to 1. 10.3.3 interrupt priori ty register (intpri) intpri is a 32-bit readable/writable register used to set the priorities of irq[7:0] (as levels from 15 to 0). these settings are only valid for irq/ irl7 to irq/ irl4 or irq/ irl3 to irq/ irl0 when set up as individual irq interrupts by setting the irlm0 or irlm1 bit in icr0 to 1. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ip3 ip2 ip1 ip0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ip7 ip6 ip5 ip4 bit: initial value: r/w: bit name initial value r/w description 31 to 28 ip0 h'0 r/w set the priority of ir q0 as an individual pin interrupt request. 27 to 24 ip1 h'0 r/w set the priority of ir q1 as an individual pin interrupt request. 23 to 20 ip2 h'0 r/w set the priority of ir q2 as an individual pin interrupt request. 19 to 16 ip3 h'0 r/w set the priority of ir q3 as an individual pin interrupt request. 15 to 12 ip4 h'0 r/w set the priority of ir q4 as an individual pin interrupt request. 11 to 8 ip5 h'0 r/w set the priority of ir q5 as an individual pin interrupt request. 7 to 4 ip6 h'0 r/w set the priority of ir q6 as an individual pin interrupt request. 3 to 0 ip7 h'0 r/w set the priority of ir q7 as an individual pin interrupt request. interrupt priorities should be established by setting values from h'f to h'1 in each of the 4-bit fields. a larger value corresponds to a higher prio rity. when the value h'0 is set in a field, the corresponding interrupt is masked (initial value).
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 260 of 1286 rej09b0158-0100 10.3.4 interrupt sou rce register (intreq) intreq is a 32-bit readable and conditionally writable register that indicates which of the irq [n] (n = 0 to 7) interrupts is currently asserting a request for the intc. even if an interrupt is masked by the setti ng in intpri or intmsk0, operation of the corresponding intreq bit is not affected. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ir7 ir6 ir5 ir4 ir3 ir2 ir0 ir1 r r r r r r r r r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: description bit name initial value r/w in edge detection (irqns = 00 or 01, n = 0 to 7) in level detection (irqns = 10 or 11, n = 0 to 7) 31 ir0 0 r/(w) 30 ir1 0 r/(w) 29 ir2 0 r/(w) 28 ir3 0 r/(w) 27 ir4 0 r/(w) 26 ir5 0 r/(w) 25 ir6 0 r/(w) 24 ir7 0 r/(w) [when reading] 0: the corresponding irq interrupt request has not been detected. 1: the corresponding irq interrupt request has been detected. [when writing] * 0: each bit is cleared by writing a 0 after having read a 1 from it. 1: sets holding of the detected interrupt request note: write 1 to the bit if it should not be cleared yet. [when reading] 0: the corresponding irq interrupt pin is not asserted. 1: the corresponding irq interrupt pin is asserted, but the cpu has not accepted the interrupt yet. values written have no effect. 23 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 261 of 1286 rej09b0158-0100 10.3.5 interrupt mask regist ers (intmsk0 to intmsk2) intmsk0 to intmsk2 are 32-bit readable and cond itionally writable registers that control mask settings for the interrupt requests. to clear a mask setting for interrupts, write 1 to the corresponding bit in intmskclr0 to intmskclr2. writing 0 to a bit in intmsk0 to intmsk2 has no effect. ? interrupt mask register 0 (intmsk0) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 1 1 1 11 ? ? ? ? ? ? ? ? im07 im06 im05 im04 im03 im02 im00 im01 r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 im00 1 r/w sets masking of individual pin interrupt request on irq0. 30 im01 1 r/w sets masking of individual pin interrupt request on irq1. 29 im02 1 r/w sets masking of individual pin interrupt request on irq2. 28 im03 1 r/w sets masking of individual pin interrupt request on irq3. 27 im04 1 r/w sets masking of individual pin interrupt request on irq4. 26 im05 1 r/w sets masking of individual pin interrupt request on irq5. 25 im06 1 r/w sets masking of individual pin interrupt request on irq6. 24 im07 1 r/w sets masking of individual pin interrupt request on irq7. [when reading] 0: no masking 1: masking [when writing] 0: no effect 1: masks the interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 262 of 1286 rej09b0158-0100 bit name initial value r/w description 23 to 0 all 0 r reserved these bits are always read as 0. the write value should always be 0. note: when the 4-bit encoded interrupt inputs are to be used, write b'1111 to the im [03:00] or im [07:04] bits to mask single-pi n interrupts in the ranges irq/irl [3:0] or irq/irl [7:4], respectively. ? interrupt mask register 1 (intmsk1) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 1 1 1 11 ? ? ? ? ? ? ? ? ? ? ? ? ? ? im10 im11 r r r r r r r r r r r r r r r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 im10 1 r/w mask setting for all irl3 to irl0 interrupt requests when pins irq/ irl3 to irq/ irl0 operate as a level-encoded interrupt input. 30 im11 1 r/w mask setting for all irl7 to irl4 interrupt requests when pins irq/ irl7 to irq/ irl4 operate as a level-encoded interrupt input. [when reading] 0: the interrupts are accepted. 1: the interrupts are masked. [when writing] 0: no effect 1: masks the interrupts 29 to 24 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 23 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 263 of 1286 rej09b0158-0100 ? interrupt mask register 2 (intmsk2) intmsk2 settings are valid for particular irl interrupt codes generated by the pattern of input signals on pins irl7 to irl4 or irl3 to irl0 and when all irl interrupts from the corresponding set of pins are not masked by the setting in intmsk1. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? im001 im002 im003 im004 im005 im006 im007 im008 im009 im010 im011 im012 im013 im015 im014 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? im101 im102 im103 im104 im105 im106 im107 im108 im109 im110 im111 im112 im113 im115 im114 bit: initial value: r/w: bit name initial value r/w description 31 im015 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = llll (h'0). 30 im014 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = lllh (h'1). 29 im013 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = llhl (h'2). [when reading] 0: the interrupt is acceptable. 1: the interrupt is masked. [when writing] 0: no effect 1: masks the interrupt 28 im012 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = llhh (h'3). 27 im011 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = lhll (h'4). 26 im010 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = lhlh (h'5). 25 im009 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = lhhl (h'6). 24 im008 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = lhhh (h'7).
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 264 of 1286 rej09b0158-0100 bit name initial value r/w description 23 im007 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hlll (h'8). 22 im006 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hllh (h'9). 21 im005 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hlhl (h'a). [when reading] 0: the interrupt is acceptable. 1: the interrupt is masked. [when writing] 0: no effect 1: masks the interrupt initial value: 0 20 im004 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hlhh (h'b). 19 im003 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hhll (h'c). 18 im002 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hhlh (h'd). 17 im001 0 r/w sets masking of interrupt- request generation by irl3 to irl0 = hhhl (h'e). 16 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 15 im115 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = llll (h'0). 14 im114 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = lllh (h'1). 13 im113 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = llhl (h'2). [when reading] 0: the interrupt is acceptable. 1: the interrupt is masked. [when writing] 0: no effect 1: masks the interrupt initial value: 0 12 im112 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = llhh (h'3).
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 265 of 1286 rej09b0158-0100 bit name initial value r/w description 11 im111 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = lhll (h'4). 10 im110 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = lhlh (h'5). 9 im109 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = lhhl (h'6). 8 im108 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = lhhh (h'7). [when reading] 0: the interrupt is acceptable. 1: the interrupt is masked. [when wswriting] 0: no effect 1: masks the interrupt initial value: 0 7 im107 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hlll (h'8). 6 im106 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hllh (h'9). 5 im105 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hlhl (h'a). 4 im104 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hlhh (h'b). 3 im103 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hhll (h'c). 2 im102 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hhlh (h'd). 1 im101 0 r/w sets masking of interrupt- request generation by irl7 to irl4 = hhhl (h'e). 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. note: ?h? and ?l? indicate high- and low-level input on the corresponding irq/ irl pin. for the relationship between the input signal level and the priority level, refer to table 10.11.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 266 of 1286 rej09b0158-0100 10.3.6 interrupt mask clear regi sters (intmskclr0 to intmskclr2) intmskclr0 to intmskclr2 are 32-bit write-only registers that clear the mask settings for each interrupt request. values read are undefined. ? interrupt mask clear re gister 0 (intmskclr0) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ic07 ic06 ic05 ic04 ic03 ic02 ic00 ic01 r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 ic00 0 r/w clears masking of irq0 as an individual pin interrupt request. 30 ic01 0 r/w clears masking of irq1 as an individual pin interrupt request. 29 ic02 0 r/w clears masking of irq2 as an individual pin interrupt request. 28 ic03 0 r/w clears masking of irq3 as an individual pin interrupt request. 27 ic04 0 r/w clears masking of irq4 as an individual pin interrupt request. 26 ic05 0 r/w clears masking of irq5 as an individual pin interrupt request. 25 ic06 0 r/w clears masking of irq6 as an individual pin interrupt request. 24 ic07 0 r/w clears masking of irq7 as an individual pin interrupt request. [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupt) 23 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 267 of 1286 rej09b0158-0100 ? interrupt mask clear re gister 1 (intmskclr1) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ic10 ic11 r r r r r r r r r r r r r r r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 ic10 0 r/w clears masking of irl3 to irl0 interrupt requests when irq/ irl3 to irq/ irl0 operate as a level-encoded interrupt input. 30 ic11 0 r/w clears masking of irl7 to irl4 interrupt requests when irq/ irl7 to irq/ irl4 operate as a level-encoded interrupt input. [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupts) 29 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 268 of 1286 rej09b0158-0100 ? interrupt mask clear re gister 2 (intmskclr2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ic001 ic002 ic003 ic004 ic005 ic006 ic007 ic008 ic009 ic010 ic011 ic012 ic013 ic015 ic014 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ic101 ic102 ic103 ic104 ic105 ic106 ic107 ic108 ic109 ic110 ic111 ic112 ic113 ic115 ic114 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit name initial value r/w description 31 ic015 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = llll (h'0). 30 ic014 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = lllh (h'1). 29 ic013 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = llhl (h'2). [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupt) 28 ic012 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = llhh (h'3). 27 ic011 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = lhll (h'4). 26 ic010 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = lhlh (h'5). 25 ic009 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = lhhl (h'6). 24 ic008 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = lhhh (h'7). 23 ic007 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hlll (h'8).
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 269 of 1286 rej09b0158-0100 bit name initial value r/w description 22 ic006 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hllh (h'9). 21 ic005 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hlhl (h'a). 20 ic004 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hlhh (h'b). 19 ic003 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hhll (h'c). [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupt) 18 ic002 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hhlh (h'd). 17 ic001 0 r/w clears masking of interrupt- request generation by irl3 to irl0 = hhhl (h'e). 16 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 15 ic115 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = llll (h'0). 14 ic114 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = lllh (h'1). 13 ic113 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = llhl (h'2). 12 ic112 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = llhh (h'3). [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupt) 11 ic111 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = lhll (h'4).
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 270 of 1286 rej09b0158-0100 bit name initial value r/w description 10 ic110 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = lhlh (h'5). 9 ic109 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = lhhl (h'6). 8 ic108 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = lhhh (h'7). 7 ic107 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hlll (h'8). [when reading] values read are undefined. [when writing] 0: no effect 1: clears the corresponding interrupt mask (enables the interrupt) 6 ic106 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hllh (h'9). 5 ic105 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hlhl (h'a). 4 ic104 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hlhh (h'b). 3 ic103 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hhll (h'c). 2 ic102 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hhlh (h'd). 1 ic101 0 r/w clears masking of interrupt- request generation by irl7 to irl4 = hhhl (h'e). 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. note: ?h? and ?l? indicate high- and low-level input on the corresponding irq/ irl pin. for the relationship between the input signal level and the priority level, refer to table 10.11.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 271 of 1286 rej09b0158-0100 10.3.7 nmi flag contro l register (nmifcr) nmifcr is a 32-bit readable and conditionally writabl e register that has an nmi flag (nmifl bit) which can be read or cleared by software. the nm ifl bit is automatically set to 1 by hardware when an nmi interrupt is detected by the intc. writing 0 to the nmifl bit clears it. the value of the nmifl bit does not affect acceptance of the nmi by the cpu. although an nmi request detected by the intc is cleared when the cpu accepts the nmi, the nmifl bit is not cleared automatically. even if 0 is written to the nmifl bit before the nmi request is accepted by the cpu, the nmi request is not canceled. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?0 nmifl ? ? ? ? ? ? ? ? ? ? ? ? ? nmil ? r/(w) r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit name initial value r/w description 31 nmil undefined r nmi input level indicates the level of the si gnal input to the nmi pin; that is, this bit is read to determine the level on the nmi pin. this bit cannot be modified. 0: the low level is being input to the nmi pin 1: the high level is being input to the nmi pin 30 to 17 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 272 of 1286 rej09b0158-0100 bit name initial value r/w description 16 nmifl 0 r/(w) nmi interrupt request signal detection indicates whether an nmi interrupt request signal has been detected. this bit is automatically set to 1 when the intc detects an nmi interrupt request. write 0 to clear the bit. writing 1 to this bit has no effect. [when reading] 1: nmi has been detected 0: nmi has not been detected [when writing] 0: clears the nmi flag 1: no effect 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 273 of 1286 rej09b0158-0100 10.3.8 user interrupt mask level register (userimask) userimask is a 32-bit readable and conditionally writable register that sets the acceptable interrupt level. when addresses in area 7 are accessed by using the mmu?s address translation function, userimask can be acce ssed in user mode. since only userimask is allocated to the 64-kbyte page (other intc regi sters are allocated to a different area), it can be set to be accessible in user mode. interrupts with priority levels lower than the level set in the uimask bits are masked. when the value h'f is set in the uimask bit, all interrupts other than the nmi are masked. interrupts with priority levels hi gher than the level set in the ui mask bits are accepted under the following conditions. ? the corresponding interrupt mask bit in the interrup t mask register is cleared to 0 (the interrupt is enabled). ? the priority level setting in the imask bits in also sr is lower than that of the interrupt. even if an interrupt is accepted, the uimask value does not change. userimask is initialized to h'0000 0000 (all interrupts are enabled) on return from a power-on reset or manual reset. to prevent incorrect writing, the value written to bits 31 to 24 must always be set to h'a5. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? wkey (h'a5) r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? uimask ? ? ? ? ? ? ?? r r r r r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w:
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 274 of 1286 rej09b0158-0100 bit name initial value r/w description 31 to 24 wkey h'00 r/w when writing a value to bits 7 to 4, always write h'a5 here. these bits are always read as 0. 23 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 4 uimask h'0 r/w interrupt mask level mask interrupts with priority levels lower than the level set in the uimask bits. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. procedure for using the user interrupt mask level register interrupts with priority levels less than or eq ual to the value set in userimask are disabled. this function can be used to disable less urgent interrupts during the execution of urgent tasks that run in user mode, e.g. device drivers, and thus reduce times until completion for such tasks. userimask is allocated to a different 64-kbyte page than that to which the other intc registers are allocated. when accessing this register in us er mode, translate the address through the mmu. in a system with a multitasking os, the memory-protection functions of the mmu must be used to control which processes have access to userimask. when terminating a task or switching to another task, be sure to clear userimask to 0 beforehand. if the uimask bits are erroneously left set at a value other than zero, interrupts which are not higher in priority than the uimask level remain disabled, and operation may be incorrect (for example, the os might be unable to switch between tasks). an example of the usage procedure is given below. 1. classify interrupts as a or b, described below, and set the priority of a-type interrupts higher than that of the b-priority interrupts. a. interrupts to be accepted by device drivers (i nterrupts for use by th e operating system: a timer interrupt etc.) b. interrupts to be disabled during the execution of device drivers 2. make the mmu settings so that the address space which contains userimask can only be accessed by the device driver for whic h interrupts should be disabled. 3. branch to the device driver.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 275 of 1286 rej09b0158-0100 4. set the uimask bits so that b-type interr upts are masked during execution of the device driver that is operating in user mode. 5. process interrupts with a high priority in the device driver. 6. clear the uimask bits to 0 to return from processing in the device driver.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 276 of 1286 rej09b0158-0100 10.3.9 on-chip module interrupt priority registers (int2pri0 to int2pri7) int2pri0 to int2pri7 are 32-bit readable/writable registers used to set priorities (levels 31 to 0) for the on-chip module interrupts. int2pri0 to int2pri7 are initialized to h'0000 0000 by a reset. int2pri0 to int2pri7 contain five-bit fields that are used to set up to 30 priority levels for the individual interrupt sources (interrupt requests are masked by settings of h'00 and h'01). 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ?? r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ?? r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w r rr bit: initial value: r/w: table 10.5 shows the correspondence between interrupt request sources and bits in int2pri0 to int2pri7. table 10.5 interrupt request sou rces and int2pri0 to int2pri7 bits register 28 to 24 20 to 16 12 to 8 4 to 0 int2pri0 tmu channel 0 tmu channel 1 tmu channel 2 tmu channel 2 input capture int2pri1 tmu channel 3 tmu channel 4 tmu channel 5 rtc int2pri2 scif channel 0 scif channel 1 wdt reserved int2pri3 h-udi dmac channels 0 to 5 dmac channels 6 to 11 reserved int2pri4 cmt hac pcic (0) pcic (1) int2pri5 pcic (2) pcic (3) pcic (4) pcic (5) int2pri6 siof hspi mmcif ssi int2pri7 flctl gpio reserved reserved note: a larger value corresponds to a higher priority. the interrupt request is masked when the bits are set to h'00 or h'01. for details, see the description above.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 277 of 1286 rej09b0158-0100 10.3.10 interrupt source re gister (int2a0: not affe cted by mask states) int2a0 is a 32-bit read-only register that indicat es interrupt states of interrupt source modules regardless of the corresponding ma sk states. even if interrupt masking is set in the interrupt mask register, corresponding bits in int2a0 indicate source modules for which interrupt conditions have been satisfied (the corresponding interrupt is not generated). when sources that are masked should not be indicated, use int2a1. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? 0 0 0 0 00 ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? 0 ? ? ? 0 0 ? ? ?? ? ? ? r r r r r r r r r r r r r r rr bit: initial value: r/w: table 10.6 shows the correspondence between bits in int2a0 and sources. table 10.6 correspondence between bits in int2a0 and sources bit initial value r/w source function description 31 to 26 all 0 r (reserved) these bits are always read as 0. the write value should always be 0. 25 ? r gpio indicates gpio interrupt source 24 ? r flctl indicates flctl interrupt source 23 ? r ssi indicates ssi interrupt source 22 ? r mmcif indicates mmc interrupt source 21 ? r hspi indicates hspi interrupt source 20 ? r siof indicates siof interrupt source indicates interrupt sources for the individual peripheral modules (int2a0 is not affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 278 of 1286 rej09b0158-0100 bit initial value r/w source function description 19 ? r pcic (5) indicates pcierr and pcipwd3 to pcipwd0 interrupt sources 18 ? r pcic (4) indicates pciintd interrupt source 17 ? r pcic (3) indicates pciintc interrupt source 16 ? r pcic (2) indicates pciintb interrupt source 15 0 r pcic (1) indicates pciinta interrupt source 14 ? r pcic (0) indicates pciserr interrupt source 13 ? r hac indicates hac interrupt source 12 ? r cmt indicates cmt interrupt source 11, 10 all 0 r (reserved) these bits are always read as 0. the write value should always be 0. 9 ? r dmac (1) indicates interrupt sources of dmac channels 6 to 11 8 ? r dmac (0) indicates interrupt sources of dmac channels 0 to 5 and address error interrupt 7 ? r h-udi indicates h-udi interrupt source 6 0 r (reserved) this bit is always read as 0. the write value should always be 0. 5 ? r wdt indicates wdt interrupt source 4 ? r scif channel 1 indicates the scif channel 1 interrupt source 3 ? r scif channel 0 indicates the scif channel 0 interrupt source indicates interrupt sources for the individual peripheral modules (int2a0 is not affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 279 of 1286 rej09b0158-0100 bit initial value r/w source function description 2 ? r rtc indicates rtc interrupt source 1 ? r tmu channels 3 to 5 indicates the tmu channel 3 to 5 interrupt sources 0 ? r tmu channels 0 to 2 indicates the tmu channel 0 to 2 interrupt sources indicates interrupt sources for the individual peripheral modules (int2a0 is not affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 280 of 1286 rej09b0158-0100 10.3.11 interrupt source register (int2a1: affect ed by mask states) int2a is a 32-bit read-only register that indicates interrupt states of interrupt source modules for which the interrupts are not masked. note that if an interrupt mask is set in the interrupt mask register, int2a1 does not indicat e the interrupt state of the sour ce module in the corresponding bit. to check whether interrupts have been generated, regardless of the state of the interrupt mask register, use int2a0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? r r r r r r r r r r r r r r rr bit: initial value: r/w: table 10.7 shows the correspondence between bits in int2a1 and sources. table 10.7 correspondence between bits in int2a1 and sources bit initial value r/w source function description 31 to 26 0 r (reserved) these bits are always read as 0. the write value should always be 0. 25 0 r gpio indicates gpio interrupt source 24 0 r flctl indicates flctl interrupt source 23 0 r ssi indicates ssi interrupt source 22 0 r mmcif indicates mmc interrupt source 21 0 r hspi indicates hspi interrupt source indicates interrupt sources for the individual peripheral modules (int2a1 is affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary. 20 0 r siof indicates siof interrupt source
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 281 of 1286 rej09b0158-0100 bit initial value r/w source function description 19 0 r pcic (5) indicates pcierr and pcipwd3 to pcipwd0 interrupt sources 18 0 r pcic (4) indicates pciintd interrupt source 17 0 r pcic (3) indicates pciintc interrupt source 16 0 r pcic (2) indicates pciintb interrupt source 15 0 r pcic (1) indicates pciinta interrupt source 14 0 r pcic (0) indicates pciserr interrupt source 13 0 r hac indicates hac interrupt source 12 0 r cmt indicates cmt interrupt source 11, 10 0 r (reserved) these bits are always read as 0. the write value should always be 0. 9 0 r dmac (1) indicates interrupt sources of dmac channels 6 to 11 indicates interrupt sources for the individual peripheral modules (int2a1 is affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary. 8 0 r dmac (0) indicates interrupt sources of dmac channels 0 to 5 and address error interrupt 7 0 r h-udi indicates h-udi interrupt source 6 0 r (reserved) 5 0 r wdt indicates the wdt interrupt source 4 0 r scif channel 1 indicates the scif channel 1 interrupt source 3 0 r scif channel 0 indicates the scif channel 0 interrupt source
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 282 of 1286 rej09b0158-0100 bit initial value r/w source function description 2 0 r rtc indicates the rtc interrupt source 1 0 r tmu channels 3 to 5 indicates the tmu channel 3 to 5 interrupt source 0 0 r tmu channels 0 to 2 indicates the tmu channel 0 to 2 interrupt source indicates interrupt sources for the individual peripheral modules (int2a1 is affected by the state of the interrupt mask register). 0: no interrupt 1: an interrupt has been generated note: interrupt sources can also be identified by directly reading the intevt code that is sent to the cpu. in this case, reading int2a0 is not necessary. 10.3.12 interrupt mask register (int2mskr) int2mskr is a 32-bit readable/w ritable register that sets in terrupt masking for each of the sources indicated in the in terrupt source register. the cpu is not notified of interrupts for which the corresponding bits in int2mskrg are set to 1. int2mskr is initialized to h'ff ff ffff (mask state) by a reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 ? ? ? r/w r/w r/w r/w r/w r/w r r/w r/w r/w r r r/w r/w r/w r/w bit: initial value: r/w: table 10.8 shows the correspondence between bits in int2mskr and interrupt masking.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 283 of 1286 rej09b0158-0100 table 10.8 correspondence between bits in int2mskr and interrupt masking bit initial value r/w target function description 31 to 26 all 1 r (reserved) these bits are always read as 1. the write value should always be 1. 25 1 r/w gpio masks the gpio interrupt 24 1 r/w flctl masks the flctl interrupt 23 1 r/w ssi masks the ssi interrupt 22 1 r/w mmcif masks the mmc interrupt 21 1 r/w hspi masks the hspi interrupt 20 1 r/w siof masks the siof interrupt 19 1 r/w pcic (5) masks pcierr and pcipwd3 to pcipwd0 interrupt 18 1 r/w pcic (4) masks the pciintd interrupt 17 1 r/w pcic (3) masks the pciintc interrupt 16 1 r/w pcic (2) masks the pciintb interrupt masks interrupts for individual modules. [when reading] 0: no masking 1: masking [when writing] 0: no effect 1: masks the interrupt 15 1 r/w pcic (1) masks the pciinta interrupt 14 1 r/w pcic (0) masks the pciserr interrupt 13 1 r/w hac masks the hac interrupt 12 1 r/w cmt masks the cmt interrupt 11, 10 all 1 r/w (reserved) these bits are always read as 1. the write value should always be 1. 9 1 r/w dmac (1) masks the interrupts of dmac channels 6 to 11 8 1 r/w dmac (0) masks the interrupts of dmac channels 0 to 5 and the address error interrupt 7 1 r/w h-udi masks the h-udi interrupt 6 1 r (reserved) this bit is always read as 0. the write value should always be 0. 5 1 r/w wdt masks the wdt interrupt 4 1 r/w scif channel 1 masks scif channel 1 interrupt 3 1 r/w scif channel 0 masks scif channel 0 interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 284 of 1286 rej09b0158-0100 bit initial value r/w target function description 2 1 r/w rtc masks the rtc interrupt 1 1 r/w tmu channels 3 to 5 masks tmu channels 3 to 5 interrupts 0 1 r/w tmu channels 0 to 2 masks tmu channels 0 to 2 interrupts masks interrupts for individual modules. [when reading] 0: no masking 1: masking [when writing] 0: no effect 1: masks the interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 285 of 1286 rej09b0158-0100 10.3.13 interrupt mask cl ear register (int2mskcr) int2mskcr is a 32-bit write-only register used to clear mask settings in the interrupt mask register. setting a bit in this register to 1 clears the masking of the corresponding interrupt source. the bits of this register are always read as 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? r/w r/w r/w r/w r/w r/w r r/w r/w r/w r r r/w r/w r/w r/w bit: initial value: r/w: table 10.9 shows the correspondence between bits in int2mskcr and interrupt mask clearing. table 10.9 correspondence be tween bits in int2mskcr an d interrupt mask clearing bit initial value r/w target function description 31 to 26 all 0 r (reserved) these bits are always read as 0. the write value should always be 0. 25 0 r/w gpio clears the gpio interrupt masking 24 0 r/w flctl clears the flctl interrupt masking 23 0 r/w ssi clears the ssi interrupt masking 22 0 r/w mmcif clears the mmc interrupt masking 21 0 r/w hspi clears the hspi interrupt masking 20 0 r/w siof clears the siof interrupt masking 19 0 r/w pcic (5) clears the pcierr and pcipwd3 to pcipwd0 interrupts masking clears interrupt masking for individual modules. [when reading] always 0 [when writing] 0: invalid 1: interrupt mask is cleared 18 0 r/w pcic (4) clears the pciintd interrupt masking 17 0 r/w pcic (3) clears the pciintc interrupt masking
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 286 of 1286 rej09b0158-0100 bit initial value r/w target function description 16 0 r/w pcic (2) clears the pciintb interrupt masking 15 0 r/w pcic (1) clears the pciinta interrupt masking 14 0 r/w pcic (0) clears the pciserr interrupt masking 13 0 r/w hac clears the hac interrupt masking 12 0 r/w cmt clears the cmt interrupt masking 11, 10 all 0 r/w (reserved) these bits are always read as 0. the write value should always be 0. 9 0 r/w dmac (1) clears the interrupt masking for dmac channels 6 to 11 8 0 r/w dmac (0) clears the interrupt masking for dmac channels 0 to 5 and address error interrupt clears interrupt masking for each peripheral module. [when reading] always 0 [when writing] 0: invalid 1: interrupt mask is cleared 7 0 r/w h-udi clears h-udi interrupt masking 6 0 r (reserved) this bit is always read as 0. the write value should always be 0. 5 0 r/w wdt clears the wdt interrupt masking 4 0 r/w scif channel 1 clears the scif channel 1 interrupt masking 3 0 r/w scif channel 0 clears the scif channel 0 interrupt masking 2 0 r/w rtc clears the rtc interrupt masking 1 0 r/w tmu channels 3 to 5 clears the tmu channel 3 to 5 interrupt masking 0 0 r/w tmu channels 0 to 2 clears the tmu channel 0 to 2 interrupt masking
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 287 of 1286 rej09b0158-0100 10.3.14 on-chip module interrupt so urce registers (int2b0 to int2b7) int2b0 to int2b7 are 32-bit read-only registers that indicate more details on sources within interrupt source modules for which the interrupt state is indicated in the interrupt source register. int2b0 to int2b7 are not affected by the state of masking in the interrupt mask register. bits for modules in the interrupt mask and interrupt enable registers enable and disa ble the operation of the corresponding detailed interrupt source bits. the initial values of these registers are undefin ed (reserved bits are always read as 0). 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: int2b0: indicates detailed interrupt sources for the tmu. module bit name detailed source description 31 to 7 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 6 tuni5 tmu channel 5 underflow interrupt 5 tuni4 tmu channel 4 underflow interrupt 4 tuni3 tmu channel 3 underflow interrupt 3 ticpi2 tmu channel 2 input capture interrupt 2 tuni2 tmu channel 2 underflow interrupt 1 tuni1 tmu channel 1 underflow interrupt tmu 0 tuni0 tmu channel 0 underflow interrupt indicates tmu interrupt sources. this register indicates the tmu interrupt sources even if the mask setting for tmu interrupts has been made in the interrupt mask register.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 288 of 1286 rej09b0158-0100 int2b1: indicates detailed interrupt sources for the rtc. module bit name detailed source description 31 to 3 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 2 cui rtc carry interrupt 1 pri rtc period interrupt rtc 0 ati rtc alarm interrupt indicates rtc interrupt sources. this register indicates the rtc interrupt sources even if the mask setting for rtc interrupts has been made in the interrupt mask register. int2b2: indicates detailed interrupt sources for the scif. module bit name detailed source description scif 31 to 8 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 7 txi1 scif channel 1 transmit fifo data empty interrupt 6 bri1 scif channel 1 break interrupt or overrun error interrupt 5 rxi1 scif channel 1 receive fifo data full interrupt or receive data ready interrupt 4 eri1 scif channel 1 receive error interrupt 3 txi0 scif channel 0 transmit fifo data empty interrupt 2 bri0 scif channel 0 break interrupt or overrun error interrupt 1 rxi0 scif channel 0 receive fifo data full interrupt or receive data ready interrupt indicates scif interrupt sources. this register indicates the scif interrupt sources even if the mask setting for scif interrupts has been made in the interrupt mask register. 0 eri0 scif channel 0 receive error interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 289 of 1286 rej09b0158-0100 int2b3: indicates detailed interrupt sources for the dmac. module bit name detailed source description 31 to 14 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 13 dmae1 dma channels 6 to 11 address error interrupt 12 dmae0 dma channels 0 to 5 address error interrupt 11 dmint11 channel 11 dma transfer end or half-end interrupt 10 dmint10 channel 10 dma transfer end or half-end interrupt 9 dmint9 channel 9 dma transfer end or half-end interrupt 8 dmint8 channel 8 dma transfer end or half-end interrupt 7 dmint7 channel 7 dma transfer end or half-end interrupt 6 dmint6 channel 6 dma transfer end or half-end interrupt 5 dmint5 channel 5 dma transfer end or half-end interrupt 4 dmint4 channel 4 dma transfer end or half-end interrupt 3 dmint3 channel 3 dma transfer end or half-end interrupt 2 dmint2 channel 2 dma transfer end or half-end interrupt 1 dmint1 channel 1 dma transfer end or half-end interrupt dmac 0 dmint0 channel 0 dma transfer end or half-end interrupt indicates dmac interrupt sources. this register indicates dmac interrupt sources even if a mask setting for dmac interrupts has been made in the interrupt mask register. note: the dma transfer end or half-end interrupt means the transfer has finished or half finished with the condition of specifi ed to the corresponding tcr.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 290 of 1286 rej09b0158-0100 int2b4: indicates detailed interrupt sources for the pcic. module bit name detailed source description 31 to 10 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 9 pwd0 pcic power state d0 state interrupt 8 pwd1 pcic power state d1 state interrupt 7 pwd2 pcic power state d2 state interrupt 6 pwd3 pcic power state d3 state interrupt 5 err pcic error interrupt 4 intd pcic intd interrupt 3 intc pcic intc interrupt 2 intb pcic intb interrupt 1 inta pcic inta interrupt pcic 0 serr pcic serr interrupt indicates pcic interrupt sources. this register indicates the pcic interrupt sources even if a mask setting for pcic interrupts has been made in the interrupt mask register.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 291 of 1286 rej09b0158-0100 int2b5: indicates detailed interrupt sources for the mmc. module bit name detailed source description 31 to 4 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 3 frdy fifo ready interrupt 2 err crc error interrupt, data timeout error interrupt, or command timeout error interrupt 1 tran data response interrupt, data transfer end interrupt, command response receive end interrupt, command transmit end interrupt, or data busy end interrupt mmcif 0 fstat mmc fifo empty interrupt or fifo full interrupt indicates mmc interrupt sources. this register indicates mmc interrupt sources even if the mask setting for mmc interrupts has been made in the interrupt mask register.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 292 of 1286 rej09b0158-0100 int2b6: indicates detailed interrupt sources for the flctl. module bit name detailed source description 31 to 4 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 3 fltrq1 flctl flecfifo transfer request interrupt 2 fltrq0 flctl tldtfifo transfer request interrupt 1 fltend flctl transfer end interrupt flctl 0 flste flctl status error interrupt or ready/busy timeout error interrupt indicates flctl interrupt sources. this register indicates flctl interrupt sources even if the mask setting for flctl interrupts has been made in the interrupt mask register.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 293 of 1286 rej09b0158-0100 int2b7: indicates detailed interrupt sources for the gpio. module bit name detailed source description gpio 31 to 26 ? (reserved) 25 porte6i gpio interrupt from port e pin 6. 24 portk5i gpio interrupt from port k pin 5. 23 to 20 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 19 portk4i gpio interrupt from port k pin 4. 18 portj0i gpio interrupt from port j pin 0. 17 porth1i gpio interrupt from port h pin 1. 16 porth0i gpio interrupt from port h pin 0. 15 to 11 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 10 porte5i gpio interrupt from port e pin 5. 9 porte4i gpio interrupt from port e pin 4. 8 porte3i gpio interrupt from port e pin 3. 7 to 3 ? (reserved) these bits are always read as 0. writing to these bits is invalid. 2 porte2i gpio interrupt from port e pin 2. 1 porte1i gpio interrupt from port e pin 1. 0 porte0i gpio interrupt from port e pin 0. indicates gpio interrupt sources. this register indicates the states of gpio interrupt sources even if gpio interrupts have been masked by the setting in the interrupt mask register.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 294 of 1286 rej09b0158-0100 10.3.15 gpio interrupt set register (int2gpic) int2gpic enables interrupt requests input from the following pins: pins 0 to 6 of port e, pins 0 and 1 of port h, pin 0 of port j, and pins 4 and 5 of port j. a gpio interrupt is an active low level-sensed si gnal. within the register, bits for the pins are arranged in four groups. pins 0 to 2 of port e are allocated to group 0, pins 3 to 5 of port e are allocated to group 1, pins 0 and 1 of port h, pin 0 of port j, and pin 4 of port k are allocated to group 2, and pin 5 of port k and pin 6 of port e are allocated to group 3. before enabling any of these interrupt requests, set the corresponding pin as an input in the corresponding port-control register (pecr, phcr, pjcr, pkcr). for the po rt-control registers, see section 28, general purpose i/o (gpio). 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r r r r r/w r/w r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ?? r/w r/w r/w r r r r r r/w r/w r/w r r r rr bit: initial value: r/w: when a gpio port pin is configured as an in terrupt, the intc is notified when the interrupt condition is satisfied on that pin. however, the interrupt is indicated as a one-bit source in the int2a0 or int2a1 register of the intc. the po rt and pin on which the interrupt was received can be identified by referring to the on-chip mo dule interrupt source register int2b7. the port group where the interrupt was generated can also be identified by referring to the intevt code in the cpu.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 295 of 1286 rej09b0158-0100 table 10.10 shows the correspondence between the interrupt input pins and bits in int2gpic. table 10.10 correspondence be tween interrupt i nput pins and bits in int2gpic bit initial value r/w name function description 31 to 26 all 0 r/w (reserved) these bits are always read as 0. the write value should always be 0. 25 0 r/w porte6e enables interrupt request from pin 6 of port e. 24 0 r/w portk5e enables interrupt request from pin 5 of port k. 23 to 20 all 0 r/w (reserved) these bits are always read as 0. the write value should always be 0. enables a gpio interrupt request for each pin. 0: disables the corresponding interrupt request 1: enables the corresponding interrupt request 19 0 r/w portk4e enables interrupt request from pin 4 of port k. 18 0 r/w portj0e enables interrupt request from pin 0 of port j. 17 0 r/w porth1e enables interrupt request from pin 1 of port h. 16 0 r/w porth0e enables interrupt request from pin 0 of port h. 15 to 11 all 0 r/w (reserved) (initial value: all 0) 10 0 r/w porte5e enables interrupt request from pin 5 of port e. 9 0 r/w porte4e enables interrupt request from pin 4 of port e. 8 0 r/w porte3e enables interrupt request from pin 3 of port e. 7 to 3 all 0 r/w (reserved) these bits are always read as 0. the write value should always be 0. 2 0 r/w porte2e enables interrupt request from pin 2 of port e. 1 0 r/w porte1e enables interrupt request from pin 1 of port e. 0 0 r/w porte0e enables interrupt request from pin 0 of port e.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 296 of 1286 rej09b0158-0100 10.4 interrupt sources there are four types of interrupt sources: nmi, irq, irl, and on-chip modules. each interrupt has a priority level (16 to 0), with level 16 as the high est and level 1 as the lowest. when level 0 is set, the interrupt is masked and interrupt requests are ignored. 10.4.1 nmi interrupt the nmi interrupt has the highest pr iority level of 16. it is alwa ys accepted unless the bl bit in sr of the cpu is set to 1. in sleep mode, the interrupt is accepted even if the bl bit is set to 1. a setting can also be made to have the nmi interrup t accepted even if the bl bit is set to 1. input from the nmi pin is edge -detected. the nmi edge selection bit (nmie) in icr0 is used to select either the rising or falling edge for detection. after modification of the nmie bit in icr0, the nmi interrupt is not detected for at least six bu s clock cycles after the modification. when the intmu bit in the cpuopm is set to 1, the interrupt mask level (imask) in sr is automatically modified to level 15 on the acceptance of an nm i interrupt. when the intmu bit in cpuopm is cleared to 0, the imask value in sr is not a ffected by the acceptance of an nmi interrupt. 10.4.2 irq interrupts irq interrupts are input by single-pin interrupts on pins irq/ irl7 to irq/ irl0 . irq interrupts are available when pins irq/ irl7 to irq/ irl0 are made to operate as irqn (n = 0 to 7) independent interrupt inputs by setting the irlm0 and irlm1 bits in icr0 to 1. the irqns1 and irqns0 bits in icr1 are used to select one from among rising-edge, falling- edge, low-level, and high-level detection. a priority level (from 15 to 0) can be set for each input by writing to intpri. when an irq interrupt request is set for detection of the low level or high level, the irq interrupt pin input level should be held until the cpu ha s accepted the interrupt and started interrupt exception handling. when high- or low-level detection has been selected, usage or non-usage of the holding function for interrupt requests can be sel ected by setting or clearing the lsh bit in icr0. when usage of the holding function has been selected (icr0.lsh = 0), interrupt requests are held in the detection circuit and the interrupt request must be cleared in the exception handling routine after acceptance of the interrupt. for details, refer to section 10.7 usage notes. to select non-usage of the holding function, set the lsh bit in icr0 to 1. in this case, the operation of irq level detection provides
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 297 of 1286 rej09b0158-0100 upward compatibility with the ?level-sense irq mo de? of current sh-4 pr oducts (here, too, the detection of high or low levels is selectable). note: when high-or low-level detection is selected, once the interrupt request has been detected, the intc holds the interrupt request as an interrupt source in intreq even if the level on the irq interrupt pin has been changed and canceled. the interrupt source is held until the cpu accepts any interrupt request (irq or not) or the corresponding interrupt mask bit is set to 1. moreover, when the holding function is selected by clearing the lsh bit in icr0 to 0, the interrupt request is held in the det ection circuit. in this case, clearing of the interrupt request in the exception handling routine must be followed by clearing of the interrupt source setting being held in intreq. for details, see section 10.7 usage notes. when the intmu bit in cpuopm is set to 1, the interrupt mask level (imask) in sr is automatically modified to the level of an accepted interrupt. when the intm u bit is cleared to 0, the imask value in sr is not affect ed by the acceptance of an interrupt. 10.4.3 irl interrupts irl interrupts are input as combinations of levels on pins irq/ irl7 to irq/ irl4 or irq/ irl3 to irq/ irl0 . the priority level is the value indicated by the levels (active low) on pins irq/ irl7 to irq/ irl4 or irq/ irl3 to irq/ irl0 . the low level on all pins from irq/ irl7 to irq/ irl4 or irq/ irl3 to irq/ irl0 corresponds to the highest-level interrupt request (interrupt priority level 15), and the high level on all pins corresponds to no interrupt request (interrupt priority level 0). figure 10.2 shows an example of irl interrupt connection, and table 10.11 shows the correspondence between the combinations of levels on the irl pins and priority. priority encoder interrupt requests sh7780 irq/ irl3 to irq/ irl0 irq/ irl7 to irq/ irl4 irl7 to irl4 irl3 to irl0 interrupt requests priority encoder . . . . . . figure 10.2 example of irl interrupt connection
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 298 of 1286 rej09b0158-0100 table 10.11 irl[3:0], irl[7:4] pins and interrupt levels irl3 or irl7 irl2 or irl6 irl1 or irl5 irl0 or irl4 interrupt priority level interrupt request low low low low 15 level 15 interrupt request low low low high 14 level 14 interrupt request low low high low 13 level 13 interrupt request low low high high 12 level 12 interrupt request low high low low 11 level 11 interrupt request low high low high 10 level 10 interrupt request low high high low 9 level 9 interrupt request low high high high 8 level 8 interrupt request high low low low 7 level 7 interrupt request high low low high 6 level 6 interrupt request high low high low 5 level 5 interrupt request high low high high 4 level 4 interrupt request high high low low 3 level 3 interrupt request high high low high 2 level 2 interrupt request high high high low 1 level 1 interrupt request high high high high 0 no interrupt request irl interrupt detection requires a built-in noise -cancellation feature; that is, a mechanism to ensure that transient level changes on the irl pins are not detected as interru pts. for this purpose, an irl interrupt is not detected unless the levels sampled per bus-clock cycle remain unchanged for four consecutive cycles. the irl interrupt priority level should be mainta ined until the cpu has accepted the interrupt and started interrupt exception handling. it is possible to change the priority level to a higher priority. when irl level-encoded interrupts have been selected, usage or non-usage of the holding function for interrupt requests can be selected by clearing or setting the lsh bit in icr0. when usage of the holding function has been selected (icr0.lsh = 0), interrupt requests are held in the detection circuit and the interrupt request must be cleared in the exception handling routine after acceptance of the interrupt. for details, refer to section 10.7 usage notes. to select non-usage of the holding function, set the lsh bit in icr0 to 1. in this case, the operation of irl level detection provides upward compatibility with the level-encoded irl interrupts on current sh-4 products.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 299 of 1286 rej09b0158-0100 note: there is no interrupt source register for irl interrupt requests. when the holding function is in use, however, operation is as follows. if , after detection of an irl interrupt, the levels on the irl pins are changed or withdraw the interrupt before it has been accepted by the cpu, the detection circuit retains the highest detected priority level for irl interrupts until the cpu accepts any interrupt re quest (irl or not) or the corresponding mask bit has been set to 1. the interrupt exception handling rou tine must then clear the irl interrupt request held in the detection circuit. for details, see section 10.7 usage notes. when the intmu bit in cpuopm is set to 1, the interrupt mask level (imask) in sr is automatically modified to the level of the accepte d interrupt. when the intm u bit is cleared to 0, the imask value in sr is not affect ed by the acceptance of an interrupt. 10.4.4 on-chip module interrupts on-chip module interrupts are interrupts generated by on-chip modules. the interrupt sources are not assigned unique interrupt vectors; however, the sources are reflected in the interrupt event register (intevt), so using the intevt value as a branch offset in the exception handling routine provides a convenient and useful way to identify the sources and handle the individual interrupts. a priority level from 31 to 0 can be set for each module by means of int2pri0 to int2pri7. the intc rounds off the lowest order bit and sends a 4-bit code to the cpu. for details, see section 10.4.5, interrupt priority levels of on-chip module interrupts. the interrupt mask level bits (imask) in sr are not affected by the processing of an on-chip module interrupt. interrupt source flags and interrupt enable flags for on-chip modules should only be updated when the bl bit in sr is set to 1 or while the corresponding interrupt will not occur because its mask bit has been set. to prevent the erroneous acceptance of interrupts from sources that should have been updated, start by reading the on-chip module regist er that contains the co rresponding flag, wait for the priority determination time shown in table 10.13 (i.e. the period required to read a register in intc; this operation is driven by the peripheral cl ock), and then clear the bl bit to 0 or clear the corresponding interrupt ma sk. this will secure the necessary time internal ly. when a number of flags have to be updated, reading only the register containing the last flag to have been updated causes no problems. if flag updating is performed while the bl bit is cleared to 0, the program may jump to the interrupt handling routine when the intevt value is 0. in this case, interrupt processing is initiated due to the timing relationship between the updating of the flag and recognition of the
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 300 of 1286 rej09b0158-0100 interrupt request within this lsi. processing can be continued without any problem after the execution of an rte instruction. 10.4.5 interrupt priority levels of on-chip module interrupts when any interrupt is generated, the intc outputs the corresponding interrupt exception code (intevt code) to the cpu. the code identifies the individual interrupt source. when the cpu accepts an interrupt, the corresponding intevt code is indicated in intevt. even without reading the interrupt source regist er of the intc, the interrupt sour ce can be identified by reading intevt of the cpu from the interrupt handler. table 10.12 lists the sources of interrupts and the corresponding interrupt exception codes. an on-chip module interrupt source can be assigned any of 30 (5-bit) priority levels (see figure 10.3). the interrupt level-receptio n interface is four bits wide and thus handles 15 priority levels (with h'0 as the interrupt-request mask setting). the value in the intc consists of five bits, one bit of which is an extension that allows the assignme nt of an individual priority level to each of the on-chip modules. when the cpu is notified of the priority, the lowest-order bit is rounded off to leave four bits of data. for example, two interrupt sources with priority levels set to h'1a and h'1b will both be output to the cpu as the 4-b it priority level h'd. that is, the two interrupt sources have the same priority value. however, although the rounded codes are the same for both interrupt sources, the interrupt with priority leve l h'1b clearly has priority when we consider the 5-bit data in the priority setting. that is, the 5-bit values in the fields shown in table 10.5 give intc a way to differentiate between interrupts with the same four-bit priority level.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 301 of 1286 rej09b0158-0100 priority level h'01 acts as an interrupt request mask. intc distinguishes between priority levels of h'1a and h'1b, although both become the same level after rounding off for the cpu. intc priority level: higher (h'1b) lower (h'1a) cpu priority level: even (h'd) when multiple interrupt requests from on-chip modules occur simultaneously, the intc processes the interrupt with the higher priority level; in the case above, the interrupt will be that corresponding to the h'1b priority level. however, if an external interrupt request is also generated at the same time the external interrupt request will have higher priority if it is; - an nmi interrupt request - an irq or irl interrupt request that has the same priority level or higher priority level (h'd or greater in the case shown above). intc priority level: h'01 cpu priority level: h'0 (interrupt is masked) priority level h'01 becomes h'00 with discarding of the lowest-order bit, so the cpu is not notified of the corresponding interrupt. the range of priority levels in the interrupt priority register thus h'02 to h'1f (30 priority levels). 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 figure 10.3 on-chip module interrupt priority 10.4.6 interrupt exceptio n handling and priority table 10.12 lists the codes for the interrupt event register (intevt) and the order of interrupt priority. each interrupt source is assigned a unique in tevt code. the start address of the exception handling routine is the same for all of the interrupt sources. therefore, the intevt value is used to control branching at the start of the exce ption handling routine. for instance, the intevt values are suitable for use as branch offsets. the priority order of the on-chip modules is specified as desired by setting values from 31 to 2 in int2pri0 to int2pri7. values 0 and 1 mask the corresponding interrupt. the priority values for the on-chip modules are retu rned to 0 by a reset. when interrupt sources share the same priority level and are generated simultaneously, they are handled according to the default prio rity order given in table 10.12. values of intpri, int2pri0 to int2pri7, intmsk0 to intmsk2, and int2mskr should only be updated while the bl bit in sr is set to 1, or the corresponding interrupt is masking. to prevent erroneous interrupt acceptan ce, clear the bl bit to 0 after ha ving read one of the interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 302 of 1286 rej09b0158-0100 priority level-setting registers, or clear the co rresponding interrupt mask. this will secure the necessary timing internally. table 10.12 interrupt excepti on handling and priority interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority nmi ? h'1c0 16 ? ? ? high irl[7:4] = llll (h'0) h'200 15 intmsk2[15] intmskclr2[15] ? ? irl[3:0] = llll (h'0) intmsk2[31] intmskclr2[31] ? ? irl[7:4] = lllh (h'1) h'220 14 intmsk2[14] intmskclr2[14] ? ? irl[3:0] = lllh (h'1) intmsk2[30] intmskclr2[30] ? ? irl[7:4] = llhl (h'2) h'240 13 intmsk2[13] intmskclr2[13] ? ? irl[3:0] = llhl (h'2) intmsk2[29] intmskclr2[29] ? ? irl l: low level input h: high level input (see table 10.11) irl[7:4] = llhh (h'3) h'260 12 intmsk2[12] intmskclr2[12] ? ? irl[3:0] = llhh (h'3) intmsk2[28] intmskclr2[28] ? ? irl[7:4] = lhll (h'4) h'280 11 intmsk2[11] intmskclr2[11] ? ? irl[3:0] = lhll (h'4) intmsk2[27] intmskclr2[27] ? ? irl[7:4] = lhlh (h'5) h'2a0 10 intmsk2[10] intmskclr2[10] ? ? irl[3:0] = lhlh (h'5) intmsk2[26] intmskclr2[26] ? ? irl[7:4] = lhhl (h'6) h'2c0 9 intmsk2[9] intmskclr2[9] ? ? irl[3:0] = lhhl (h'6) intmsk2[25] intmskclr2[25] ? ? low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 303 of 1286 rej09b0158-0100 interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority irl[7:4] = lhhh (h'7) h'2e0 8 intmsk2[8] intmskclr2[8] ? ? high irl[3:0] = lhhh (h'7) intmsk2[24] intmskclr2[24] ? ? irl[7:4] = hlll (h'8) h'300 7 intmsk2[7] intmskclr2[7] ? ? irl[3:0] = hlll (h'8) intmsk2[23] intmskclr2[23] ? ? irl[7:4] = hllh (h'9) h'320 6 intmsk2[6] intmskclr2[6] ? ? irl[3:0] = hllh (h'9) intmsk2[22] intmskclr2[22] ? ? irl l: low level input h: high level input (see table 10.11) irl [7:4] = hlhl (h'a) h'340 5 intmsk2[5] intmskclr2[5] ? ? irl[3:0] = hlhl (h'a) intmsk2[21] intmskclr2[21] ? ? irl[7:4] = hlhh (h'b) h'360 4 intmsk2[4] intmskclr2[4] ? ? irl[3:0] = hlhh (h'b) intmsk2[20] intmskclr2[20] ? ? irl[7:4] = hhll (h'c) h'380 3 intmsk2[3] intmskclr2[3] ? ? irl[3:0] = hhll (h'c) intmsk2[19] intmskclr2[19] ? ? irl[7:4] = hhlh (h'd) h'3a0 2 intmsk2[2] intmskclr2[2] ? ? irl[3:0] = hhlh (h'd) intmsk2[18] intmskclr2[18] ? ? irl[7:4] = hhhl (h'e) h'3c0 1 intmsk2[1] intmskclr2[1] ? ? irl[3:0] = hhhl (h'e) intmsk2[17] intmskclr2[17] ? ? low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 304 of 1286 rej09b0158-0100 interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority irq irq[0] h'240 intpri [31:28] intmsk0[31] intmskclr0 [31] intreq [31] ? high high irq[1] h'280 intpri [27:24] intmsk0[30] intmskclr0 [30] intreq [30] ? irq[2] h'2c0 intpri [23:20] intmsk0[29] intmskclr0 [29] intreq [29] ? irq[3] h'300 intpri [19:16] intmsk0[28] intmskclr0 [28] intreq [28] ? irq[4] h'340 intpri [15:12] intmsk0[27] intmskclr0 [27] intreq [27] ? irq[5] h'380 intpri [11:8] intmsk0[26] intmskclr0 [26] intreq [26] ? irq[6] h'3c0 intpri [7:4] intmsk0[25] intmskclr0 [25] intreq [25] ? irq[7] h'200 intpri [3:0] intmsk0[24] intmskclr0 [24] intreq [24] ? low rtc ati h'480 int2b1[0] high pri h'4a0 int2b1[1] cui h'4c0 int2pri1 [4:0] int2mskr[2] int2mskcr[2] int2a0[2] int2a1[2] int2b1[2] low wdt iti * h'560 int2pri2 [12:8] int2mskr[5] int2mskcr[5] int2a0[5] int2a1[5] ? tmu-ch0 tuni0 * h'580 int2pri0 [28:24] int2a0[0] int2a1[0] int2b0[0] tmu-ch1 tuni1 * h'5a0 int2pri0 [20:16] int2b0[1] tmu-ch2 tuni2 * h'5c0 int2pri0 [12:8] int2b0[2] ticpi2 * h'5e0 int2pri0 [4:0] int2mskr[0] int2mskcr[0] int2b0[3] low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 305 of 1286 rej09b0158-0100 interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority h-udi h-udii h'600 int2pri3 [28:24] int2mskr[7] int2mskcr[7] int2a0[7] int2a1[7] ? high dmac(0) dmint0 * h'640 int2b3[0] high dmint1 * h'660 int2pri3 [20:16] int2mskr[8] int2mskcr[8] int2a0[8] int2a1[8] int2b3[1] dmint2 * h'680 int2b3[2] dmint3 * h'6a0 int2b3[3] dmae (ch0 to 5) * h'6c0 int2b3[12] dmae (ch6 to 11) * int2b3[13] low scif-ch0 eri0 * h'700 int2b2[0] high rxi0 * h'720 int2pri2 [28:24] int2mskr[3] int2mskcr[3] int2a0[3] int2a1[3] int2b2[1] bri0 * h'740 int2b2[2] txi0 * h'760 int2b2[3] low dmac(0) dmint4 * h'780 int2b3[4] high dmint5 * h'7a0 int2pri3 [20:16] int2mskr[8] int2mskcr[8] int2a0[8] int2a1[8] int2b3[5] low dmac(1) dmint6 * h'7c0 int2b3[6] high dmint7 * h'7e0 int2pri3 [12:8] int2mskr[9] int2mskcr[9] int2a0[9] int2a1[9] int2b3[7] low ctm cmti h'900 int2pri4 [28:24] int2mskr[12] int2mskcr[12] int2a0[12] int2a1[12] ? hac haci h'980 int2pri4 [20:16] int2mskr[13] int2mskcr[13] int2a0[13] int2a1[13] ? pcic(0) pciserr h'a00 int2pri4 [12:8] int2mskr[14] int2mskcr[14] int2a0[14] int2a1[14] int2b4[0] pcic(1) pciinta h'a20 int2pri4 [4:0] int2mskr[15] int2mskcr[15] int2a0[15] int2a1[15] int2b4[1] pcic(2) pciintb h'a40 int2pri5 [28:24] int2mskr[16] int2mskcr[16] int2a0[16] int2a1[16] int2b4[2] pcic(3) pciintc h'a60 int2pri5 [20:16] int2mskr[17] int2mskcr[17] int2a0[17] int2a1[17] int2b4[3] pcic(4) pciintd h'a80 int2pri5 [12:8] int2mskr[18] int2mskcr[18] int2a0[18] int2a1[18] int2b4[4] low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 306 of 1286 rej09b0158-0100 interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority pcic(5) pcierr h'aa0 int2b4[5] high high pcipwd3 h'ac0 int2pri5 [4:0] int2mskr[19] int2mskcr[19] int2a0[19] int2a1[19] int2b4[6] pcipwd2 h'ae0 int2b4[7] pcipwd1 h'b00 int2b4[8] pcipwd0 h'b20 int2b4[9] low scif-ch1 eri1 * h'b80 int2b2[4] high rxi1 * h'ba0 int2pri2 [20:16] int2mskr[4] int2mskcr[4] int2a0[4] int2a1[4] int2b2[5] bri1 * h'bc0 int2b2[6] txi1 * h'be0 int2b2[7] low siof siofi h'c00 int2pri6 [28:24] int2mskr[14] int2mskcr[14] int2a0[14] int2a1[14] ? hspi spii h'c80 int2pri6 [20:16] int2mskr[21] int2mskcr[21] int2a0[21] int2a1[21] ? mmcif fstat h'd00 int2b5[0] high tran h'd20 int2pri6 [12:8] int2mskr[22] int2mskcr[22] int2a0[22] int2a1[22] int2b5[1] err h'd40 int2b5[2] frdy h'd60 int2b5[3] low dmac(1) dmint8 * h'd80 int2b3[8] high dmint9 * h'da0 int2pri3 [12:8] int2a0[9] int2a1[9] int2b3[9] dmint10 * h'dc0 int2mskr[9] int2mskcr[9] int2b3[10] dmint11 * h'de0 int2b3[11] low tmu-ch3 tuni3 * h'e00 int2pri1 [28:24] int2mskr[1] int2mskcr[1] int2a0[1] int2a1[1] int2b0[4] tmu-ch4 tuni4 * h'e20 int2pri1 [20:16] int2b0[5] tmu-ch5 tuni5 * h'e40 int2pri1 [12:8] int2b0[6] ssi ssii h'e80 int2pri6 [4:0] int2mskr[23] int2mskcr[23] int2a0[23] int2a1[23] ? low
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 307 of 1286 rej09b0158-0100 interrupt source intevt code interrupt priority mask/clear register & bit interrupt source register detail source register priority within sets of sources default priority flctl flste * h'f00 int2b6[0] high high fltend * h'f20 int2pri7 [28:24] int2mskr[24] int2mskcr[24] int2a0[24] int2a1[24] int2b6[1] fltrq0 * h'f40 int2b6[2] fltrq1 * h'f60 int2b6[3] low gpio gpioi0 (port e0) h'f80 int2b7[0] high gpioi0 (port e1) int2mskr[25] int2mskcr[25] int2a0[25] int2a1[25] int2b7[1] gpioi0 (port e2) int2pri7 [20:16] int2b7[2] gpioi1 (port e3) h'fa0 int2b7[8] gpioi1 (port e4) int2b7[9] gpioi1 (port e5) int2b7[10] gpioi2 (port h0) h'fc0 int2b7[16] gpioi2 (port h1) int2b7[17] gpioi2 (port j0) int2b7[18] gpioi2 (port k4) int2b7[19] gpioi3 (port k5) h'fe0 int2b7[24] gpioi3 (port e6) int2b7[25] low low note: * iti: interval timer interrupt tuni0 to tuni5: tmu channels 0 to 5 under flow interrupt ticpi2: tmu channel 2 input capture interrupt dmint0 to dmint11: transfer end or half-end interrupts for dmac channel 0 to 11 dmae: dmac address error interrupt (channel 0 to 11) eri0, eri1: scif channel 0, 1 receive error interrupts rxi0, rxi1: scif channel 0, 1 receive data full interrupts bri0, bri1: scif channel 0, 1 break interrupts txi0, txi1: scif channel 0, 1 transmission data empty interrupts flste: flctl error interrupt fltend: flctl error interrupt fltrq0: flctl data fifo transfer request interrupt fltrq1: flctl control code fifo transfer request interrupt
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 308 of 1286 rej09b0158-0100 10.5 operation 10.5.1 interrupt sequence the sequence of interrupt operations is described below. figure 10.4 is the flowchart of the operations. 1. interrupt request sources send interrupt request signals to the intc. 2. the intc selects the interrupt with the highes t-priority among the inte rrupts that have been sent, according to the priority levels set in intpri and int2pri0 to int2pri7. lower- priority interrupts are held as pending interrupts . if two of the interrupts have the same priority level or multiple interrupts are generated by a single module, the interrupt with the highest priority is selected acco rding to table 10.12. 3. the priority level of the interrupt selected by the intc is compared with the interrupt mask level (imask) set in sr of the cpu. if the prio rity level is higher than the mask level, the intc accepts the interrupt and sends an interrupt request signal to the cpu. 4. the cpu accepts an interrupt at th e next break between instructions. 5. the interrupt source code is set in the interrupt event register (intevt). 6. the sr and program counter (pc) are saved in ssr and spc, respectively. at the same time, r15 is saved in sgr. 7. the bl, md, and rb bits in sr are set to 1. 8. execution jumps to the start address of the interrupt exception handling routine (the sum of the value set in the vector base register (vbr) and h'0000 0600). in the exception handling routine, branching with the intevt value as an offset provides a convenient way to differentiate between the interrupt sources. execution thus branches to the handling routines for the individual interrupt sources. notes: 1. when the intmu bit in the cpu operating mode register (cpuopm) is set to 1, the interrupt mask level (imask) in sr is au tomatically set to the level of the accepted interrupt. when the intmu bit is cleared to 0, the imask value in sr is not affected by the accepted interrupt. 2. the interrupt source flag should be cleared in the interrupt handling routine. to ensure that an interrupt source which should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, wait for the time shown in table 10.8, and then clear the bl bi t or execute an rte instruction. 3. the power-on reset initializes the values of the interrupt mask bits for irq interrupts, irl interrupts, and interrupts for the on-ch ip modules. thus, intmskclr must be used to clear the interrupt mask setting (intmsk) for any required irq, irl, and on- chip module interrupts .
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 309 of 1286 rej09b0158-0100 program execution state interrupt generated? icr0.mai = 1? sr.bl = 0 or sleep mode? yes yes yes yes yes yes yes yes yes yes yes yes no no no no no no no no nmi? no yes no no yes is nmi input low? level 15 interrupt? no no no set interrupt source code in intevt save sr in ssr; save pc in spc; save r15 in sgr set sr.imask to accepted interrupt level branch to exception handling routine is sr.imask level 14 or less level 14 interrupt? level 1 interrupt? nmi? is sr.imask level 13 or less is sr.imask level 0? icr0.nmib = 1? cpuopm.intmu = 1? figure 10.4 interrupt operation flowchart
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 310 of 1286 rej09b0158-0100 10.5.2 multiple interrupts when multiple interrupts must be handled, the interrupt handling routine should include the following procedure: 1. identify the interrupt source by using the in tevt code as an offset in branching to the corresponding interrupt handling routine. 2. clear the interrupt source in the corresponding interrupt handling routine. 3. save ssr and spc on the stack. 4. clear the bl bit in sr. when the intmu bit in cpuopm is set to 1, the interrupt mask level (imask) in sr is automatically modified to the priority level of the accepted interrupt. when the intmu bit in cpuopm is clear ed to 0, use software to set the imask bit in sr to the same priority level as the accepted interrupt. 5. execute processing as required in response to the interrupt. 6. set the bl bit in sr to 1. 7. restore ssr and spc from the stack. 8. execute the rte instruction. following this procedure in the above order ensure s that, if further interrupts are generated, an interrupt with higher pr iority than the one currently being handled can be accepted after step 4. this reduces the interrupt response time for urgent processing. 10.5.3 interrupt masking by mai bit setting the mai bit in icr0 to 1 selects masking of interrupts while the nmi signal is low regardless of the bl and imask bit settings in sr. ? normal operation or sleep mode all other interrupts are masked while the nmi signal is low. note that only nmi interrupts due to nmi signal input are generated.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 311 of 1286 rej09b0158-0100 10.6 interrupt response time table 10.13 shows the components of the interrupt response time for the five classes of interrupt in terms of response time. the response time is the interval from generation of an interrupt request until the start of interrupt exception handling; i.e. until fetching of the first instruction of the exception handling routine. table 10.13 interrupt response time formulae for response time on-chip modules item nmi irl irq other than gpio/pcic/ rtc gpio/pcic/ rtc remarks priority determination time 5bcyc + 2pcyc 8bcyc + 2pcyc 4bcyc + 2pcyc 5pcyc 7pcyc wait time until the cpu finishes the current sequence s-1 ( 0) icyc interval from the start of interrupt exception handling (saving sr and pc) until a superhyway bus request is issued to fetch the first instruction of the exception handling routine 11icyc + 1scyc total (s + 10) icyc + 1scyc + 5bcyc + 2pcyc (s + 10) icyc + 1scyc + 8bcyc + 2pcyc (s + 10) icyc + 1scyc + 4bcyc + 2pcyc (s + 10) icyc + 1scyc + 5pcyc (s + 10) icyc + 1scyc + 7pcyc response time minimum 29icyc + sxicyc 27icyc + sxicyc 35icyc + sxicyc 31icyc + sxicyc 39icyc + sxicyc when icyc:scyc: bcyc:pcyc = 4:4:2:1 [legend] icyc: period of one cpu clock cycle scyc: period of one superhyway clock cycle bcyc: period of one bus clock cycle pcyc: period of one peripheral clock cycle s: number of instruct ion execution states
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 312 of 1286 rej09b0158-0100 10.7 usage notes 10.7.1 to clear interrupt request when holding function selected when an irq level-sense interrupt request or irl level-encoded interrupt request (irq/irl level interrupt request) is generated and the holding function is in use, the interrupt request must be cleared in the interrupt handling routine after it has been accepted. figure 10.5 shows an example of an interrupt-handling routine to clear interr upt request holding in the detection circuit. interrupt handling instruct the external device to cancel the irq/irl level interrupt request by using the gpio output or writing to an address in the local bus allow time for the cancellation of external device interrupt requests and for the intc to respond to cancellation requests clear the irq/irl level interrupt request holding in the detection circuit and clear the irq interrupt source end of irq/irl level interrupt handling 1) writing to the gpio register or local bus space. 2) read the address of writing. allow at least 8 bus-clock cycles for cancellation and the intc response time. 1) set the corresponding bit in intmsk0/1 to 1. 2) set the corresponding bit in intmskclr0/1 to 1. 3) read intmsk0/1. start of irq level-sense or irl level-encoded interrupt (irq/irl level interrupt) handling figure 10.5 example of interrupt hand ling routine to cancel an interrupt request after its acceptance by the cpu, the external device that generated the request must be notified of its acceptance. the method of noti fication might take the form of using the gpio to output the acceptance level or in terrupt pin information, or writing to a special address in the local bus space. it is necessary to consecutively execute writing to and reading from the gpio register or the special location in the local bus space. after clearing an interrupt request that is held in the detection circuit, ensure that the time required for the cpu to detect the interrupt has elapsed. to ensure this time, cons ecutively execute writing to intmsk0/1 and intmskclr0/1 and reading of intmsk0/1.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 313 of 1286 rej09b0158-0100 10.7.2 notes on setting irq/ irl[7:0] pin function when switching between individual interrupt and level-encoded interrupt functions on the irq/ irl[7:0] pins, the intc may wind up holding an interrupt that was generated by mistake. therefore, to prevent the detection of such unintentional interrupts, mask all irq and irl interrupts before switching between irq/ irl[7:0] pin functions. table 10.14 switching sequence of irq/ irl[7:0] pin function sequence item procedure 1 irl interrupt request and irq interrupt request masking write 1 to all bits in intmsk0 and intmsk1 2 setting irl/ irq[7:4] pins to operate as interrupt-request pins write 0 to the omsel12 bit in omselr write 0 to the pe6md[1:0] bits in pecr 3 setting irq/ irl[7:0] pins for level- encoded or individual interrupt request input and setting usage of holding function for irq level-sense or irl interrupt set the irlm[1:0] bits and the lsh bit in icr0 4 start of irl and irq interrupt detection write 1 to the corresponding bit in intmskclr0 and intmskclr1 10.7.3 to clear irq and irl interrupt requests the procedure for clearing interrupts held in the intc is as follows. ? to clear irl interrupt requests when the holding function is in use (icr0.lsh = 0), clear an irl interru pt request from the irq/irl[3:0] pins by writing a 1 to the im10 bit in intmsk1, and clear an irl interrupt request from the irq/irl[7:4] pins by writing a 1 to the im11 bit in the same register. irl interrupt requests held in the detection circuit ar e not cleared even if eac h of the corresponding interrupt levels is masked by the setting in intmsk2. when the holding function is not in use (icr0.lsh = 1), interrupt requests are simply not held. ? to clear irq level-sense interrupt requests when the holding function is in use (icr0.lsh = 0), clear an irq level-sense interrupt request from the irq/ irl[7:0] pins by writing a 1 to the corresponding mask bit (im07 to im00) of intmsk0.
section 10 interrupt controller (intc) rev.1.00 dec. 13, 2005 page 314 of 1286 rej09b0158-0100 irq interrupt requests held in the detection circu it are not cleared even if a 0 is written to the corresponding bit in intpri. the irq interrupt so urces detected by the intc (which will be cleared when they are accepte d by the cpu) can be confirmed by reading intreq. when not using holding function (icr0.lsh = 1), the interrupt request is not held but the interrupt source is set to the corresponding bit in intreq that is to be cleared when the cpu accepts it. ? to clear irq edge-detection interrupt requests to clear an irq edge-detection interrupt request from the irq/ irl[7:0] pins, read the value 1 from the corresponding irn (n = 0 to 7) bit in intreq and then write a 0 to the same bit. an irq interrupt request detected by the intc is not cleared even if a 1 is written to the corresponding bit in intmsk0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 315 of 1286 rej09b0158-0100 section 11 local bus state controller (lbsc) the local bus state controller (lbsc) divides the external memory sp ace and outputs control signals corresponding to the sp ecifications of various types of memory and bus interfaces. the lbsc enables the connection of sram or rom, et c., to this lsi. it also supports the pcmcia interface protocol, which is used to implement simplified system design and high-speed data transfers in a compact system. 11.1 features the lbsc has the following features. ? controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven areas. ? maximum 64 mbytes for each of areas 0 to 2 and 4 to 6 ? bus width of each area can be controlled through register settings (except area 0, which is controlled by the external pin setting) ? wait-cycle insertion by the rdy pin ? wait-cycle insertion can be controlled by a program ? types of memory are specifiab le for connection to each area ? output of the control signals of memory to each area ? automatic wait cycle insertion to prevent data bus collisions on consecutive memory accesses ? insertion of cycles to ensure the setup time and hold time to the write strobe on a write cycle enables connection to low-speed memory ? sram interface ? wait-cycle insertion can be controlled by a program ? insertion of the wait cycle through the rdy pin connectable areas : 0 to 2 and 4 to 6 settable bus widths: 32, 16, and 8 bits ? burst rom interface ? wait-cycle insertion can be controlled by a program ? burst length specified by the register connectable areas: 0 to 2 and 4 to 6 settable bus widths: 32, 16, and 8 bits
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 316 of 1286 rej09b0158-0100 ? mpx interface ? address/data multiplexing connectable areas: 0 to 2 and 4 to 6 settable bus width: 32 bits ? byte control sram interface ? sram interface with byte control connectable areas: 1 and 4 settable bus widths: 32 and 16 bits ? pcmcia interface ? wait-cycle insertion can be controlled by a program ? bus sizing function for i/o bus width ? little endian connectable areas: 5 and 6 settable bus widths: 16 and 8 bits ? function for ata device access figure 11.1 shows a block diagram of the lbsc.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 317 of 1286 rej09b0158-0100 lbsc wait control unit bus interface rdy breq , iois16 mode5 to mode3 cs0 to cs2 cs4 to cs6 ce2a , ce2b a25 to a0 back , bs rd / frame r/ w we3 / iowr we2 / iord we1 , we0 / reg area control unit [legned] bcr: csnbcr: csnpcr: csnwcr: bus control register csn bus control register (n = 0 to 2, 4 to 6) csn pcmcia control register(n = 5, 6) csn wait control register (n = 0 to 2, 4 to 6) memory control unit csnwcr d31 to d0 csnbcr bcr csnpcr superhyway bus module bus figure 11.1 lbsc block diagram
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 318 of 1286 rej09b0158-0100 11.2 input/output pins table 11.1 shows the lbsc pin configuration. table 11.1 pin configuration pin name function i/o description a25 to a0 address bus output address output d31 to d0 * 1 data bus i/o data input/output bs bus cycle start output signal that indicates the start of a bus cycle. asserted once for a burst transfer when setting mpx interface. asserted each data cycle for a burst transfer when setting other interfaces. cs6 to cs4 , cs2 to cs0 chip select 6 to 4 and 2 to 0 output chip select signal that indicates the area being accessed. cs5 and cs6 can also be used as ce1a to ce1b of pcmcia. r/ w read/write output data bus i nput/output direction designation signal. also used as pcmcia interface write designation signal. rd / frame read/cycle frame output strobe signal indicating a read cycle. frame signal when setting mpx interface. we0 / reg data enable 0 output when setting sram interface: write strobe signal for d7 to d0 when setting pcmcia interface: reg signal we1 data enable 1 output when setting sram interface: write strobe signal for d15 to d8 when setting pcmcia interface: write strobe signal we2 / iord data enable 2 output when setting sram interface: write strobe signal for d23 to d16 when setting pcmcia interface: iord signal we3 / iowr data enable 3 output when setting sram interface: write strobe signal for d31 to d24 when setting pcmcia interface: iowr signal rdy ready input wait cycle request signal
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 319 of 1286 rej09b0158-0100 pin name function i/o description iois16 * 2 16-bit i/o input 16-bit i/o signal when setting pcmcia interface. valid only in little endian mode breq * 3 bus release request input bus release request signal back bus request acknowledge output bus release acknowledge signal ce2a * 4 , ce2b * 4 pcmcia card select output when setting pcmcia, ce2a and ce2b mode3 * 5 , mode4 * 5 area 0 bus width input signal setting area 0 bus width and mpx interface at power-on reset mode5 * 6 endian switchover input endian setting at a power-on reset dack0 * 7, 10 dma channel 0 transfer end notification output strobe output from channel 0 to external device which has output dreq0 * 11 , regarding dma transfer request dack1 * 7, 10 dma channel 1 transfer end notification output strobe output from channel 1 to external device which has output dreq1 * 11 , regarding dma transfer request dack2 * 8, 10 dma channel 2 transfer end notification output strobe output from channel 2 to external device which has output dreq2 * 11 , regarding dma transfer request dack3 * 9, 10 dma channel 3 transfer end notification output strobe output from channel 3 to external device which has output dreq3 * 11 , regarding dma transfer request notes: 1. these pins are multiplexed with the gpio pins. 2. this pin is multiplex ed with the tmu/rtc and gpio pin. 3. this pin is multiplexed with the gpio pin. 4. when bits type2 to type0 in the cs5 bus control register (cs5bcr) are set to b'100, ce2a act as pcmcia output pin, and bits type2 to type0 in the cs6 bus control register (cs6bcr) are set to b'100, ce2b act as pcmcia output pin. 5. this pin is multiplexed with the intc and flctl pin. 6. this pin is multiplexed with the scif, mmcif and gpio pin. 7. this pin is multiplexed wit h the mode control and gpio pin. 8. this pin is multiplexed with the mresetout , h-udi, and gpio pin. 9. this pin is multiplexed with the intc, h-udi and gpio pin. 10. can be selectable the polarity (initial st ate is low active). for details, see section 14, direct memory access controller (dmac). 11. can be selectable the polarity and detection edge (initial state is low active). for details, see section 14, direct memory access controller (dmac).
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 320 of 1286 rej09b0158-0100 11.3 area overview 11.3.1 space divisions the architecture of this lsi pr ovides a 32-bit address space. the virtual address space is divided into five areas (p0 to p4 areas) according to the upper address value. this lsi supports both a 29-bit and a 32-bit phys ical address space, and the lbsc supports a 29- bit physical address space. the 29-bit physical addres s space is divided into eight areas (areas 0 to 7) according to the upper three bits [28:26] of an address and the lbsc can control areas 0 to 2 and 4 to 6 as an external memory space. the maxi mum capacity of each area used as an external memory space is 64 mbytes; the lbsc can control a total of 6 areas with a maximum capacity of 384 mbytes as the external memory spaces. a virtual address can be allocated to any physical address through the address translation function of the mmu. for details, see section 7, memory management unit (mmu). with the lbsc, various types of memory or pc car ds can be connected to each of the six areas as shown in table 11.2, an d accordingly output the chip select signals ( cs0 to cs2 , cs4 to cs6 , ce2a and ce2b ). cs0 to cs2 are asserted when accessing ar eas 0 to 2 individually, and cs4 to cs6 are asserted when accessing areas 4 to 6 individually. when the pcmcia interface is selected for area 5 or 6, ce2a or ce2b is asserted along with cs5 and cs6 for the bytes to be accessed. area 3 is for ddr-sdram me mory space and controlled by the ddr-sdram interface (ddrif). for details, see section 12, ddr-sdram interface (ddrif). areas 2, 4, and 5 can also be used for the ddr-sdram memory space, and area 4 can also be used for the pci memory space by setting the me mory address map select register (mmselr). area 7 is a reserved area. for the pci memory sp ace, see section 13, pci controller (pcic). both ddrif and pcic support a 32-bit physical address sp ace in addition to a 29-b it address. for a 32- bit physical address, refer also to section 7.7, 32-bit address extended mode.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 321 of 1286 rej09b0158-0100 h'0000 0000 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff h'e400 0000 h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1fff ffff h'1c00 0000 area 0 area 1 area 2 (area 3) area 4 area 5 area 6 area 7 (reserved area) p0 and u0 areas p1 area p2 area p3 area virtual address space (mmu off) virtual address space (mmu on) lbsc external memory space store queue area p4 area p0 and u0 areas 256 p1 area p2 area p3 area store queue area p4 area notes: 1. when the mmu is off (mmucr.at = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. 3. when the mmu is on (mmucr.at = 1), the p0, u0, p3, and store queue areas can be mapped onto any external space using the tlb. for details, see section 7, memory management unit (mmu). area 3 is for ddr-sdram memory and controlled by the ddrif. for details, see section 12, ddr-sdram interface (ddrif). figure 11.2 correspondence between virtual address space and external memory space of lbsc
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 322 of 1286 rej09b0158-0100 table 11.2 lbsc extern al memory space map area external addresses size connectable memory specifiable bus width (bits) access size * 8 sram 8, 16, 32 * 1 burst rom 8, 16, 32 * 1 0 h'0000 0000 to h'03ff ffff 64 mbytes mpx 32 * 1 8/16/32 bits and 32 bytes sram 8, 16, 32 * 2 burst rom 8, 16, 32 * 2 mpx 32 * 2 1 h'0400 0000 to h'07ff ffff 64 mbytes byte control sram 16, 32 * 2 8/16/32 bits and 32 bytes sram 8, 16, 32 * 2 burst rom 8, 16, 32 * 2 mpx 32 * 2 2 * 4 h'0800 0000 to h'0bff ffff 64 mbytes (ddr-sdram) 32 8/16/32 bits and 32 bytes 3 * 3 h'0c00 0000 to h'0fff ffff 64 mbytes (ddr-sdram) 32 8/16/32 bits and 32 bytes sram 8, 16, 32 * 2 burst rom 8, 16, 32 * 2 mpx 32 * 2 byte control sram 16, 32 * 2 (ddr-sdram) 32 4 * 4, 5 h'1000 0000 to h'13ff ffff 64 mbytes (pci) 32 8/16/32 bits and 32 bytes sram 8, 16, 32 * 2 burst rom 8, 16, 32 * 2 mpx 32 * 2 pcmcia 8, 16 * 2, 6 5 * 4 h'1400 0000 to h'17ff ffff 64 mbytes (ddr-sdram) 32 8/16/32 bits and 32 bytes sram 8, 16, 32 * 2 burst rom 8, 16, 32 * 2 mpx 32 * 2 6 h'1800 0000 to h'1bff ffff 64 mbytes pcmcia 8, 16 * 2, 6 8/16/32 bits and 32 bytes
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 323 of 1286 rej09b0158-0100 area external addresses size connectable memory specifiable bus width (bits) access size * 8 7 * 7 h'1c00 0000 to h'1fff ffff 64 mbytes ? ? ? notes: 1. the memory bus width is spec ified by external pins (mode3 and mode4). 2. the memory bus width is specified by the register. 3. area 3 is used specifically for t he ddr-sdram. for details, see section 12, ddr- sdram interface (ddrif). 4. these areas can be used for the ddr-s dram by setting mmselr. for details, see section 12, ddr-sdram interface (ddrif). 5. this area can be used for the pci memory by setting mmselr. for details, see section 13, pci controller (pcic). 6. with the pcmcia interface, the bus width is either 8 bits or 16 bits. 7. area 7 is a reserved area. if a reserved area is accessed, correct operation cannot be guaranteed. 8. if 8 or 16 bytes access transfer by another lsi internal bus master module is being executed, the lbsc is executing two or four times 32-bit access individually. area 0: h'0000 0000 area 1: h'0400 0000 area 2: h'0800 0000 area 3: h'0c00 0000 area 4: h'1000 0000 area 5: (1st half) h'1400 0000 (2nd half) h'1600 0000 area 6: (1st half) h'1800 0000 (2nd half) h'1a00 0000 sram/burst rom/mpx sram/burst rom/mpx/byte control sram sram/burst rom/mpx/ddr-sdram ddr-sdram sram/burst rom/mpx/byte control sram /ddr-sdram/pci sram/burst rom/mpx/pcmcia /ddr-sdram sram/burst rom/mpx/pcmcia the pcmcia interface is for memory and i/o card use figure 11.3 external memory spac e allocation (29-bit address mode)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 324 of 1286 rej09b0158-0100 11.3.2 memory bus width the memory bus width of the lbsc can be set independently for each area. for area 0, a bus width of 8, 16, or 32 bits is se t according to the external pin sett ings at a power-on reset by the preset pin. the correspondence be tween the external pins (mod e 4 and mode 3) and the bus width at a power-on reset is shown below. table 11.3 correspondence between ex ternal pins (mode4 and mode3) mode 4 mode 3 bus width low low 32 bits (for mpx interface) low high 8 bits high low 16 bits high high 32 bits (other than mpx) when either the sram or rom interface is used in areas 1 to 2 and 4 to 6, a bus width of 8, 16, or 32 bits can be selected through the csn bus control register (csnbcr). when the burst rom interface is used, a bus width of 8, 16, or 32 b its can be selected. when the byte-control sram interface is used, a bus width of 16 or 32 bits can be selected. wh en the mpx interface is used, a bus width of 32 bits should be selected. when using the pcmcia interface, a bus width of 8 or 16 bits should be selected. for details, see section 11.5.5, pc mcia interface. for details, see section 11.4.3, csn bus control register (csnbcr). the bus width of the ddr-sdram and the pci interfaces is 32 bits. for details, see section 12, ddr-sdram interface (ddrif), and section 13, pci controller (pcic). the addresses of area 7 (h'1c00 0000 to h'1fff ffff) are reserved and must not be used.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 325 of 1286 rej09b0158-0100 11.3.3 data alignment this lsi supports the big endian and little endian methods of data alignment. the data alignment method is specified using the external pin (mode5) at a power-on reset. table 11.4 correspondence between external pin (mode5) and endian mode 5 endian low big endian high little endian 11.3.4 pcmcia support this lsi supports the pcmcia interface specificati ons for areas 5 and 6 in the external memory space. the ic memory card interface and i/o card inte rface prescribed in jeida specifications version 4.2 (pcmcia2.1) are supported. both the ic memory card interface and the i/o card interface are sup ported in areas 5 and 6 in the external memory space. the pcmcia interface is only su pported in little endian mode. table 11.5 pcmcia interface features item features access random access data bus 8/16 bits memory type masked rom, otprom, eprom, flash memory, sram, ata device common memory capacity maximum 64 mbytes attribute memory capacity maximum 64 mbytes others dynamic bus sizing for i/o bus width, access to ata devices control register
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 326 of 1286 rej09b0158-0100 table 11.6 pcmcia support interface ic memory card interface i/o card interface pin signal name * 1 i/o * 1 function signal name * 1 i/o * 1 function corresponding pin of this lsi 1 gnd ground gnd ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable cs5 or cs6 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we i write enable we i write enable we1 16 ready o ready ireq o interrupt request sensed on port 17 vcc operation power supply vcc operation power supply ? 18 vpp1 (vpp) programming power supply vpp1 (vpp) programming/ peripheral power supply ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 327 of 1286 rej09b0158-0100 ic memory card interface i/o card interface pin signal name * 1 i/o * 1 function signal name * 1 i/o * 1 function corresponding pin of this lsi 30 d0 i/o data d0 i/o data d0 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp * 2 o write protect iois16 o 16-bit i/o port iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection sensed on port 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2a or ce2b 43 rfsh ( vs1 ) i refresh request rfsh ( vs1 ) i refresh request output from port 44 rsrvd reserved iord i i/o read iord 45 rsrvd reserved iowr i i/o write iowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 vcc power supply vcc power supply ? 52 vpp2 (vpp) programming power supply vpp2 (vpp) programming/ peripheral power supply ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address a25 57 rsrvd reserved rsrvd reserved ?
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 328 of 1286 rej09b0158-0100 ic memory card interface i/o card interface pin signal name * 1 i/o * 1 function signal name * 1 i/o * 1 function corresponding pin of this lsi 58 reset i reset reset i reset output from port 59 wait o wait request wait o wait request rdy * 3 60 rsrvd reserved inpack o input acknowledge ? 61 reg i attribute memory space select reg i attribute memory space select reg 62 bvd2 o battery voltage detection spkr o digital voice signal sensed on port 63 bvd1 o battery voltage detection stschg o card status change sensed on port 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection sensed on port 68 gnd ground gnd ground ? notes: 1. i/o means input/output on the side of the pcmcia card. the polarity of the pcmcia card interface means that on the side of the card, while the polarity of the corresponding pin of this lsi means that on the side of this lsi. 2. wp is not supported. 3. check the polarity.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 329 of 1286 rej09b0158-0100 11.4 register descriptions table 11.7 shows the lbsc register configuratio n. table 11.8 shows the register state in each processing mode. table 11.7 register configuration register name abbrev. r/w p4 address area 7 address access size * memory address map select register mmselr r/w h'ff40 0020 h'1f40 0020 32 bus control register bcr r/w h'ff80 1000 h'1f80 1000 32 cs0 bus control register cs0bcr r/w h'ff80 2000 h'1f80 2000 32 cs1 bus control register cs1bcr r/w h'ff80 2010 h'1f80 2010 32 cs2 bus control register cs2bcr r/w h'ff80 2020 h'1f80 2020 32 cs4 bus control register cs4bcr r/w h'ff80 2040 h'1f80 2040 32 cs5 bus control register cs5bcr r/w h'ff80 2050 h'1f80 2050 32 cs6 bus control register cs6bcr r/w h'ff80 2060 h'1f80 2060 32 cs0 wait control register cs0wcr r/w h'ff80 2008 h'1f80 2008 32 cs1 wait control register cs1wcr r/w h'ff80 2018 h'1f80 2018 32 cs2 wait control register cs2wcr r/w h'ff80 2028 h'1f80 2028 32 cs4 wait control register cs4wcr r/w h'ff80 2048 h'1f80 2048 32 cs5 wait control register cs5wcr r/w h'ff80 2058 h'1f80 2058 32 cs6 wait control register cs6wcr r/w h'ff80 2068 h'1f80 2068 32 cs5 pcmcia control register cs5pcr r/w h'ff80 2070 h'1f80 2070 32 cs6 pcmcia control register cs6pcr r/w h'ff80 2080 h'1f80 2080 32 note: * do not access registers with other than the designated access size.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 330 of 1286 rej09b0158-0100 table 11.8 register state in each processing mode register name abbrev. power-on reset manual reset sleep memory address map select register mmselr h'0000 0000 h'0000 0000 retained bus control register bcr h'x000 0000 retained retained cs0 bus control register cs0bcr h'7777 7770 retained retained cs1 bus control register cs1bcr h'7777 7770 retained retained cs2 bus control register cs2bcr h'7777 7770 retained retained cs4 bus control register cs4bcr h'7777 7770 retained retained cs5 bus control register cs5bcr h'7777 7770 retained retained cs6 bus control register cs6bcr h'7777 7770 retained retained cs0 wait control register cs0wcr h'7777 770f retained retained cs1 wait control register cs1wcr h'7777 770f retained retained cs2 wait control register cs2wcr h'7777 770f retained retained cs4 wait control register cs4wcr h'7777 770f retained retained cs5 wait control register cs5wcr h'7777 770f retained retained cs6 wait control register cs6wcr h'7777 770f retained retained cs5 pcmcia control register cs5pcr h'7700 0000 retained retained cs6 pcmcia control register cs6pcr h'7700 0000 retained retained
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 331 of 1286 rej09b0158-0100 11.4.1 memory address map select register (mmselr) mmselr is a 32-bit register that selects memory address maps for areas 2 to 5. this register should be accessed at the address h'ff40 0020 in longword. writing is acc epted only when the upper 16-bit data is h'a5a5 to prevent unintentional writing. the upper 29 bits are always read as 0. this register is initialized by a power-on reset or a manual reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 areasel ? ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 ? all 0 r/w reserved set these bits to h'a5a5 only when writing to areasel bits in this register. these bits are always read as 0. 15 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 332 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 to 0 areasel 000 r/w ddrif/pcic memory space select 000: sets area 3 (h'0c00 0000 to h'0fff ffff) as the ddrif space and other areas as the lbsc space 001: sets area 3 (h'0c00 0000 to h'0fff ffff) as the ddrif space, area 4 (h'1000 0000 to h'13ff ffff) as the pci memory space, and other areas as the lbsc space 010: sets areas 2 and 3 (h'0800 0000 to h'0fff ffff) as the ddrif space and other areas as the lbsc space 011: sets areas 2 and 3 (h'0800 0000 to h'0fff ffff) as the ddrif space, area 4 (h'1000 0000 to h'13ff ffff) as the pci memory space, and other areas as the lbsc space 100: sets areas 2 to 5 (h'0800 0000 to h'17ff ffff) as the ddrif space 101: setting prohibited 110: setting prohibited 111: setting prohibited the mmselr must be written by the cpu. wr iting to mmselr, the dmac or pcic module must be set not to access to any resources, and all processing should be fini shed (for example, the synco instruction preceding the mov instruction should be executed) before mmselr is modified. in addition, execute the mov instruction to read out mmselr (a dummy read) twice and the synco instruction in succession immediately after a mov inst ruction of write to mmselr. example: ----------------------------------------------------------------------- mov.l #h'ff400020, r0 ; mov.l #mmselr_data, r1 ; mmselr_data=writing value of mmselr synco ; (upper word=h'a5a5) mov.l r1, @r0 ; writing to mmselr mov.l @r0, r2 mov.l @r0, r2 synco -----------------------------------------------------------------------
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 333 of 1286 rej09b0158-0100 the instruction to modi fy the value of the mms elr should be allocated non-cacheable p2 area and an address that will not be affected by an address map change. write to mmselr before enabling the instru ction cache, operand cache, and mmu address translation, and then do not write to it agai n until after power-on reset or manual reset. 11.4.2 bus control register (bcr) bcr is a 32-bit readable/writable register that sp ecifies the function and bus cycle status for each area. bcr is initialized to h'0000 0000 in big endian or h'8000 0000 in little endian by a power- on reset, but is not initialized by a manual reset mode. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 * 0 dma bst breq en ? ? dackbst[3:0] opup ? dpup ? ? ? end ian ? r/w r/w r r r/w r/w r/w r/w r/w r r/w r r r r/w r bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 async[6:0] ? ? ? ? ? ? ? ? hiz cnt r/w r/w r/w r/w r/w r/w r/w r r r r r r r r r/w bit: initial value: r/w: note: * the intial value of the endian bit (bit 31) depends on the mode5 pin setting. bit bit name initial value r/w description 31 endian 0/1 r endian flag the value of the external pin (mode5) designating the endian mode is sampled at a power-on reset by the preset pin. this bit determines the endian mode of all spaces. 0: indicates that the external pin (mode5) designating the endian mode is low at a power-on reset and big- endian mode is specified for this lsi. 1: indicates that the external pin (mode5) designating the endian mode is high at a power-on reset and little-endian mode is specified for this lsi. 30 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 334 of 1286 rej09b0158-0100 bit bit name initial value r/w description 26 dpup 0 r/w data pin pull-up resistor control specifies the pull-up resistor state of the data pins (d31 to d0). this bit is initialized by a power-on reset. the pins are not pulled up when access is performed or when the bus is released, even if the pull-up resistor is on. 0: cycles in which the pull-up resistors of the data pins (d31 to d0) are turned on are inserted before and after a memory access. * 1: pull-up resistor is off for data pins (d31 to d0). note: * we recommend that a pull-up resistor be externally connected to the data pins if it is required. 25 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 24 opup 0 r/w control output pin pull-up resistor control specifies the pull-up resistor state (a25 to a0, bs , cs0 to cs2 , cs4 to cs6 , rd / frame , we , r/ w , ce2a , and ce2b ) when the control output pins are high- impedance. this bit is initialized by a power-on reset. 0: pull-up resistors are on for control output pins (a25 to a0, bs , cs0 to cs2 , cs4 to cs6 , rd / frame , we , r/ w , ce2a , and ce2b ) 1: pull-up resistors are off for control output pins (a25 to a0, bs , cs0 to cs2 , cs4 to cs6 , rd / frame , we , r/ w , ce2a , and ce2b ) 23 to 20 dackbst [3:0] all 0 r/w dack burst select the assert period of dack0 to dack3 signals. 0: dack signals asserted in synchronization with the bus cycle. 1: dack signals remain asserted from burst start to end in dma burst transfer mode only set to 1 when the area of a dack assertion in dma transfer is the pcmcia interface memory area, otherwise this bit should be cleared to 0. dackbst[3]: dack3 dackbst[2]: dack2 dackbst[1]: dack1 dackbst[0]: dack0
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 335 of 1286 rej09b0158-0100 bit bit name initial value r/w description 19, 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 breqen 0 r/w breq enable indicates whether or not an external bus request can be accepted. this bit is initialized to the state where an external bus request is not accepted at a power-on reset. 0: an external bus request is not accepted 1: an external bus request is accepted 16 dmabst 0 r/w dmac burst mode transfer priority setting specifies the priority of burst mode transfers by the dmac. when this bit is cleared to 0, the priority is as follows: bus release, dmac (burst mode), cpu, dmac, pcic. when this bit is set to 1, the bus release is not performed until completion of the dmac burst transfer. this bit is initialized at a power-on reset. 0: dmac burst mode transfer priority setting off 1: dmac burst mode transfer priority setting on 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 hizcnt 0 r/w high imp edance (hi-z) control specifies the state of signals we and rd / frame during the bus-released state. 0: signals of we and rd / frame are high-impedance during the bus-released state 1: signals of we and rd / frame are output during the bus-released state 13 to 7 ? 0 r reserved these bits are always read as 0. the write value should always be 0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 336 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 to 0 async[6:0] all 0 r/w asynchronous input enable asynchronous input to the corresponding pins. 0: input signals to the corresponding pins must be synchronized with clkout 1: input signals to the corresponding pins can be asynchronous to clkout async[6]: dreq3 async[5]: dreq2 async[4]: dreq1 async[3]: dreq0 async[2]: iois16 async[1]: breq async[0]: rdy 11.4.3 csn bus control register (csnbcr) csnbcr are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 2 and 4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory types. some types of memory continue to drive the da ta bus immediately after the read signal is inactivated. therefore, a data bus collision may o ccur when there is cons ecutive memory access to different areas or writing to a memory immediatel y after reading. this lsi automatically inserts the number of idle cycles set by csnbcr to prevent data bus collision. csnbcr is initialized to h'7777 7770 by a power-on reset, but is not initialized by a manual reset. do not access external memory space other than area 0 until the cs nbcr initialization is completed. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 0 1 1 1 0 1 1 1 0 1 1 01 iwrrd ? iwrws ? iwrwd ? iww ? r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 1 1 1 0 1 1 1 0 1 1 01 type mpx bw rdspl sz bst iwrrs ? r/w r/w r/w r/w * r/w r/w r/w r/w r/w * r/w * r/w r/w r/w r/w r note: * bits sz and mpx in cs0bcr are read-only. r/w bit: initial value: r/w:
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 337 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 to 28 iww 111 r/w idle cycles between write-read/write-write specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. the target cycles are write-read cycles and write-write cycles. for details , see section 11.5.8, wait cycles between accesses. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted 27 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 26 to 24 iwrwd 111 r/w idle cycles between read-write to different spaces specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. the target cycles are read-write cycles to different spaces. for details, see section 11.5.8, wait cycles between accesses. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 338 of 1286 rej09b0158-0100 bit bit name initial value r/w description 23 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 22 to 20 iwrws 111 r/w idle cycles between read-write to same space specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. the target cycles are read-write cycles to the same space. for details , see section 11.5.8, wait cycles between accesses. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 18 to 16 iwrrd 111 r/w idle cycles between read-read to different spaces specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. the target cycles are read-read cycles to different spaces. for details, see section 11.5.8, wait cycles between accesses. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 339 of 1286 rej09b0158-0100 bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 to 12 iwrrs 111 r/w idle cycles between read-read to same space specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed. the target cycles are read-read cycles to the same space. for details , see section 11.5.8, wait cycles between accesses. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 3 idle cycles inserted 100: 4 idle cycles inserted 101: 5 idle cycles inserted 110: 6 idle cycles inserted 111: 7 idle cycles inserted 11, 10 bst 01 r/w burst length when a burst rom interface is used, these bits specify the number of accesses in a burst. the mpx interface is not affected. 00: 4 consecutive accesses (can be used with 8-, 16-, or 32-bit bus width) 01: 8 consecutive accesses (can be used with 8-, 16-, or 32-bit bus width) 10: 16 consecutive accesses (can be used with 8-, or 16-bit bus width) 11: 32 consecutive accesses (can be used with 8-bit bus width)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 340 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9, 8 sz 11 r/w * bus width specify the bus width. set to 11 for the mpx interface, and set to 10 or 11 for the byte control sram interface. in cs0bcr, the external pins (mode3 and mode4) are sampled at a power-on reset. 00: reserved 01: 8 bits 10: 16 bits 11: 32 bits note: * bits sz in cs0bcr are read-only. the sz bits in cs0bcr are set to 11 when area 0 is set to the mpx interface by the mode3 and mode4 pins. 7 rdspl 0 r/w rd hold cycle specifies the number of cycles to be inserted into the rd assertion period to elongate the data hold time for the read data sample timing. when setting this bit to 1, specify the number of rd negation- csn negation delay cycles as 1 or more by setting the rdh bit in csnwcr. also the rd negation- csn negation delay cycle is reduced by 1 cycle when this bit is set to 1 (available only when the sram interface or byte control sram interface). 0: no hold cycle inserted 1: 1 hold cycle inserted 6 to 4 bw 111 r/w burst pitch when the burst rom interfac e is used, these bits specify the number of wait cycles to be inserted after the second data access in a burst transfer. 000: no idle cycle inserted, rdy signal disabled 001: 1 idle cycle inserted, rdy signal enabled 010: 2 idle cycles inserted, rdy signal enabled 011: 3 idle cycles inserted, rdy signal enabled 100: 4 idle cycles inserted, rdy signal enabled 101: 5 idle cycles inserted, rdy signal enabled 110: 6 idle cycles inserted, rdy signal enabled 111: 7 idle cycles inserted, rdy signal enabled
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 341 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 mpx 0 r/w * mpx interface setting selects the type of mpx interface 0: interface that is specified by type bits 1: mpx interface selected note: * the mpx bit in cs0bcr is read-only. 2 to 0 type 000 r/w memory type setting specify the type of memory connected to the space. 000: sram (initial value) 001: sram with byte-control * 1 010: burst rom (burst at read/sram at write) 011: reserved (setting prohibited) 100: pcmcia * 2 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) note: 1. setting possible only in cs1bcr and cs4bcr 2. setting possible only in cs5bcr and cs6bcr
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 342 of 1286 rej09b0158-0100 11.4.4 csn wait control register (csnwcr) csnwcr (n = 0 to 2, 4 to 6) are 32-bit readable/wr itable registers that specify the number of wait cycles to be inserted, the pitch of data access fo r burst memory accesses, an d the number of cycles to be inserted for the address setup time to the read/write strobe assertion or for the data hold time from the write strobe negation. csnbcr is initialized to h'7777 770f by a power-on reset, but is not initialized by a manual reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 0 1 1 1 0 1 1 1 0 1 1 01 rdh ? rds ? adh ? ads ? r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r r/w r/w r r/w bit: initial value: r/w: ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 0 0 0 0 1 1 1 0 1 1 01 iw[3:0] bsh wth wts ? r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r r/w bit: initial value: r/w: bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 to 28 ads 111 r/w address setup cycle specify the number of cycles to be inserted to ensure the address setup time to the csn assertion. (available only when the sram interface, byte control sram interface, or burst rom interface is selected.) clear to 0 when using pcmcia interface. 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 343 of 1286 rej09b0158-0100 bit bit name initial value r/w description 27 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 26 to 24 adh 111 r/w address hold cycle specify the number of cycles to be inserted to ensure the address hold time to the csn negation. (available only when the sram interface, byte control sram interface, or burst rom interface is selected.) 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted 23 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 22 to 20 rds 111 r/w rd setup cycle ( csn assertion? rd assertion delay cycle) specify the number of cycles to be inserted form csn assertion to rd assertion (available only when the sram interface, byte contro l sram interface, or burst rom interface is selected.) 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 344 of 1286 rej09b0158-0100 bit bit name initial value r/w description 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 18 to 16 rdh 111 r/w rd hold cycle ( rd negation? csn negation delay cycle) specify the number of cycles to be inserted from rd negation to csn negation. (available only when the sram interface, byte control an sram interface, or burst rom interface is selected.) 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 to 12 wts 111 r/w we setup cycle ( csn assertion? we assertion delay cycle) specify the number of cycles to be inserted from csn assertion to we assertion. (available only when the sram interface, byte control an sram interface, or burst rom interface is selected.) 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 345 of 1286 rej09b0158-0100 bit bit name initial value r/w description 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 to 8 wth 111 r/w we hold cycle ( we negation? csn negation delay cycle) specify the number of cycles to be inserted from we negation to csn negation. (available only when the sram interface, byte contro l sram interface, or burst rom interface is selected.) 000: no cycle inserted 001: 1 cycle inserted 010: 2 cycles inserted 011: 3 cycles inserted 100: 4 cycles inserted 101: 5 cycles inserted 110: 6 cycles inserted 111: 7 cycles inserted 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 to 4 bsh 000 r/w bs hold cycle specify the number of cycles for the bs assertion. total access cycle number is not change by setting these bits. this setting is valid when csn assertion- rd or - we assertion delay cycle (rds or wts setting) is set to 1 or more. 000: bs assertion is 1 cycle 001: bs assertion is 2 cycle 010: setting prohibited 011: setting prohibited 100: setting prohibited 101: setting prohibited 110: setting prohibited 111: setting prohibited
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 346 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 to 0 iw[3:0] 1111 r/w insert wait cycle specify the number of wait cycles to be inserted. ? when the sram interface, byte control sram interface, burst rom interface (first data cycle only), or pcmcia interface is selected, the following cycles are inserted. the exte rnal wait cycle insertion by using the rdy pin monitor cannot be used when no cycle inserted is selected. 0000: no cycle inserted 1000: 8 cycles inserted 0001: 1 cycle inserted 100 1: 9 cycles inserted 0010: 2 cycles inserted 1010: 11 cycles inserted 0011: 3 cycles inserted 1011: 13 cycles inserted 0100: 4 cycles inserted 1100: 15 cycles inserted 0101: 5 cycles inserted 1101: 17 cycles inserted 0110: 6 cycles inserted 1110: 21 cycles inserted 0111: 7 cycles inserted 1111: 25 cycles inserted ? when the mpx interface is selected, the following cycles are inserted by the setting value of iw [2:0] and then iw3 setting is invalid. and the external wait cycle insertion by using the rdy pin monitor can be used in all the following settings. iw2 specifies the number of wait cycle to be inserted into second data or after. 0: no cycle inserted 1: 1 cycle inserted iw[1:0] specify the number of wait cycles to be inserted into first data. 00: 1 cycle inserted into read cycle and no cycle inserted into write cycle 01: 1 cycle inserted into read cycle and 1 cycle inserted into write cycle 10: 2 cycles inserted into read cycle and 2 cycles inserted into write cycle 11: 3 cycles inserted into read cycle and 3 cycles inserted into write cycle
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 347 of 1286 rej09b0158-0100 11.4.5 csn pcmcia control register (csnpcr) csnpcr is a 32-bit readable/writable register that specifies the timing fo r the pcmcia interface connected to area n (n = 5 or 6), the space pr operty, and the assert /negate timing for the oe ( rd ) and we signals. in addition, the wait timing for ar ea 5 and 6 access can be set in csnpcr for the first half and second half individually. the first half of area 5 is allocated from h'1400 0000 to h'15ff ffff, and the second half of area 5 is a llocated from h'1600 0000 to h'17ff ffff. the first half of area 6 is allocated from h'1800 0000 to h'19ff ffff, and the second half of area 6 is allocated from h'1a00 0000 to h'1bff ffff (each address is an external address). the pulse widths of oe and we assertion for the first half of area 5 and 6 are set using the iw bits in csnwcr. csnpcr is initialized to h'7700 0000 by a power-on reset, but is not initialized by a manual reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 0 1 1 01 pciw pcwa pcwb sab ? saa ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r r/w bit: initial value: r/w: ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 tehb teha tedb teda ? r/w r/w r/w r r/w r/w r/w r r/w r/w r/w r/w r/w r/w r r/w bit: initial value: r/w: bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 to 28 saa 111 r/w space property a specify the space property of pcmcia connected to first half of area n (n = 5 and 6). 000: ata complement mode 001: dynamic i/o bus sizing 010: 8-bit i/o space 011: 16-bit i/o space 100: 8-bit common memory 101: 16-bit common memory 110: 8-bit attribute memory 111: 16-bit attribute memory
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 348 of 1286 rej09b0158-0100 bit bit name initial value r/w description 27 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 26 to 24 sab 111 r/w space property b specify the space property of pcmcia connected to second half of area n (n = 5 and 6). 000: ata complement mode 001: dynamic i/o bus sizing 010: 8-bit i/o space 011: 16-bit i/o space 100: 8-bit common memory 101: 16-bit common memory 110: 8-bit attribute memory 111: 16-bit attribute memory 23, 22 pcwa 00 r/w pcmcia wait a wait cycle for low-speed pc mcia. the number of wait cycles specified by these bits is added to the number designated by the iw bits in csnwcr. these bits are valid, when the access area of pcmcia interface is first half of area n (n = 5 and 6). 00: no wait cycle inserted 01: 15 wait cycles inserted 10: 30 wait cycles inserted 01: 50 wait cycles inserted 21, 20 pcwb 00 r/w pcmcia wait b wait cycle for low-speed pc mcia. the number of wait cycles specified by these bits is added to the number designated by pciw. these bits are valid, when the access area of pcmcia interface is second half of area n (n = 5 and 6). 00: no wait cycle inserted 01: 15 wait cycles inserted 10: 30 wait cycles inserted 01: 50 wait cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 349 of 1286 rej09b0158-0100 bit bit name initial value r/w description 19 to 16 pciw 0000 r/w pcmcia insert wait cycle b specify the number of wait cycles to be inserted. these bits are valid, when the access area of pcmcia interface is second half of area n (n = 5 and 6). 0000: no cycle inserted 0001: 1 cycle inserted 0010: 2 cycles inserted 0011: 3 cycles inserted 0100: 4 cycles inserted 0101: 5 cycles inserted 0110: 6 cycles inserted 0111: 7 cycles inserted 1000: 8 cycles inserted 1001: 9 cycles inserted 1010: 11 cycles inserted 1011: 13 cycles inserted 1100: 15 cycles inserted 1101: 17 cycles inserted 1110: 21 cycles inserted 1111: 25 cycles inserted note: specify the number of wait cycle designated by csnwcr when the access area of pcmcia interface is first half of area 5 or 6. 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 350 of 1286 rej09b0158-0100 bit bit name initial value r/w description 14 to 12 teda 000 r/w oe / we assert delay a these bits set the delay time from address output to oe / we assertion for the access of first half area of pcmcia interface (area n, n = 5 and 6). 000: no wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 to 8 tedb 000 r/w oe / we assert delay b these bits set the delay time from address output to oe / we assertion for the access of second half area of pcmcia interface (area n, n = 5 and 6). 000: no wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 351 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 to 4 teha 000 r/w oe / we negation-address delay a these bits set the delay time from oe / we negation to address hold for the access of first half area of pcmcia interface (area n, n = 5 and 6). 000: no wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 to 0 tehb 000 r/w oe / we negation-address delay b these bits set the delay time from oe / we negation to address hold for the access of second half area of pcmcia interface (area n, n = 5 and 6). 000: no wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted 011: 3 wait cycles inserted 100: 6 wait cycles inserted 101: 9 wait cycles inserted 110: 12 wait cycles inserted 111: 15 wait cycles inserted
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 352 of 1286 rej09b0158-0100 11.5 operation 11.5.1 endian/access size and data alignment this lsi supports both big-endian mode, in which the upper byte in a string of byte data is at address 0, and little-endian mode, in which the lower byte in a string of byte data is at address 0. the mode is specified by the external pin (mod e5 pin) at a power-on reset through the reset pin. at a power-on reset by preset , big-endian mode is specified when the mode5 pin is low, and little-endian mode is specified when the mode5 pin is high. a data bus width of 8, 16, or 32 bits can be sel ected for the normal memory interface, and one of 8 or 16 bits can be selected for the pcmcia interf ace. data alignment is carried out according to the data bus width and endian mode of each device. accordingly, when the data bus width is smaller than the access size, multiple bus cycles are automatically genera ted to reach the access size. in this case, access is performed by incrementing th e addresses corresponding to the bus width. for example, when a longword access is performed at the area with an 8-bit width in the sram interface, each address is incremented one by one, and then access is performed four times. in the 32-byte transfer, a total of 32-byte data is con tinuously transferred accordin g to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wraparound method accor ding to the set bus width. the bus is not released during these transfers. in this lsi, data alignment and data length conversion between different interfaces is performed automatically. when an 8- or 16-byte transfer is requested, the lbsc executes the transfer in two or four separate 4-byte accesses. the relationship between the endi an mode, device data length, and access unit are shown in tables 11.9 to 11.14.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 353 of 1286 rej09b0158-0100 table 11.9 32-bit extern al device/big-e ndian access and data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte 4n 1 data 7 to 0 ? ? ? assert 4n + 1 1 ? data 7 to 0 ? ? assert 4n + 2 1 ? ? data 7 to 0 ? assert 4n + 3 1 ? ? ? data 7 to 0 assert word 4n 1 data 15 to 8 data 7 to 0 ? ? assert assert 4n + 2 1 ? ? data 15 to 8 data 7 to 0 assert assert longword 4n 1 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert table 11.10 16-bit external device/bi g-endian access a nd data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte 2n 1 ? ? data 7 to 0 ? assert 2n + 1 1 ? ? ? data 7 to 0 assert word 2n 1 ? ? data 15 to 8 data 7 to 0 assert assert longword 4n 1 ? ? data 31 to 24 data 23 to 16 assert assert 4n + 2 2 ? ? data 15 to 8 data 7 to 0 assert assert
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 354 of 1286 rej09b0158-0100 table 11.11 8-bit external device/big-endian access and data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte n 1 ? ? ? data 7 to 0 assert word 2n 1 ? ? ? data 15 to 8 assert 2n + 1 2 ? ? ? data 7 to 0 assert longword 4n 1 ? ? data 31 to 24 assert 4n + 1 2 ? ? ? data 23 to 16 assert 4n + 2 3 ? ? ? data 15 to 8 assert 4n + 3 4 ? ? ? data 7 to 0 assert
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 355 of 1286 rej09b0158-0100 table 11.12 32-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte 4n 1 ? ? ? data 7 to 0 assert 4n + 1 1 ? ? data 7 to 0 ? assert 4n + 2 1 ? data 7 to 0 ? ? assert 4n + 3 1 data 7 to 0 ? ? ? assert word 4n 1 ? ? data 15 to 8 data 7 to 0 assert assert 4n + 2 1 data 15 to 8 data 7 to 0 ? ? assert assert longword 4n 1 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert table 11.13 16-bit external device/li ttle-endian access and data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte 2n 1 ? ? ? data 7 to 0 assert 2n + 1 1 ? ? data 7 to 0 ? assert word 2n 1 ? ? data 15 to 8 data 7 to 0 assert assert longword 4n 1 ? ? data 15 to 8 data 7 to 0 assert assert 4n + 2 2 ? ? data 31 to 24 data 23 to 16 assert assert
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 356 of 1286 rej09b0158-0100 table 11.14 8-bit external device/little-e ndian access and data alignment operation data bus strobe signals access size address no. d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we2 we1 we0 byte n 1 ? ? ? data 7 to 0 assert word 2n 1 ? ? ? data 7 to 0 assert 2n + 1 2 ? ? ? data 15 to 8 assert longword 4n 1 ? ? ? data 7 to 0 assert 4n + 1 2 ? ? ? data 15 to 8 assert 4n + 2 3 ? ? ? data 23 to 16 assert 4n + 3 4 ? ? ? data 31 to 24 assert
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 357 of 1286 rej09b0158-0100 11.5.2 areas (1) area 0 for area 0, physical addre ss bits 28 to 26 are 000. the interfaces that can be se t for this area are the sram, burst rom and mpx interfaces. a bus width of 8, 16, or 32 bits is selectable with external pins mode4 and mode3 at a power- on reset. for details, see section 11.3.2, memory bus width. when area 0 is accessed, the cs0 signal is asserted. in the case where the sram interface is set, the rd signal, which can be used as oe, and write control signals we0 to we3 are asserted. for the number of bus cycles, 0 to 25 wait cy cles inserted by cs0w cr can be selected. when the burst rom interface is used, a burst pitc h number in the range of 0 to 7 is selectable with bits bw2 to bw0 in cs0bcr. any number of wait cycles can be inserted in each bus cycle th rough the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) when the burst rom interface is used, the number of transfer cycles for a burst cycle is selected from a range of 2 to 9 according to the number of wait cycles. the setup time and hold time (cycle number) of the address and cs0 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs0wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. (2) area 1 for area 1, physical addre ss bits 28 to 26 are 001. the interfaces that can be set for this area are the sram, burs t rom, mpx and byte-control sram interfaces. a bus width of 8, 16, or 32 bits is selectable with bits sz in cs1bcr. when th e mpx interface is used, a bus width of 32 bits should be selected through bits sz in cs1bcr. when using the byte- control sram interface, select a bus width of 16 or 32 bits. when area 1 is accessed, the cs1 signal is asserted.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 358 of 1286 rej09b0158-0100 in the case where the sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we3 are asserted. for the number of bus cycles, 0 to 25 wait cycles inserted by cs1wcr can be selected. when the burst rom interface is used, a burst pitc h number in the range of 0 to 7 is selectable with bits bw2 to bw0 in cs1bcr. any number of wait cycles can be inserted in each bus cycle through the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) the setup time and hold time (cycle number) of the address and cs1 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs1wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. (3) area 2 for area 2, physical addre ss bits 28 to 26 are 010. the interfaces that can be se t for this area are the sram, burst rom, mpx and ddr-sdram interfaces. when the sram interface is used, a bus width of 8, 16, or 32 bits is selectable with bits sz in cs2bcr. when the mpx inte rface is used, a bus width of 32 bits should be selected through bits sz in cs2bcr. when area 2 is accessed, the cs2 signal is asserted (ex cept for ddr-sdram area). in the case where the sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we3 are asserted. for the number of bus cycles, 0 to 25 wait cycles inserted by cs2wcr can be selected. any number of wait cycles can be inserted in each bus cycle th rough the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) the setup time and hold time (cycle number) of the address and cs2 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs2wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. when using area 2 for the ddr- sdram interface, set the areasel bit in mmselr. then the cs2 signal is not asserted. when the ddr-sdram is used, see section 12, ddr-sdram interface (ddrif).
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 359 of 1286 rej09b0158-0100 (4) area 3 for area 3, physical addre ss bits 28 to 26 are 011. this area is used only for the ddr-sdram inte rface. for details, see section 12, ddr-sdram interface (ddrif). (5) area 4 for area 4, physical addre ss bits 28 to 26 are 100. the interfaces that can be set fo r this area are the sram, burst rom, mpx , byte control sram, ddr-sdram and pci local bus interfaces. a bus width of 8, 16, or 32 bits is selectable with bits sz in cs4bcr. when th e mpx interface is used, a bus width of 32 bits should be selected through bits sz1 and sz0 in cs4bcr. when the byte control sram interface is used, select a bus width of 16 or 32 bits. for details, see section 11.3.2, memory bus width. when area 4 is accessed, the cs4 signal is asserted (except for ddr-sdram and pci areas). in the case where the sram interface is set, the rd signal, which can be used as oe , and write control signals we0 to we3 are asserted. for the number of bus cycles, 0 to 25 wait cycles inserted by cs4wcr can be selected. any number of wait cycles can be inserted in each bus cycle through the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) the setup time and hold time (cycle number) of the address and cs4 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs4wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. when using area 4 as the ddr-sdram or pci local bus interface, set the areasel bit in mmselr. then the cs4 signal is not asserted. when th e ddr-sdram or pci is used, see section 12, ddr-sdram interface (ddrif) or sec tion 13, pci controller (pcic), respectively. (6) area 5 for area 5, physical addre ss bits 28 to 26 are 101. the interfaces that can be set for this area are the sram, burs t rom, pcmcia, mpx, and ddr- sdram interfaces.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 360 of 1286 rej09b0158-0100 when the sram or burst rom interface is used, a bus width of 8, 16, or 32 bits is selectable with bits sz in cs5bcr. when the mpx interface is us ed, a bus width of 32 bits should be selected through bits sz in cs5bcr. when the pcmcia inte rface is used, select a bus width of 8 or 16 bits with sz in cs5bcr. for details, see section 11.3.2, memory bus width. when area 5 is accessed, the cs5 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 are asserted. while the pcmcia interface is used, the ce1a and ce2a signals, the rd signal, (which can be used as oe ), the we0 , we1 , we2 , and we3 signals, (which can be used as, reg , we , iord , and iowr , respectively) are asserted. for the number of bus cycles, 0 to 25 wait cycles inserted by cs5wcr can be selected. any number of wait cycles can be inserted in each bus cycle th rough the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) the setup time and hold time (cycle number) of the address and cs5 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs5wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. for the pcmcia interface, the setup time of ad dresses to the read/wri te strobe signals ( ce1a and ce2a ) can be specified within a range from 0 to 15 cycles through bits teda/b2 to teda/b0 and teda/b to teha/b in cs5pcr. in addition, the number of wait cy cles can be specified within a range from 0 to 50 cycles through bits pcwa/b1 and pcwa/b0. the number of wait cycles specified by cs5pcr is added to the value specified by iw3 to iw0 in cs5wcr or pciw3 to pciw0 in cs5pcr. when using area 5 for the ddr- sdram interface, set the areasel bit in mmselr. then the cs5 signal is not asserted. when the ddr-sdram is used, see section 12, ddr-sdram interface (ddrif). (7) area 6 for area 6, physical addre ss bits 28 to 26 are 110. the interfaces that can be se t for this area are the sram, mpx, burst rom, and pcmcia interfaces. when the sram or burst rom is used, a bus width of 8, 16, or 32 bits is selectable with bits sz in cs6bcr. when the mpx interface is used, a bus width of 32 bi ts should be selected through bits sz in cs6bcr. when the pcmc ia interface is used, select a bu s width of 8 or 16 bits with sz in cs6bcr. for details, see section 11.3.2, memory bus width.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 361 of 1286 rej09b0158-0100 when area 6 is accessed, the cs6 signal is asserted. in addition, the rd signal, which can be used as oe , and write control signals we0 to we3 are asserted. while the pcmcia interface is used, the ce1b and ce2b signals, the rd signal (which can be used as oe ), and the we0 , we1 , we2 , and we3 signals (which can be used as reg , we , iord , and iowr , respectively) are asserted. for the number of bus cycles, 0 to 25 wait cycles inserted by cs6wcr can be selected. any number of wait cycles can be inserted in each bus cycle th rough the external wait pin ( rdy ). (when the insert number is 0, the rdy signal is ignored.) the setup time and hold time (cycle number) of the address and cs6 signals to the read and write strobe signals can be set within a ra nge of 0 to 7 cycles by cs6wcr. the bs hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more. for the pcmcia interface, the setup time of ad dresses to the read/wri te strobe signals ( ce1b and ce2b ) can be specified within a range from 0 to 15 cycles by bits teda/b2 to teda/b0 and teha/b2 to teha/b0 in cs6pcr. in addition, the nu mber of wait cycles can be specified within a range from 0 to 50 cycles by bits pcwa/b 1 and pcwa/b0. the number of wait cycles specified by cs6pcr is added to the value speci fied by iw3 to iw0 in cs6wcr or pciw3 to pciw0 in cs6pcr. 11.5.3 sram interface (1) basic timing the strobe signals for the sram interface of this lsi are output primarily based on the sram connection. figure 11.4 shows the basic timing of the sram interface. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycl e to indicate the start of a bus cycle. the csn signal is asserted at the rising edge of th e clock in the t1 state, and negated at the next rising edge of the clock in the t2 state. ther efore, there is no negation period in the case of access at minimum pitch. during reading, specification of an access size is not needed. the output of an access address on the address pins (a25 to a0) is correct, however, since the access size is not specified, 32-bit data is always output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use. during writing, only the we signal corresponding to the byte to be written is asserted. for details, see section 11.5.1, endian/access size and data alignment. in 32-byte transfer, a total of 32 bytes are transferred continuously according to the bus width set. the first access is performed on the data for whic h there was an access request, and the remaining
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 362 of 1286 rej09b0158-0100 accesses are performed in wraparound method accor ding to the set bus width. the bus is not released during this transfer. t 1 clkout a25 to a0 csn r/ w rd d31 to d0 (read) we d31 to d0 (write) bs t 2 rdy dack figure 11.4 basic timi ng of sram interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 363 of 1286 rej09b0158-0100 figures 11.5 to 11.7 show examples of the connection to sram with data width of 32, 16, and 8 bits. ... ... ... ... ... a16 a0 cs oe i/o7 i/o0 we ... ... ... ... a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 sh7780 128 k 8-bit sram ... a16 a0 cs oe i/o7 i/o0 we ... ... ... ... ... ... a16 a0 cs oe i/o7 i/o0 we ... ... ... ... a16 a0 cs oe i/o7 i/o0 we ... ... ... ... ... ... figure 11.5 example of 32-bit data-width sram connection
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 364 of 1286 rej09b0158-0100 a16 a0 cs oe i/o7 i/o0 we a17 sh7780 a1 csn rd d15 d8 we1 d7 d0 we0 a16 a0 cs oe i/o7 i/o0 we ... ... ... ... ... ... ... ... ... ... ... ... ... ... 128 k 8-bit sram figure 11.6 example of 16-bit data-width sram connection
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 365 of 1286 rej09b0158-0100 a16 a0 csn rd d7 d0 we0 a16 a0 cs oe i/o7 i/o0 we ... ... ... ... ... ... ... ... sh7780 128 k 8-bit sram figure 11.7 example of 8-bi t data-width sram connection
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 366 of 1286 rej09b0158-0100 (2) wait cycle control wait cycle insertion for the sram interface can be controlled by csnwcr. if the iw bits for each area in csnwcr is not 0, a software wait is in serted in accordance with the wait-control bits. for details, see section 11.4.4, csn wait control register (csnwcr). a specified number of tw cycles is inserted as wait cycles in accordance with the csnwcr setting. the insertion timing of the wait cycle is shown in figure 11.8. t 1 clkout a25 to a0 csn r/ w rd d31 to d0 (read) we d31 to d0 (write) bs t w t 2 rdy dack figure 11.8 sram interface wa it timing (software wait only)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 367 of 1286 rej09b0158-0100 when software wait insertion is specified by csnwcr, the external wait input signal ( rdy ) is also sampled. the rdy signal sampling timing is shown in figure 11.9, where a single wait cycle is specified as a software wait. the rdy signal is sampled at the transition from the tw state to the t2 state. therefore, the assertion of the rdy signal has no effect in the t1 cycle or in the first tw cycle. the rdy signal is sampled on the rising edge of the clock. t 1 clkout a25 to a0 csn r/ w rd (read) d31 to d0 (read) we (write) d31 to d0 (write) bs t w t we t 2 rdy dack figure 11.9 sram in terface wait timing (wait cycle insertion by rdy signal, rdy signal is synchronous input)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 368 of 1286 rej09b0158-0100 (3) read-strobe negate timing when the sram interface is used, the negation timing of the strobe signal during a read operation can be specified through the rdspl bit in csnbcr. for details of settings, see section 11.4.3, csn bus control register (csnbcr). clear the rdspl bit to 0, when using a byte control sram.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 369 of 1286 rej09b0158-0100 clkout t as1 t 1 t s1 t w t w t w t w t 2 t h1 t h2 t ah1 notes: 1. when csnbcr rdspl is set to 1. 2. when csnwcr.bsh is set to 1. a25 to a0 csn r/ w rd (read) d31 to d0 (read) we (write) d31-d0 (ads = 0) (write) d31-d0 (ads = 1 to 7) (write) bs ts1: csn assertion- rd assertion delay cycle ( rd setup cycle) csnwcr.rds (0 to 7 cycles) th1,th2: rd negation- csn negation delay cycle ( rd hold cycle) csnwcr.rdh (0 to 7 cycles) tas1: address setup cycle csnwcr.ads (0 to 7 cycles) tw: insert wait cycle csnwcr.iw (0 to 25 cycles) tah1: address hold cycle csnwcr.adh (0 to 7 cycles) ts1: csn assertion- we assertion delay cycle ( we setup cycle) csnwcr.wts (0 to 7 cycles) tas1: address setup cycle csnwcr.ads (0 to 7 cycles) tw: insert wait cycle csnwcr.iw (0 to 25 cycles) clkout clkout * 1 tah1: address hold cycle csnwcr.adh (0 to 7 cycles) * 2 th1,th2: we negation- csn negation delay cycle ( we hold cycle) csnwcr.wth (0 to 7 cycles) figure 11.10 sram interfa ce wait timing (read-strobe negate timing setting)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 370 of 1286 rej09b0158-0100 11.5.4 burst rom (clock asynchronous) interface setting the type bit in csnbcr (n = 0 to 2 and 4 to 6) to 010 allows a burst rom (clock asynchronous memory) to be co nnected to areas 0 to 2 and 4 to 6. the burst rom interface provides high-speed access to ro m that has a burst access functi on. the burst access timing of burst rom is shown in figure 11.11. the wait cy cle is set to 0 cycle. although the access is similar to that of the sram interface, only the ad dress is changed when the first cycle ends and then the next access is started. when 8-bit ro m is used, the number of consecutive accesses can be set as 4, 8, 16, or 32 through bits bst2 to bst0 in csnbcr (n = 0 to 2 and 4 to 6). similarly, when 16-bit rom is used, 4, 8 or 16 accesses can be set; when 32-bit rom is used, 4 or 8 accesses can be set. the rdy signal is always sampled when one or more wait cycles are set. even when no wait is specified in the burst rom settings, two acce ss cycles are inserted in the second and subsequent accesses as shown in figure 11.12. a writing operation for this interface is performed in the same way as for the sram interface. in a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. the first access is performed on the data for which there was an access request, and the remaining accesses are performed in wraparound meth od according to the se t bus width. the burst access is stopped once (negate the rd ) at the address boundary which is a bus width (csnbcr.sz) x burst length (csnbcr.bst) addr ess and then the access is resumed by the settings of csnwcr. the bus is not released during this transfer. figure 11.13 shows the timing chart when the burst rom is used and setup/hold is specified by csnwcr.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 371 of 1286 rej09b0158-0100 t 1 t b1 t b2 t b1 t b2 t b1 t b2 t 2 clkout a25 to a5 a4 to a0 csn r/ w rd d31 to d0 (read) bs rdy figure 11.11 burst rom basic timing t 1 t we t b2 t b1 t w t b2 t w t w t b1 t b2 t w t 2 t b1 clkout a25 to a5 a4 to a0 csn r/ w rd d31 to d0 (read) bs rdy figure 11.12 burst rom wait timing
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 372 of 1286 rej09b0158-0100 t as1 t 1 t s1 t b1 t b2 t b2 t b1 t b2 t b1 t 2 t h1 t ah1 clkout a25 to a5 a4 to a0 csn r/ w rd d31 to d0 dackn * (read) bs rdy note: * when csnbcr rdspl is set to 1. figure 11.13 burst rom wait timing 11.5.5 pcmcia interface areas 5 and 6 can be set to the ic memory card interface or i/o car d interface, which is stipulated in jeida specification version 4.2 (pcmcia 2.1), by setting the type bits in cs5bcr and cs6bcr. since operation in big-endian mode is not explicitly stipulated in the jeida/pcmcia standard, this lsi supports the pcmcia in terface only in little-endian mode through little-endian mode setting. the pcmcia interface can select the space prop erty from among 8-bi t common memory, 16-bit common memory, 8- bit attribute memory, 16-bit attribut e memory, 8-bit i/o space, 16-bit i/o space, dynamic i/o bus sizing, and ata compleme nt mode by dependi ng on the setting of saa[2:0] and sab[2:0] bits in csnpcr. when the first half area is accessed, bit iw in csnwcr (n = 5 or 6) and bits pcwa, teda, and teha in csnpcr (n = 5 or 6) are selected. when the second half area is accessed, bit iw in csnwcr (n = 5 or 6) and bits pcwb, tedb, and tehb in csnpcr (n = 5 or 6) are selected.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 373 of 1286 rej09b0158-0100 bits pcwa/b1 and pcwa/b0 can be used to set th e number of wait cycles to be inserted in a low-speed bus cycle as 0, 15, 30, or 50. this value is added to the number of inserted wait cycles specified by iw bit in csnwcr or pciw bit in csnpcr. bit teda/b (with a setting range from 0 to 15) can be used to ensure the setup times of the address, ce1a ( cs5 ), ce1b ( cs6 ), ce2a , ce2b and reg to the rd and we1 signals. bits teha/b (with a setting range from 0 to15) can be used to ensure the hold times of the address, ce1a ( cs5 ), ce1b ( cs6 ), ce2a , ce2b , and reg to the rd and we1 signals. bits iww, iwrwd, iwrws, iwrrd, and iwrrs in the cs5 bus control register (cs5bcr) or cs6 bus control register (cs6bcr) are used to se t the number of idle cycles between cycles. the selected number of wait cycles between cycles depends only on the area to be accessed (area 5 or 6). when area 5 is accessed, bits iww, iwrw d, iwrws, iwrrd, and iwrrs in cs5bcr are selected, and when area 6 is accessed, bits iww, iwrwd, iwrws, iwrrd, and iwrrs in cs6bcr are selected. in 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wraparound method accor ding to the set bus width. the bus is not released during this transfer. ata complement mode is to access the ata device register connected to this lsi. the device control register, alternate status register, data register, and da ta port can be accessed in ata complement mode. to access the device control register and alternat e status register, use a cpu byte access (do not use a dma transfer), and to access the data register, use the cpu word access (do not use a dma transfer). when a cpu byte access is executed, ce1x is negated and ce2x is asserted (x = a, b). when a cpu word access is executed, ce1x is asserted and ce2x is negated. to access the data port use a dma transfer. th e setting example of the dmac is external request, burst mode, level detection, overrun 0, dack output to the corr espondent pcmcia connected area. when dm a transfer of an ata complement mode area is executed, neither ce1x nor ce2x is asserted. set the dackbst bit in bcr of the corresponding dma transfer channel to 1, so th at the corresponding dack signal is asserted from the beginning to the end of the dma transfer cycle. specify the number of wait cycl es between accesses as 0 for the dack assertion area when setting the dma transfer size to 16-byte. afte r the dma burst transfer that dackbst was enabled has finished, set the dackbst bit to 1 again before starting the next dma burst transfer.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 374 of 1286 rej09b0158-0100 cexx dack cexx dack (a) io card interface dackbst invalid (b) ata complement mode dackbst valid note: number of dma transfer times: 4, dma transfer size: word (16-bit) xx = 1a, 1b, 2a, 2b figure 11.14 cexx and dack output of ata complement mode in dma transfer figure 11.15 shows an example of pcmcia card connection to this lsi. to enable hot insertion of pcmcia cards (i.e., insertion or removal while system power is being su pplied), a three-state buffer must be connected between this lsi bus interface and the pcmcia cards.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 375 of 1286 rej09b0158-0100 table 11.15 relationship between addre ss and ce when usin g pcmcia interface bus (bits) read/ write access (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15 to d8 d7 to d0 8 read 8 even ? h l l invalid read data odd ? h l h invalid read data 16 even first h l l invalid lower read data even second h l h invalid upper read data odd ? ? ? ? ? ? write 8 even ? h l l invalid write data odd ? h l h invalid write data 16 even first h l l invalid lower write data even second h l h invalid upper write data odd ? ? ? ? ? ? 16 read 8 even ? h l l invalid read data odd ? l h h read data invalid 16 even ? l l l upper read data lower read data odd ? ? ? ? ? ? write 8 even ? h l l invalid write data odd ? l h h write data invalid 16 even ? l l l upper write data lower write data odd ? ? ? ? ? ? read 8 even l ? h l l invalid read data odd l ? l h h read data invalid dynamic bus sizing * 2 16 even l ? l l l upper read data lower read data odd l ? ? ? ? ? ? write 8 even l ? h l l invalid write data odd l ? l h h write data invalid 16 even l ? l l l upper write data lower write data odd l ? ? ? ? ? ? read 8 even h ? h l l invalid read data odd h first l h h invalid invalid odd h second h l l invalid read data 16 even h first l l l invalid lower read data even h second h l h invalid upper read data odd h ? ? ? ? ? ?
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 376 of 1286 rej09b0158-0100 bus (bits) read/ write access (bits) * 1 odd/ even iois16 access ce2 ce1 a0 d15 to d8 d7 to d0 write 8 even h ? h l l invalid write data odd h first l h h invalid write data dynamic bus sizing * 2 odd h second h l h invalid write data 16 even h first l l l upper write data lower write data even h second h l h invalid upper write data odd h ? ? ? ? ? ? 8 even ? l h l invalid read data odd ? ? ? ? ? ? ata comple- ment mode 16 even ? h l l upper read data lower read data read (does not output dack) odd ? ? ? ? ? ? 8 even ? l h l invalid write data odd ? ? ? ? ? ? 16 even ? h l l upper write data lower write data write (does not output dack) odd ? ? ? ? ? ? 8 even ? h h l invalid read data odd ? h h l read data invalid 16 even ? h h h upper read data lower read data read (outputs dack) odd ? ? ? ? ? ? 8 even ? h h l invalid write data odd ? h h l write data invalid 16 even ? h h h upper write data lower write data write (outputs dack) odd ? ? ? ? ? ? [legend] : don't care l : low level h : high level notes: 1. in 32-bit/64-bit/16-byte/32-byte trans fer, the addresses are aut omatically incremented by the bus width, and then above accesses are repeated until the transfer data size is reached. 2. pcmcia i/o card interface only.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 377 of 1286 rej09b0158-0100 g a25 to a0 d15 to d0 cd1, cd2 ce1 g ce2 oe we / pgm ( iord ) ( iowr ) ( iois16 ) wait a25 to a0 d15 to d0 cd1, cd2 ce1 ce2 oe we / pgm wait a25 to a0 d15 to d0 r/ w ce2b ce2a rd we1 ce1b /( cs6 ) ce1a /( cs5 ) iord iowr rdy iois16 g dir d7 to d0 d15 to d8 d7 to d0 d15 to d8 g dir g g g dir g dir reg reg reg pc card (memory, i/o) pc card (memory) card detection circuit card detection circuit sh7780 figure 11.15 example of pcmcia interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 378 of 1286 rej09b0158-0100 (1) memory card interface basic timing figure 11.16 shows the basic timing for the pcmcia memory card interface, and figure 11.17 shows the wait timing for the pc mcia memory card interface. clkout t pcm1 t pcm2 a25 to a0 cexx r/ w d15 to d0 (read) d15 to d0 (write) rd (read) we1 (write) bs rdy dack reg ( we0 ) figure 11.16 basic timing for pcmcia memory card interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 379 of 1286 rej09b0158-0100 clkout t pcm0 a25 to a0 r/ w cexx rd we1 bs rdy reg ( we0 ) (read) d15 to d0 (read) d15 to d0 (write) (write) dack t pcm0w t pcm1 t pcm1w t pcm1we t pcm2 t pcm2w figure 11.17 wait timing for pcmcia me mory card interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 380 of 1286 rej09b0158-0100 (2) i/o card interface timing figures 11.18 and 11.19 s how the timing for the pcmc ia i/o card interface. when accessing a pcmcia card via the i/o card interface, it is possibl e to perform dynamic sizing of the i/o bus width using the iois16 pin. with the 16-bit bus width selected, if the iois16 signal is high during the word-size i/o bus cycle, the i/o port is recognized as eight bits in bus width. in this case, a data access for only eight bits is performed in the i/o bus cycle being executed, and this is automatically followed by a data access for the remaining eight bits. dynamic bus sizing is also performed fo r byte-size access to address 2n + 1. figure 11.20 shows the basic timing for dynamic bus sizing. clkout t pci1 t pci2 a25 to a0 r/ w cexx iord (read) d15 to d0 (read) iowr (write) d15 to d0 (write) bs dack reg ( we0 ) figure 11.18 basic timing fo r pcmcia i/o card interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 381 of 1286 rej09b0158-0100 clkout a25 to a0 r/ w cexx iord (read) iowr (write) dack d15?d0 (read) d15 to d0 (write) bs rdy iois16 t pci0 t pci0w t pci1 t pci1we t pci1w t pci2 t pci2w reg ( we0 ) figure 11.19 wait timing fo r pcmcia i/o card interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 382 of 1286 rej09b0158-0100 t pci t pci0 t pci1w t pci2 t pci2w t pci0 t pci t pci2 t pci1w t pci2w clkout a25 to a1 a0 r/ w iord ( we2 ) (read) iowr ( we3 ) (write) d15 to d0 (write) d15 to d0 (read) bs iois16 cexx reg ( we0 ) rdy dack figure 11.20 dynamic bus sizing ti ming for pcmcia i/ o card interface
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 383 of 1286 rej09b0158-0100 11.5.6 mpx interface when both the mode4 and mode3 pins are set to 0 at a power-on reset by the preset pin, the mpx interface is selected for area 0. the mpx interf ace is selected for areas 1, 2, and 4 to 6 by the mpx bit in cs1bcr, cs2 bcr, and cs4bcr to cs6bcr. th e mpx interface provides an address/data multiplex-type bus protocol and facilitates connection with external memory controller chips using an address/data multiplex-type 32-bit single bus. a bus cycle consists of an address phase and a data phase. address informatio n is output on d25 to d0 and the access size is output on d31 to d29 in the address phase. the bs signal is asserted for one cycle to indicate the address phase. the csn signal is asserted at the rising edge in tm1 and is negated after the end of the last data transfer in the data phase. therefore, a negation cycle does not occur in the case of minimum pitch access. the frame signal is asserted at the rising edge in tm1 and negated at the start of the last data tr ansfer cycle in the data phase. ther efore, an external device for the mpx interface must internally store th e address information and access size output in the address phase and perform data input/output for the data phase. for details, see section 11.5.1, endian/access size and data alignment. values output on address pins a25 to a0 are not guaranteed. in 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed according to the set bus width. if the access size is larger than the bus width in this case, a burst access with continui ng multiple data cycle occurs after one address output. the bus is not released during this transfer. table 11.16 relationship between d31 to d29 and access size in address phase d31 d30 d29 access size 0 0 0 byte 1 word 1 0 longword 1 unused 1 x x 32-byte burst [legend] x: don't care
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 384 of 1286 rej09b0158-0100 clkout csn bs rd / frame r/ w d31 to d0 rdy sh7780 mpx device clk cs bs frame we i/o31 to i/o0 rdy figure 11.21 example of 32-bit data width mpx connection the mpx interface timing is shown below. when the mpx interface is used for ar eas 1, 2, and 4 to 6, a bus size of 32 bits should be specified by csnbcr. in wait control, either waits by csnwcr or waits by the rdy pin can be inserted. in a read, one wait cycle is automatically inserted after address output, even if csnwcr is cleared to 0. t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1 rdy dack d0 a figure 11.22 mpx interface timi ng 1 (single read cycle, iw = 0, no external wait)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 385 of 1286 rej09b0158-0100 t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1we t md1 rdy dack d0 a figure 11.23 mpx interface timing 2 (single read, iw = 0, one external wait inserted) t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1 rdy dack d0 a figure 11.24 mpx interface timi ng 3 (single write cycle, iw = 0, no external wait)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 386 of 1286 rej09b0158-0100 t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1we t md1 rdy dack d0 a figure 11.25 mpx interface timi ng 4 (single write cycle, iw = 1, one external wait inserted) t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1 t md2 t md3 t md4 t md5 t md6 t md7 t md8 rdy dack d2 d3 d4 d6 d7 d8 d5 d1 a figure 11.26 mpx interface timing 5 (burst read cycle, iw = 0, no external wait, 32-byte data transfer)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 387 of 1286 rej09b0158-0100 t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1 t md2we t md2 t md3 t md7 t md8we t md8 rdy dack d7 d8 d2 d3 d1 a figure 11.27 mpx interface timing 6 (burst read cycle, iw = 0, external wait control, 32-byte data transfer) t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1 t md2 t md3 t md4 t md5 t md6 t md7 t md8 rdy dack d1 d2 d3 d4 d5 d6 d7 d8 a figure 11.28 mpx interface timing 7 (burst write cycle, iw = 0, no external wait, 32-byte data transfer)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 388 of 1286 rej09b0158-0100 t m1 clkout rd / frame csn r/ w d31 to d0 bs t md1w t md1 t md2we t md2 t md3 t md7 t md8we t md8 rdy dack d3 d2 d1 d7 d8 a figure 11.29 mpx interface timing 8 (burst write cycle, iw = 1, external wait control, 32-byte data transfer)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 389 of 1286 rej09b0158-0100 11.5.7 byte contro l sram interface the byte control sram interface is a memory interface that outputs a byte-select strobe ( we ) in both read and write bus cycles. this interface has 16-bit data pins and can be connected to sram having an upper byte select strobe and lower select strobe functions, such as ub and lb. areas 1 and 4 can be specified as a byte control sram interface. however, when these areas are set to the mpx interface, the mpx interface has priority. the write timing for the byte control sram inte rface is identical to that of a normal sram interface. in read operations, on the other hand, the we pin timing is different. in a read access, only the we signal for the byte being read is asserted. assertion is synchronized with the falling edge of the clkout clock in the same way as for the we signal, while negation is synchronized with the rising edge of the clkout clock in the same way as for the rd signal. in 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. the first access is performed on the data for whic h there was an access request, and the remaining accesses are performed in wraparound method accor ding to the set bus width. the bus is not released during this transfer. figure 11.30 shows an example of a byte control sram connection, and figures 11.31 to 11.33 show examples of byte-co ntrol sram read cycles. a17 to a2 csn rd r/ w sh7780 64 k 16-bit sram d15 to d0 we1 we0 a15 to a0 cs oe we i/o15 to i/o0 ub lb a15 to a0 cs oe we i/o15 to i/o0 ub lb d31 to d16 we3 we2 figure 11.30 example of 32-bit data-width byte-control sram
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 390 of 1286 rej09b0158-0100 t 1 t 2 clkout a25 to a0 csn r/ w rd d31 to d0 (read) bs dack rdy we figure 11.31 byte-control sr am basic read cycle (no wait)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 391 of 1286 rej09b0158-0100 t 1 t w t 2 clkout a25 to a0 csn r/ w rd d31 to d0 (read) bs dack rdy we figure 11.32 byte-control sram basic read cycle (one int ernal wait cycle)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 392 of 1286 rej09b0158-0100 t 1 t w t we t 2 clkout a25 to a0 csn r/ w rd d31 to d0 (read) bs dack rdy we figure 11.33 byte-control sram basic read cycle (one internal wait + one external wait)
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 393 of 1286 rej09b0158-0100 11.5.8 wait cycles between accesses a problem associated with higher operating frequencie s for external memory bu ses is that the data buffer turn-off after completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and re sulting in lower reliabil ity or malfunctions. to prevent this problem, this module provides a data collision prevention function. it stores the preceding access area and the type of read/write and inserts a wait cycle before the access cycle if there is a possibility of a bus collision when the next access is started. the proces s for wait cycle insertion consists of inserting idle cycles betw een the access cycles as shown in sect ion 11.4.3, csn bus control register (csnbcr). if bits iww, iwrwd, iwrws, iwrrd and iwrrs in csnbcr (n = 0 to 2 and 4 to 6) are used to set the number of idle cycles between accesses, the number of inserted idle cycles is only the specifie d number of idle cycles minus the number of idle cycles specified by the bits. when bus arbitration is performed, the bus is rel eased after wait cycles are inserted between the cycles. when a dma transfer is performed, wait cycles are inserted as set in csnbcr idle cycle bits. when access the mpx interface area continuously afte r read access, 1 wait cycle is inserted even if set the wait cycle to 0. when the access size is 8-byte or 16-byte, wa it cycles are inserted every 4-byte access.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 394 of 1286 rej09b0158-0100 t 1 clkout csm csn a25 to a0 bs r/ w rd d31 to d0 t 2 t wait t 1 t 2 t wait t 1 t 2 area m space read area m - n access wait specification m n, (m, n) = 0 to 2, 4 to 6 area n inter-access wait specification area n space read area n space write iwrrd iwrws figure 11.34 wait cycl es between access cycles
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 395 of 1286 rej09b0158-0100 11.5.9 bus arbitration the lbsc is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. in normal operation, the bus is held by the lbsc (bus master), and is released to another device in response to a bus request. it is possible to connect an external device that issues bus requests. in the following description, an external device that i ssues bus requests is also referred to as a slave. the sh7780 has three internal bu s masters: the cpu, dmac, and pcic. in addition to these are bus requests from external devices (highest priority). if requests occur simultaneously, the lru method is used to decide the request priority. the initial priority order is : cpu > dmac > pcic. to prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated befo re the bus is released. when mastership of the bus is received, also, bus contro l signals begin driving the bus from the negate d state. since signals are driven to the same value by the mast er and slave exchanging the bus, output buffer collisions can be avoided. by turning off the output buffer on the side releasing the bus, and turning on the output buffer on th e side receiving the bus, simulta neously with respect to the bus control signals, it is possible to eliminate the signal high-impedance period. it is not necessary to provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect operation due to external noise in the high-impedance state. bus transfer is executed between bus cycles. when the bus release request signal ( breq ) is asserted, the lbsc releas es the bus as soon as the currently executin g bus cycle ends, and outputs the bus use permission signal ( back ). however, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing long word access to 8-bit bus width memory) or during a 32-byte transf er such as a cache fill or write-b ack. in addition, bus release is not performed between read and write cycles duri ng execution of a tas in struction, or between read and write cycles in dma dual a ddress mode of the bus locked. when breq is negated, back is negated and use of the bus is resumed. as the cpu is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the sh7780. when writing from the cpu, an external write cycle is generated when write-through has been set for the cache in the sh 7780, or when an access is made to a cache-off area. there is consequently a delay until the bus is returned.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 396 of 1286 rej09b0158-0100 clkout breq back csn rd we a25 to a0 bs d31 to d0 (write) r/ w hiz hiz hiz hiz hiz hiz hiz master access master access slave access asserted for least 2 cycles negated within 2 cycles figure 11.35 arbitration sequence
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 397 of 1286 rej09b0158-0100 11.5.10 bus release and acquire sequence the lbsc holds the bus itself unless it receives a bus request. on receiving an assertion (low le vel) of the bus request signal ( breq ) from off-chip, the lbsc releases the bus and asserts (drives lo w) the bus use permission signal ( back ) as soon as the currently executin g bus cycle ends. on receiving the breq negation (high level) indicating that the slave has released the bus, th e lbsc negates (drives high) the back signal and resumes use of the bus. the actual bus release sequence is as follows. first, the bus use permission signal is asserted in synchronization with the rising edge of the clock. the address bus and data bus go to the high-impedance state in synchronization from next rising edge of the clock after this back assertion. at the same time, the bus control signals ( bs , csn , we , rd , r/ w , ce2a , and ce2b ) go to the high-impedance stat e. these bus control signals are negated no later than one cycle before going to high-impedance. bus request signal sampling is performed on the rising edge of the clock. the sequence for re-acquiring the bu s from the slave is as follows. as soon as breq negation is detected on the rising edge of the clock, back is negated and bus control signal driving is started. driving of the address bus and data bus starts at the next rising edge of an in-phase clock. the bus control si gnals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. in order to reacquire the bus and start execution of bus access, the breq signal must be negated for at least two cycles. using the lckn bit in chcr of the dmac, it is po ssible to restrain the bus release in the cycle between read and write access. if a dma transfer is executed for the space that the source and destinat ion address are in the lbsc space and the lckn bit in chcr is cleared to 0, the bus is not released in the cycle between read and write accesses ev en if the bus release signal ( breq ) is asserted.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 398 of 1286 rej09b0158-0100 if a dma transfer is executed for the space that the source address is in the lbsc space and the destination address is out of the lbsc space and the lckn bit in chcr is cleared to 0, the bus is not released after the dma write access is ended even if the bus release signal ( breq ) is asserted. and then execute read or write access to any addr ess of the lbsc space fro m the cpu, the bus is released after the access. this procedure does not need when the lckn bit is set to 0. if a dma transfer is executed for the space that the source address is out of the lbsc space and the destination addres s is in the lbsc space and the lckn bit in chcr is cl eared to 0, the bus is released in the cycle between read access and write access. csn breq back dmac chcr lckn = 0, source address: lbsc space, destination address: lbsc space dma read access to the lbsc space dma write access to the lbsc space csn breq back dmac chcr lckn = 0, source address: lbsc space, destination address: not lbsc space dma read access to the lbsc space cpu access to the lbsc space dma write access to other than the lbsc space dma read access to other than the lbsc space csn breq back dmac chcr lckn = 0, source address: not lbsc space, destination address: lbsc space dma write access to the lbsc space figure 11.36 example of the bus releas e restraint by the dmac chcr lckn bit
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 399 of 1286 rej09b0158-0100 11.5.11 cooperation between master and slave to enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. when designing an application system that includes the sh7780, all control, including initialization, and low power consumption control, are supposed to be carried out by the sh7780. in a power-on reset, the sh7780 will not accept bus requests from the slave until the breq enable bit (bcr.breqen) is set to 1. to ensure that the slave processor does not access memory requiring initialization before use, write 1 to the breq enable bit only after the sh7780 has performed the initialization.
section 11 local bus state controller (lbsc) rev.1.00 dec. 13, 2005 page 400 of 1286 rej09b0158-0100
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 401 of 1286 rej09b0158-0100 section 12 ddr-sdram interface (ddrif) the ddr-sdram interface (ddrif) is an inte rface for the control of ddr-sdram. the ddrif supports ddr320- and ddr266-sdram. 12.1 features ? the data bus width of the ddrif is 32 bits ? supports ddr-sdram self-refreshing ? supports ddr320 (160 mhz) or ddr266 (133 mhz) ? efficient data transfer via the superhyway bus (internal bus) ? supports a four-bank ddr-sdram ? supports a burst length of two ? connectable memory sizes: 256 mbits, 512 mbits, 1 gbit, and 2 gbits address bit width (bits) of supported memory configurations are as listed below. ddr-sdram data bus width is 32 bits: ? parallel connection of two 128-mbit ddr-sdrams ( 16) (total size 256 mbits) ? parallel connection of two 256-mbit ddr-sdrams ( 16) (total size 512 mbits) ? parallel connection of two 512-mbit ddr-sdrams ( 16) (total size 1 gbit) ? parallel connection of two 1-gbit ddr-sdrams ( 16) (total size 2 gbits) ? big or little endian convention for external data bus access can be selected by a pin setting at the time of a power-on reset note: ddr320 indicates the ddr-sdram bus interf ace which operates at a frequency of 160 mhz in this manual.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 402 of 1286 rej09b0158-0100 figure 12.1 shows a block diagram of the ddrif. ddrif (ddr-sdram interface) [legend] cpg: dbk: ddr: dll: min: pll: scr: sdmr: sdr: str: clock pulse generator ddr-sdram backup register double data rate delay locked loop memory interface mode register phase locked loop sdram control register sdram mode register sdram row attribute register sdram timing register superhyway bus interface ddr controller ddr i/o transfer request controller command/write data output and control register control register read data register controller scr sdmr mim sdr str dbk control register synchronizer synchronizing for internal process mclk from cpg module ddrif read data register synchronizer superhyway bus (internal bus) superhyway request receiver superhyway request buffer superhyway response transmitter superhyway response buffer dll pll3 mclk bkprst cke mcs mras mcas mwe ba1,ba0 ma13 to ma 0 mdqm3 to mdqm0 mdqs3 to mdqs0 mda31 to mda0 ddr-vref figure 12.1 ddrif block diagram
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 403 of 1286 rej09b0158-0100 12.2 input/output pins table 12.1 shows the ddrif pin configuration. for details on connection with the ddr-sdram, see the ddr-sdram pin information. table 12.1 pin configuration pin name function i/o description mclk ddr-sdram clock output clock output for ddr-sdram mclk ddr-sdram clock output clock output for ddr-sdram inverse of the mclk cke clock enable output when this pin is set high, the clock signal is active. when this pin is set low, the clock signal is inactive. mcs chip select output chip select output mwe write enable output write enable output ma13 to ma0 address output row/column address ba1, ba0 bank address output bank address output md31 to md0 data i/o data i/o mdqs3 to mdqs0 i/o data strobe i/o i/o data strobe mdqm3 to mdqm0 data mask output i/o data mask signal mras row address strobe output row address strobe signal mcas column address strobe output column address strobe signal bkprst power back-up reset input when this pin goes low, the cke pin also goes low ddr-vref reference voltage input input input reference voltage
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 404 of 1286 rej09b0158-0100 12.3 address space, bus width, and data alignment 12.3.1 address space of the ddrif this lsi supports both 29 -bit and 32-bit physical address sp aces (29-bit addres s mode and 32-bit address extended mode), and the address space is selectable from among five kinds of map by setting memory address map select register (mmselr) of the lbsc. figure 12.2 shows the physical address space of this lsi. the ddrif supports both 29-bit and 32-bit phys ical address spaces and can control an externally connected ddr-sdram memory sp ace with up to 256 mbytes. the setting in mmselr for the 29-bit address mode gives the ddrif control of not only area 3, but also areas 2, 4, and 5, which are also within the 29-bit address range. the ddrif can control a total of 4 areas with a maximum capacity of 256 mbytes as the exte rnal ddr-sdram memory space. in the case of the 32-bit address extended mode, the ddrif controls not only area 3 (and, with some settings, area 2, 4 and 5) within the 29-bit address range but also ddr-sdram areas in the physical address range from h'4000 0000 to h'7fff ffff. however, this 1-gbyte range includes areas where the areas actually allocated to th e ddrif by the mmselr are shadowed. the actual area controlled by the ddrif as the external ddr-sdram memory space is still a total of 256 mbytes. for further information on the 32-bit address extended mode, see section 7.7, 32-bit address extended mode.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 405 of 1286 rej09b0158-0100 h'0000 0000 h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1800 0000 h'1c00 0000 h'2000 0000 h'4000 0000 h'4400 0000 h'4800 0000 h'4c00 0000 h'5000 0000 h'5400 0000 h'5800 0000 h'5c00 0000 h'6000 0000 h'6400 0000 h'6800 0000 h'6c00 0000 h'7000 0000 h'7400 0000 h'7800 0000 h'7c00 0000 h'8000 0000 h'c000 0000 h'e000 0000 h'ffff ffff area 0 (lbsc) area 1 (lbsc) area 2 (lbsc/ddrif) area 3 (ddrif) area 4 (lbsc/ddrif/pcic) area 5 (lbsc/ddrif) area 6 (lbsc) area 7 (reserved area) (undefined) ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-0 ddrif-2 ddrif-1 ddrif-3 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-0 ddrif-2 ddrif-1 ddrif-3 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-0 ddrif-2 ddrif-1 ddrif-3 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-0 ddrif-2 ddrif-1 ddrif-3 ddrif-0 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-1 ddrif-2 ddrif-3 ddrif-1 ddrif-0 ddrif-2 ddrif-3 ddrif-0 ddrif-2 ddrif-1 ddrif-3 ddrif-0 ddrif-1 (undefined) ddr-sdram (ddrif) : shadow pci (pcic) pcic pcic pcic pcic pcic (internal resources) lbsc lbsc lbsc ddrif-1 lbsc lbsc lbsc lbsc lbsc lbsc ddrif-1 pcic lbsc lbsc lbsc lbsc ddrif-0 ddrif-1 lbsc lbsc lbsc lbsc lbsc ddrif-0 ddrif-1 pcic lbsc lbsc lbsc lbsc ddrif-0 ddrif-1 ddrif-2 ddrif-3 lbsc mmselr. areasel[2:0] * b'000 29-bit physical address space (normal mode) 32-bit physical address space (extended mode) note: memory address map select register (mmselr) area select bit (areasel) for details, see section 11.4.1, memory address map select register (mmselr). b'001 b'010 b'011 b'100 figure 12.2 physical address space of this lsi 12.3.2 memory data bus width the data bus width of the ddrif is 32 bits.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 406 of 1286 rej09b0158-0100 12.3.3 data alignment the ddrif supports both big endian mode, where the address of the highest order byte is 0, and little endian mode, where the address of the lowest order byte is 0. these modes can be switched by changing the level on an external pin (mode5) and then generating a power-on reset. note that wraparound in memory data access is on 32-byte boundaries. table 12.2 access and data alig nment in little endian mode md31 to md24 md23 to md16 md15 to md8 md7 to md0 byte access at address 0 bit 7 to 0 byte access at address 1 bit 7 to 0 byte access at address 2 bit 7 to 0 byte access at address 3 bit 7 to 0 byte access at address 4 bit 7 to 0 byte access at address 5 bit 7 to 0 byte access at address 6 bit 7 to 0 byte access at address 7 bit 7 to 0 word access at address 0 bit 15 to 8 bit 7 to 0 word access at address 2 bit 15 to 8 bit 7 to 0 word access at address 4 bit 15 to 8 bit 7 to 0 word access at address 6 bit 15 to 8 bit 7 to 0 longword access at address 0 bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 longword access at address 4 bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 quadword access at address 0 (first round: from address 0) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 quadword access at address 0 (second round: from address 4) bit 63 to 56 bit 55 to 48 bit 47 to 40 bit 39 to 32 16-byte access at address 0 (first round: from address 4) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (second round: from address 0) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (third round: from address 12 (h'c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (fourth round: from address 8) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 407 of 1286 rej09b0158-0100 md31 to md24 md23 to md16 md15 to md8 md7 to md0 32-byte access at address 0 (first round: from address 4) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (second round: from address 0) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (third round: from address 12 (h'c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (fourth round: from address 8) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (fifth round: from address 20 (h'14)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (sixth round: from address 16 (h'10)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (seventh round: from address 28 (h'1c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (eighth round: from address 24 (h'18)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 408 of 1286 rej09b0158-0100 table 12.3 access and data a lignment in big endian mode md31 to md24 md23 to md16 md15 to md8 md7 to md0 byte access at address 0 bit 7 to 0 byte access at address 1 bit 7 to 0 byte access at address 2 bit 7 to 0 byte access at address 3 bit 7 to 0 byte access at address 4 bit 7 to 0 byte access at address 5 bit 7 to 0 byte access at address 6 bit 7 to 0 byte access at address 7 bit 7 to 0 word access at address 0 bit 15 to 8 bit 7 to 0 word access at address 2 bit 15 to 8 bit 7 to 0 word access at address 4 bit 15 to 8 bit 7 to 0 word access at address 6 bit 15 to 8 bit 7 to 0 longword access at address 0 bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 longword access at address 4 bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 quadword access at address 0 (first round: from address 0) bit 63 to 56 bit 55 to 48 bit 47 to 40 bit 39 to 32 quadword access at address 0 (second round: from address 4) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (first round: from address 0) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (second round: from address 4) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (third round: from address 8) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 16-byte access at address 0 (fourth round: from address 12 (h'c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 409 of 1286 rej09b0158-0100 md31 to md24 md23 to md16 md15 to md8 md7 to md0 32-byte access at address 0 (first round: from address 0) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (second round: from address 4) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (third round: from address 8) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (fourth round: from address 12 (h'c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (fifth round: from address 16 (h'10)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (sixth round: from address 20 (h'14)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (seventh round: from address 24 (h'18)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 32-byte access at address 0 (eighth round: from address 28 (h'1c)) bit 31 to 24 bit 23 to 16 bit 15 to 8 bit 7 to 0 bit 31 time sequence example of memory address a[3:0] = 0000 (other than above: 32-byte wraparound operation) read (address a + 0) (address a + 4) (address a + 8) (address a + 12) bit 0 bit 63 (address a + 4) bit 32 bit 31 (address a + 0) bit 0 bit 63 (address a + 12) little endian big endian bit 32 bit 31 (address a + 8) bit 0 write ddr-sdram 32 bit time sequence bit 63 (address a + 0) bit 32 bit 31 (address a + 4) bit 0 bit 63 (address a + 8) bit 32 bit 31 (address a + 12) bit 0 time sequence figure 12.3 data alignment in ddr-sdram and ddrif
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 410 of 1286 rej09b0158-0100 12.4 register descriptions table 12.4 shows the ddrif regist er configuration. table 12.5 sh ows the register states in each processing mode. these registers should only be set while access to the ddr-s dram from a module is not in progress. furthermor e, access to registers other than the memory interface mode register (mim) should only proceed when the mim?s dce bit (ddr -sdram control enable) is cleared to 0 or the mim?s selfs bit (self-refresh status) is set to 1. although the registers are 64 bits wide, they sh ould be accessed in longword (32-bit) units. the value of a longword written to the register will be reflected correctly. a longword read from the register will contain the value in the corresponding half of the register at the time of reading. whether the current endian is big or little, specify the address liste d below to access bits 63 to 32. to access bits 31 to 0, specify the address listed below + 4. table 12.4 register configuration register name abbreviation r/w p4 address area 7 address access size memory interface mode register mim r/w h'fe80 0008 h'1e80 0008 32 ddr-sdram control register s cr r/w h'fe80 0010 h'1e80 0010 32 ddr-sdram timing register str r/w h'fe80 0018 h'1e80 0018 32 ddr-sdram row attribute register sdr r/w h'fe80 0030 h'1e80 0030 32 ddr-sdram mode register sdmr w h'fecx xxxx * h'1ecx xxxx * 32 ddr-sdram back-up register dbk r h'fe80 0400 h'1e80 0400 32 note: * for details, see section 12.4.5, sdram mode register (sdmr).
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 411 of 1286 rej09b0158-0100 table 12.5 register states in each operating mode register name abbreviation power-on reset manual reset sleep memory interface mode register mim h'0000 0000 0c34 xx00 * 1 h'0000 0000 0c34 xx00 * 1 retained ddr-sdram control register scr h'0000 0000 0000 0000 h'0000 0000 0000 0000 retained ddr-sdram timing register str h'0000 0000 0000 0000 h'0000 0000 0000 0000 retained ddr-sdram row attribute register sdr h'0000 0000 0000 0100 h'0000 0000 0000 0100 retained ddr-sdram mode register sdmr ? ? ? ddr-sdram back-up register dbk h'0000 0000 0000 000x * 2 h'0000 0000 0000 000x * 2 retained notes: 1. the initial value of bit 8 (endian bit) depends on the setting of external pins (mode5). 2. the initial value of bit 0 (sdbup bi t) depends on the setting of external pin ( bkprst ).
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 412 of 1286 rej09b0158-0100 12.4.1 memory interfac e mode register (mim) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 1 0 1 1 0 0 0 0 1 1 0 0 00 dri ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 ? 0 0 0 ? ? ?? dce ? ? dllen ? ? ? bw end ian dre ? ? lock r/w r r r/w r r r r/w r r/w r r r r rr bit: initial value: r/w: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 bomode ? ? ? ? ? ? ? ? ? ? pc ke sel fs rm ode ? r r/w r r r r r r r r r r r/w r r/w r/w bit: initial value: r/w: note: * depends on the setting of external pin (mode5). * bit bit name initial value r/w description 63 to 48 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 47, 46 bomode 00 r/w access mode switch switch access modes for the ddr-sdram. the ddrif supports two sdram access modes. for details on operation in each of the modes, see section 12.5.4, sdram access mode. 00: bank open mode 01: bank closed mode other than above: setting prohibited
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 413 of 1286 rej09b0158-0100 bit bit name initial value r/w description 45 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 44 pcke 0 r/w power down this bit controls a low power consumption mode in which the cke pin is set low to place the ddr-sdram in ?power-down mode? whenever the ddr-sdram is not being accessed (whether it is in the idle state or bank active state). when the pcke bit is set to 1, the ddr-sdram enters this power down mode. for details, see section 12.5.5 (2), power-down mode (when cke goes low). note that the sms bits in scr should be set so that the cke pin is enabled when the sdram is in its initial state. 43 to 35 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 34 selfs 0 r self-refresh decision indicates whether the ddr-sdram is or is not in the self-refresh state. 0: not self-refresh state 1: self-refresh state 33 rmode 0 r/w refresh mode select specifies whether the ddr-sdram is set to auto- refresh mode or to self-refresh mode. this bit is only valid if the dre bit in mim is set to 1. 0: auto-refresh mode 1: self-refresh mode 32 to 29 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 414 of 1286 rej09b0158-0100 bit bit name initial value r/w description 28 to 16 dri h'0c34 r/w dram refresh interval when refreshing is valid (the dre bit in mim is set to 1), these bits specify the maximum refresh interval (auto-refresh). the unit for counting is t he cycle of the mclk. in 160-mhz operation, the unit corresponds to 6.3 ns. the smallest possible setting is h'0020 units. if a lower setting is made, h'020 is added to the value for counting. the ddrif has a 13-bit internal counter. when the dce or dre bit is cleared to 0, or the rmode bit is set to 1, this counter is cleared to 0. otherwise, the counter is incremented by the external mclk. the value in the counter is compared with the dri bits. if the values match, an auto-refresh request is generated in the controller and auto-refreshing is performed. note that the counter is cleared to 0 on the match, after which incrementation begins again. a single instance of the internally generated request for auto-refresh is recorded; if the dce and dre bits are set to 1 and the rmode bit is cleared to 0, the auto- refresh request is not cleared until auto-refreshing has been performed. when setting these bits, start by making the setting and writing a 0 to the dre bit at the same time. make the setting a gain, but this time write a 1 to the dre bit at the same time. this is required for timing consistency. 15 to 12 lock undefined r dll lock status these bits indicate the state of locking by the dll that generates the read timing for the ddr-sdram when these bits are all set to 1 and the dllen bit is 1, access to memory is possible. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 dre 0 r/w dram refresh enable this bit enables or disables the use of refresh modes. 0: disable 1: enable
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 415 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 endian undefined * r endian identifier indicates whether big endian or little endian mode is selected for the external data bus. 0: little endian mode 1: big endian mode 7 bw 0 r/w bus width specifies the ddr-sdram bus width. this bit should always be cleared to 0. 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 dllen 0 r/w dll enable sets whether the dll for generating the read timing for the ddr-sdram is valid or invalid. when this bit is set to 1, the dll is enabled and read access to memory is possible. 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 dce 0 r/w ddr controller enable enables or disables sdram control by the ddrif. 0: disables sdram control 1: enables sdram control note: * depends on the setting of external pin (mode5).
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 416 of 1286 rej09b0158-0100 12.4.2 sdram control register (scr) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 sms ? ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r r r r r r r r r r r rr bit: initial value: r/w: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w:
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 417 of 1286 rej09b0158-0100 bit bit name initial value r/w description 63 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 sms 000 r/w sdram mode select these bits initialize the ddr-sdram when power is supplied and after release of the reset signal. software can be used to set these bits as listed below so that the corresponding command is issued.for details on the initialization procedure, see section 12.5.2, ddr- sdram initialization sequence. after the ddr- sdram has been initialized, normal operation (000) is specified. 000: normal operation 001: a nop command is issued (only valid if the dce bit in mim is set to 1). 010: a preall command is issued (only valid if the dce bit in mim is set to 1). 011: the cke pin is enabled. at that time, the deselect command is issued (only valid if the dce bit in mim is set to 1). 100: the refa (auto-refresh) command is issued (only valid if the dce bit in mim is set to 1). settings other than the above are prohibited. if such settings are made, correct op eration is not guaranteed. note that the pcke bit in mim is used to set the cke pin low for reduced power consumption of the ddr- sdram.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 418 of 1286 rej09b0158-0100 12.4.3 sdram timi ng register (str) str specifies various timing parameters for the ddr-sdram. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rw wr ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 srp srcd scl src sras srrd swr srfc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 63 to 20 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 19, 18 wr 00 r/w minimum number of cycles from write command to read commands these bits specify the minimum number of cycles required by the sdram from the issuing of a write command to the issuing of a subsequent read command. 00: 3 cycles 01: 4 cycles 10: 5 cycles 11: 6 cycles
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 419 of 1286 rej09b0158-0100 bit bit name initial value r/w description 17, 16 rw 00 r/w minimum number of cycles from read command to write command these bits specify the minimum number of cycles required by the sram from the issuing of a read command to the issuing of a subsequent write command. 00: 3 cycles 01: 4 cycles 10: 5 cycles 11: 6 cycles 15 to 13 srfc 000 r/w number of cycles within a single individual bank these bits specify the number of cycles between the following access operations in a given bank (the corresponding time is trfc). (1) from auto-refresh to issuing the act command (2) from auto refresh to auto refresh 000: 11 cycles 001: 12 cycles 010: 13 cycles 011: 14 cycles 100: 15 cycles other than above: setting prohibited 12 swr 0 r/w pre/preall command issuing cycle within write cycles, specifies the number of cycles from the last postamble to the issuing of a pre/preall command (the corresponding time is twr). 0: 2 cycles 1: 3 cycles 11 srrd 0 r/w inter-bank number of cycles between act commands specifies the minimum number of cycles between the issuing of act commands (the corresponding time is trrd) for any two banks. 0: 2 cycles 1: 3 cycles
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 420 of 1286 rej09b0158-0100 bit bit name initial value r/w description 10 to 8 sras 000 r/w minimum number of cycles between act and pre commands these bits specify the minimum number of cycles until a pre command is issued after an act command has been issued (the corresponding time is tras) for the same bank. 000: 6 cycles 001: 7 cycles 010: 8 cycles 011: 9 cycles other than above: setting prohibited 7 to 5 src 000 r/w auto-refresh/act command issuance cycle these bits specify the number of cycles between the following access operations in a given bank (the corresponding time is trc). (1) from issuing the act command to auto-refresh (2) from issuing one act command to issuing the next act command 000: 6 cycles 001: 7 cycles 010: 8 cycles 011: 9 cycles 100: 10 cycles 101: 11 cycles 110: 12 cycles 111: 13 cycles other than above: setting prohibited 4 to 2 scl 000 r/w cas latency these bits specify the cas latency (cl) in data read operation. 000: 2.5 cycles other than above: setting prohibited
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 421 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 srcd 0 r/w numbers of cycles between ras and cas commands specifies the number of cycles from an ras (act) command to a subsequent cas (read/reada, write/writea) command (the corresponding time is trcd). 0: 3 cycles 1: 4 cycles 0 srp 0 r/w number of cycles between pre and act commands specifies the number of cycles from a pre command to a subsequent act command (the corresponding time is trp). 0: 3 cycles 1: 4 cycles 12.4.4 sdram row attribute register (sdr) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 1 0 0 0 0 0 00 ? ? ? ? ? ? ? ? split ? ? ?? r r r r r r r r r/w r/w r/w r/w r r rr bit: initial value: r/w: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w:
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 422 of 1286 rej09b0158-0100 bit bit name initial value r/w description 63 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 8 split 0001 r/w ddr-sdram memory configuration these bits specify the row/co lumn configuration of the ddr-sdram. 0001: 12 9 (= product with 8 m 16 bits) 0011: 13 9 (= product with 16 m 16 bits) 0100: 13 10 (= product with 32 m 16 bits) 0110: 14 10 (= product with 64 m 16 bits) other than above: setting prohibited the relationship between the split bits and numbers of rows and columns is shown in section 12.5.6, address multiplexing. 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12.4.5 sdram mode register (sdmr) sdmr refers to the mode register and extended mode register of th e ddr-sdram. since the sdmr is physically within the sdram rather than the ddrif, reading the registers is invalid. only the address bits have any meaning for the ddr-sdram and any data included in the write operation is ignored. writing to the sdmr proceeds when the signal ou tput on pins connected to the ddr-sdram is as shown in the table below. address bits 12 to 3 correspond to external pins ma9 to ma0, address bits 14 and 13 to external pins ba1 and ba0, and address bits 18 to 15 to external pins ma13 to ma10. these bits contain the values for the mode registers.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 423 of 1286 rej09b0158-0100 cke address bit correspondence n-1 n cs ras cas we ba1 and ba0 ma13 to ma10 ma9 to ma0 h h l l l l bits 14 and 13 bits 18 to 15 bits 12 to 3 figure 12.4 shows the relationship between write values in sdmr and output signals to the memory pins. 31 sdram address l: low level h: high level ddr-sdram 1 30 1 29 1 28 1 27 1 26 1 25 1 24 0 23 1 22 1 21 0 20 0 19 0 18 0 17 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 1 8 1 7 0 6 0 5 0 4 0 3 1 2 0 1 0 0 0 ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 ma11 ma12 ma13 ba0 ba1 cs ras cas we h l l l l h h l l l l l l l l l l l l l mcs mars mcas mwe figure 12.4 relationship betw een write values in sdmr and output signals to memory pins for example, to release the dll from the reset st ate, set a cas latency of 2.5 cycles, sequential burst sequence, and burst length of 2 in the mode register of the sdram, the following signals must be output on the sdram pins. cs = low, ras = low, cas = low, we = low, ba0 = low, ba1 = low, ma13/ma12/ma11/ma10/ma9 = low, ma8 = low, ma7 = low, ma6 = high, ma5 = high, ma4 = low, ma3 = low, ma2 = low, ma1 = low, and ma0 = high
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 424 of 1286 rej09b0158-0100 to output the above control signals, write access to address h'fec0 0308 in sdmr is made in longwords. then the above control signals are output to the sdram pins. write data to sdmr is don't care. 12.4.6 ddr-sdram back-up register (dbk) this register indicates the ddr-sdram back-up status. for details, see section 17, power-down mode. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 00 sdbup ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: note: * depends on the setting of external pin ( bkprst ). * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 63 to 1 all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 sdbup undefined * r back-up status determine whether ddr-sdram is or is not being battery back-up status. 0: battery back-up 1: not back-up note: * depends on the setting of external pin ( bkprst ).
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 425 of 1286 rej09b0158-0100 12.5 operation 12.5.1 ddr-sdram access the ddr-sdram is accessed with a burst length of 2. read or write commands for the same page can be issued consecutively and the data is read or written continuously. 12.5.2 ddr-sdram in itialization sequence since the internal state of the sdram is undefined immediately after power is initially supplied, initialize the sdram according to the following sequence. the device may be damaged if you don?t follow this sequence. the below description is only an example of the initialization sequence for the ddr-sdram. for further details, see the datasheet from the relevant memory manufacturer. 1. turn on the four power supplies to the sdram in the following order: vdd, vddq, vref, and vtt. 2. after stabilization of the power supply, reference voltage, and clock signals, maintain the current state for at least 200 s. 3. perform a dummy read to any ddr-sdram address. 4. write h'a500 0000 to the p4 address h'fe80 0604 (big endian)/h'fe80 0600 (little endian) or the area 7 address h'1e80 0604 (big endian)/h'1e80 0600 (l ittle endian) with 32-bit access. note: the initial value of this address field is h'a500 0002 and the writing value is retained in sleep mode and initialized after a power-on reset or a manual reset. when accessing the ddr-sdram, the value of this field should be h'a500 0000. 5. set mim to enable the sdram controller and on- chip dll, select the required endian, and so on. 6. set sdr and str. 7. use the sms field in scr to enable the cke pin. 8. use the sms field in scr to issue th e all-bank precharge (preall) command. 9. use sdmr to issue the emrs command and enable the dll. 10. use sdmr to issue the mrs command and re set the dll. also set the burst length, cas latency, and so on. 11. after the preall command has been issued, use the sms field in scr to issue the refa command twice.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 426 of 1286 rej09b0158-0100 12. use sdmr to issue the mrs command, releas e the dll reset (ma8 = low), and determine the operating mode. in this case, use the settings for burst length, etc. that were specified in step 10. 13. after the dll is reset, wait for 200 cycles of the mclk: normal memory access will then be possible. ensure that the above sdmr settings, etc. of the sdram match the settings of the ddrif registers. 12.5.3 supported sdram commands table 12.6 shows the sdram comm ands supported by the ddrif. table 12.6 sdram commands issuable by ddrif function symbol cken ? 1 cken cs ras cas we ma13 to ma11 ap (ma10) ba1 and ba0 ma9 to ma0 device deselect deselect h x h x x x x x x x no operation nop h x l h h h x x x x read read h x l h l h v l v v read with auto precharge reada h x l h l h v h v v write write h x l h l l v l v v write with auto precharge writea h x l h l l v h v v bank activate act h x l l h h v v v v precharge select bank pre h x l l h l x l v x precharge all banks preall h x l l h l x h x x auto refresh refa h h l l l h x x x x self-refresh entry from idle refs h l l l l h x x x x exit self refresh refsx l h h x x x x x x x enter power down pwrdn h l h x x x x x x x exit power down pwrdnx l h h x x x x x x x mode register set mrs/ emrs h x l l l l v v v v [legend] h: high level l: low level x: don?t care
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 427 of 1286 rej09b0158-0100 v: valid data the deselect command in table 12.6 is auto matically issued whenever the sdram is not being accessed by any module. the deselect co mmand therefore cannot be explicitly issued by the user. 12.5.4 sdram access mode the ddrif supports th e following two sdram access modes. the bomode bits in mim are used to select the required mode. bank open mode: the sdram is accessed without the pre command immediately after a memory read or memory write, meaning that the bank is always open. this mode is useful for applications in which a single bank is the targ et of consecutive memory accesses. when another bank becomes the target, the pre command is automatically issued. bank closed mode: immediately after each round of read ing or writing, the pre command is output and the target bank is closed. this mode is useful for applications in which the same bank is unlikely to be the target of consecutive memory accesses. 12.5.5 power-down modes (1) self-refresh mode the self-refresh mode is a standby state in wh ich the sdram generates its own refresh timing and refresh addresses. once the self-refresh mode has been set by setting the dre and rmode bits in mim to 1, the self-refresh state is retained even if the cpu enters the sleep mode. if an interrupt then takes the cpu out of the sleep mode, the self-refresh state is still retained. although the sdram is made to enter the self-refre sh state by simply setting registers of the ddrif, the sequence given below should be followed. note that in the transition from au to-refresh state to self-refresh st ate, the current auto-refresh state should have been finished or been disabled before the transition. [transition to self-refresh state] 1. confirm that transactions to the ddrif are completed. 2. through software control, set the sms bits in scr to issue the preall (precharge all-banks) command. this closes any sdram bank that was open. after that, use the sms bits in scr to issue the refa (auto-refresh) command to ensure that all memory rows are refreshed.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 428 of 1286 rej09b0158-0100 3. the str settings do not establish a relations hip between the timing of the preall and refa commands that are issued by using scr. a period of waiting that is suitable for the memory unit must be inserted. 4. make the sdram enter the self-refresh state by setting the dre and rmode bits in mim to 1 (in this case, the value of the dce bit should be left at 1). 5. the ddrif automatically issu es the self-refresh command and sets the cke pin low. the sdram then automatically enters the self-refresh mode. 6. read the selfs status bit in mim to check whether or not the sdram has actually entered the self-refresh mode. [return from self-refresh state] 1. clear the rmode and dre bits in mim to 0 to take the dds-sdram out of the self-refresh state. 2. read the selfs status bit in mim to check whether or not the sdram has actually returned from the self-refresh mode. 3. after allowing the time required for recovery from the self-refresh state, set registers so that auto-refreshing is performed at an appropriate in terval. after the recovery, wait for the time required by the sdram before accessing th e sdram (the time depends on the ddr- sdram; for example, the requirements might be for 130 ns before issuing a command other than a read command, and 200 clock cycl es before issuing a read command). 4. when access becomes possible, use the sms bits in scr to issue the refa (auto-refresh) command so that all memory rows are refreshed. 5. dummy read a byte from any sdram address. 6. use the sms bits in scr to issue the preall (all-bank precharge) command. 7. use the sms bits in scr to issue the refa command. this operation is required to make the delay adjustment unit in the ddrif operate. 8. set mim so that the counter for the auto-refresh function starts counting and thus drives auto- refreshing at a regular interval. after this, normal memory access is possible. (2) power-down mode (when cke goes low) clearing or setting the pcke bit in mim changes the level of the cke pin, the sdram enters or leaves the power-down mode . the sdram in this mode consumes less power. since the sdram is made to enter the power-do wn mode after each round of memory access and has to leave the power-down mode before each round of memory access, an overhead of one cycle of the mclk is incurred in each case.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 429 of 1286 rej09b0158-0100 12.5.6 address multiplexing address multiplexing is performed in line with the settings of the split bits in sdr so that connecting the sdram does not require an extern al address-multiplexing circuit. table 12.7 shows the relationship between the settings of split bits and address multiplexing. the number of row or col line is the addresses (bit) that are output to the address pins according to the setting of the split bits. if a setting not specified in table 12.7 is used, correct operation is not guaranteed. table 12.7 relationship between sp lit bits and address multiplexing split[3:0] row col ba1 ba0 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 128 mbit 2 0001 12 9 row 13 12 ? ? 11 24 23 22 21 20 19 18 17 16 15 14 (8 m 16 bit 2) col 13 12 ? ? ? ap * ? 10 9 8 7 6 5 4 3 2 256 mbit 2 0011 13 9 row 13 12 ? 11 25 24 23 22 21 20 19 18 17 16 15 14 (16 m 16 bit 2) col 13 12 ? ? ? ap * ? 10 9 8 7 6 5 4 3 2 512 mbit 2 0100 13 10 row 13 12 ? 26 25 24 23 22 21 20 19 18 17 16 15 14 (32 m 16 bit 2) col 13 12 ? ? ? ap * 11 10 9 8 7 6 5 4 3 2 1 gbit 2 0110 14 10 row 13 12 27 26 25 24 23 22 21 20 19 18 17 16 15 14 (64 m 16 bit 2) col 13 12 ? ? ? ap * 11 10 9 8 7 6 5 4 3 2 note: * auto-precharge
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 430 of 1286 rej09b0158-0100 12.6 ddr-sdram basic timing figures 12.5 to 12.14 show basic timing of the ddrif. in each timing chart, the ddr- sram has been idle at t0. the settings in the sdram timing register (str) must set up timing that is within the specifications of the ddr-sdram. note that the only cas latency supported by the ddrif is 2.5. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t rcd (srcd = 1) cl = 2.5 act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda read pre row bank bank d0 d1 hi-z hi-z row bank col 0 figure 12.5 ddrif basic timing (1-/2-/4-/8-byte single burst read without auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 431 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda row write col 0 pre row bank bank bank d0 d1 hi-z hi-z t rcd (srcd = 1) figure 12.6 ddrif basic timing (1-/2-/4-/8-byte single burst write without auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 432 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 cl = 2.5 act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda reada act row bank bank bank row col 0 row row d0 d1 hi-z hi-z t rc (src = 011) t rcd (srcd = 1) t rp (srp = 0) t ras (sras = 000) figure 12.7 ddrif basic timing (1-/2-/4-/8-byte single burs t read with auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 433 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda row writea col 0 act row bank row row bank bank d0 d1 hi-z hi-z t rc (src = 101) t rcd (srcd = 1) t wr (swr = 0) t rp (srp = 0) t ras (sras = 010) figure 12.8 ddrif basic timing (1-/2-/4-/8-byte single burs t write with auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 434 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t rcd (srcd = 1) cl = 2.5 act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda row read read read read pre col 2 col 0 col 4 col 6 row bank bank bank bank bank bank d0 d1 d2 d3 d4 d5 d6 d7 hi-z hi-z figure 12.9 ddrif basic timing (4 burst read: 32-byte without auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 435 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t rcd (srcd = 1) act ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda row write write write write pre col 2 col 0 col 4 col 6 row bank bank bank bank bank bank hi-z hi-z d1 d2 d3 d4 d5 d6 d7 d0 figure 12.10 ddrif basic timing (4 burst write: 32-byte without auto precharge)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 436 of 1286 rej09b0158-0100 t0 t1 t2 t3 t4 t rp (srp = 1) preall ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda act row bank hi-z hi-z row figure 12.11 ddrif basic timing (from p recharging all banks to bank activation)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 437 of 1286 rej09b0158-0100 t0 t1 t2 t3 mrs notes: 1. operating mode or other setting 2. mode register setting: ba1 = low, ba0 = low extended mode register setting: ba1 = low, ba0 = high ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ma10 ba1-0 mdqs mdqm mda * 1 hi-z hi-z * 1 * 2 figure 12.12 ddrif basic ti ming (mode register setting)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 438 of 1286 rej09b0158-0100 refa t0 t1 t0 t1 refa ( mclk ) mcs mras mcas mwe mclk cke command ma13-11 ma9-0 ba1-0 row act bank row ma10 t rfc = 11 to 15 cycles auto refresh t rfc = 11 to 15 cycles figure 12.13 ddrif basic timing (enter auto-refresh/exit to bank activation)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 439 of 1286 rej09b0158-0100 t xsnr /t xsrd * 2 refs refsx ( mclk ) mcs mras mcas mwe notes: 1. the time where the cke signal rises should satisfy the refresh interval conditions of the sdram in use. 2. these parameters must satisfy the refresh-interval specification of the sdram. txsnr is for all commands other than read commands. txsrd is for read commands, and is usually at least 200 clock cycles. mclk cke t0 t1 t0 t1 command ma9-0 ma13-11 ma10 ba1-0 any command * 1 self refresh figure 12.14 ddrif basic timing (enter self-refresh/exit to command issuing)
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 440 of 1286 rej09b0158-0100 12.7 usage notes 12.7.1 operating frequency the ddrif supports ratios of 5:4 (ddr320) and 1:1 (ddr266) between the frequencies of the superhyway clock (shck) and ddr clock (ddrck). for details, see section 15, clock pulse generator (cpg). the maximum operating frequency of the superhyway clock is 200 mhz. the minimum operating frequency depends on the frequency of the ddr-sdram clock. therefore, see the datasheet for the ddr-sdram. 12.7.2 stopping clock supply of the clock signal for the ddrif stops in the following two cases: ? when the sdram is in battery backup mode; and ? when the pll multiplication ratio or bus-clock frequency-division ratio is changed by the frequency change register (frqcr) of the cpg. since the clock signal is not being supplied in the above situations, auto-refreshing does not proceed. since the refresh cycle is not being maintained, data in the sdram will be lost. to prevent this, software should pl ace the sdram in the self-refresh state before supply of the clock signal is stopped. for details on making the sdram enter and leave the self-refresh mode, see section 12.5.5 (1), self-refresh mode. 12.7.3 using scr to issue refa command (outside the initialization sequence) the ddr-sdram bank is automati cally opened by the ddrif access (read from or written to). when the refa (auto-refresh) command is issued by using the sms bits in scr, be sure to close the bank by using the sms bits in scr to issue the preall command. the same operation is necessary when the scr register setting is used to issue a refa command for refreshing all rows in the memory before starting up auto-refresh operations. 12.7.4 timing of connected sdram the ddrif only supports memory in which the number of cycles (trap) required from issuing an act command to issuing a read with auto-precharge or write with auto-precharge command and the number of cycles (trcd) requ ired from issuing an act command to issuing a read or write command are the same. if the tw o numbers differ, the sdram should be accessed in bank open mode.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 441 of 1286 rej09b0158-0100 12.7.5 setting auto -refresh interval the auto-refresh interval is specified by the dri bits in mim. if the dre bit is set to 1 at the same time as the dri bits are set, the time until the firs t auto-refresh is that selected by the value of the dri bits before the new setting was made. however, the second and subsequent auto-refresh intervals take on the value corresponding to the new setting for the dri bits. to avoid this situation, clear the dre bit to 0 whenever you ch ange the settings of the dri bits. when the dre bit is subsequently set to 1 and the same dri se tting is repeated, auto-refre shing proceeds with the specified interval from the first r ound. in this case, take care to ensure that the dri bits have the same value.
section 12 ddr-sdram interface (ddrif) rev.1.00 dec. 13, 2005 page 442 of 1286 rej09b0158-0100
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 443 of 1286 rej09b0158-0100 section 13 pci controller (pcic) the pci controller (pcic) controls the pci bus for data transfers between memory connected to an external bus and a pci device connected to the pci bus. the ability to connect pci devices facilitates the design of systems using the pci bus and enables more compact systems capable of faster data transfer. the pcic functions as a bus bridge which co nnects an external pci bus to the internal superhyway bus. it provides a device connected to the external pci bus with a channel for access to the on-chip modules connected to the superhyway bus. the pcic supports both the host bus bridge mode and normal mode (non-host mode). in host busbridge mode, pci bus arbitration control is available and in normal mode, arbitrati on is executed by the external pci bus arbiter. 13.1 features the pcic has the following features: ? supports subset of pci local bus specification revision 2.2 ? pci bus operating speeds of 33 mhz/66 mhz ? 32-bit data bus ? pci master and target functions ? supports subset of pci power management revision 1.1 ? supports the host bus bridge mode and normal mode (selectable by mode6 pin settings) ? supports the pci bus arbiter (in host bus bridge mode) ? supports four external masters ? pseudo-round-robin or fixed priority arbitration ? supports external bus arbiter mode ? supports configuration mechanism #1 (in host bus bridge mode) ? supports burst transfer ? parity check and error report
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 444 of 1286 rej09b0158-0100 ? exclusive access (target only) ? once locked, only accessible from the device that accessed the lock signal ? the superhyway bus in not locked during lock transfer ? can support cache coherency between a device co nnected to the pci bus and system memory (pci target) although device performance may become suboptimal ? supports four external interrupt inputs ( intd to inta ) in host bus bridge mode ? supports one external interrupt output ( inta ) in normal mode ? supports both big endian and little endian formats for the superhyway bus (the pci bus operates in the little endian format) the pcic does not support the following pci functions. ? cache support (no sbo or sdone pin) ? address wrap-around mechanism ? pci jtag (other modules in this lsi can support th e jtag feature) ? dual address cycles ? interrupt acknowledge cycles ? fast back-to-back transfer initiation (supported when performed as a target device) ? extended rom for initialization and system boot etc.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 445 of 1286 rej09b0158-0100 figure 13.1 is a block diagram of the pcic. pciecr pcic [legend] pciecr: pci enable control register superhyway bus interface shck (superhyway bus clock) superhyway bus data fifo 32-byte 2 (2 planes) data fifo 32-byte 2 (2 planes) interrupt control target control register control configuration/local register master control pciclk (pci bus clock) mode6 host/normal pci bus interface (pci bus access control) pci local bus pcireset pci standard signal figure 13.1 pcic block diagram the pcic comprises two blocks: the pci bus interface and superhyway bus interface block. the pci bus interface block comprises the pci conf iguration register, loca l register, pci master, and pci target controller. the functions of the pci bus interface are tr ansaction control on the pci local bus. the superhyway bus interface block comprises the control register (pciecr) and the data fifo. the functions of the superhyw ay bus interface are access tran slation between the pci bus interface and the cpu or dm ac via superhyway bus. the interrupt controller requests interrup t request to the intc of this lsi.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 446 of 1286 rej09b0158-0100 13.2 input/output pins table 13.1 shows the pin configuration of the pcic. table 13.1 input/output pins pin name pci standard signal name i/o description ad31 to ad0 * 1 ad[31:0] i/o (tri) pci address/data bus address and data buses are multiplexed. each bus transaction consists of an address phase followed by one or more data phases. cbe3 to cbe0 c/ be[3:0] i/o (tri) pci command/byte enable bus command and byte enables are multiplexed. these signals indicate the type of transaction during the address phase and the byte enables during the data phases. par par i/o (tri) pci parity generates/checks even parit y across ad[31:0] and cbe[3:0]. pciclk clk input pci clock provides timing for all transactions on the pci bus. pciframe frame i/o (stri) pci frame current initiator drives this signal, which indicates the start and duration or end of a transaction. trdy trdy i/o (stri) pci target ready selected target drives this signal, which indicates the target is ready to execute a transaction. during a write, this signal indicates that the target is ready to accept data. during a read, this signal indicates that valid data is present on the ad [31:0] lines. irdy irdy i/o (stri) pci initiator ready the current bus master drives this signal. during a write, this signal indicates that valid data is present on the ad [31:0] lines. during a read, this signal indicates that the master is r eady to accept data. stop stop i/o (stri) pci stop selected target drives this signal to stop the current transaction. lock lock i/o (stri) pci lock
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 447 of 1286 rej09b0158-0100 pin name pci standard signal name i/o description idsel idsel input pci configuration device select this signal is input to the pci device to select configuration cycles ( only for normal mode). devsel devsel i/o (stri) pci device select indicates the device driving this signal has decoded its address as the target. as an input, this signal indicates that a device has been selected. intd * 2 intc * 3 intb * 3 intd intc intb input interrupts d, c, and b indicate that a pci device is requesting an interrupt. only these signals are available in host bus bridge mode. inta inta i/o (output: o/d) interrupt a indicates that a pci device is requesting an interrupt (input) in host bus bridge mode. this signal is used to request an interrupt (output: o/d) in normal mode. req3 to req1 * 4 req[3:1] input pci bus request available only in host bus bridge mode. gnt3 to gnt1 * 4 gnt[3:1] output (tri) pci bus grant available only in host bus bridge mode. req0 / reqout req0 i/o (tri) pci bus request functions as an input or an output in host bus bridge mode and as an output in normal mode. gnt0 / gntin gnt0 i/o (tri) pci bus grant functions as an input or an output in host bus bridge mode and as an input in normal mode. serr serr i/o (output: o/d) pci system error perr perr i/o (tri) pci parity error pcireset ? output pci reset output (only for host bus bridge mode) mode6 * 5 ? input pci operating mode select low: pci normal mode in which the pcic operates as a pci bridge on the pciclk high: pci host bus bridge mode in which the pcic operates as a pci bridge on the pciclk
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 448 of 1286 rej09b0158-0100 [legend] tri: tri-state stri: sustained tri-state o/d: open drain notes: 1. these pins are multiplex ed with the gpio pins (port a to d). 2. this pin is multiplexed with the scif channel 0 and gpio pins. 3. these pins are multiplexed wi th the dmac, h-udi and gpio pins. 4. these pins are multiplexed with the gpio pins. 5. this pin is multiplexed with the intc and flctl pins.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 449 of 1286 rej09b0158-0100 13.3 register descriptions table 13.2 shows the pcic regist er configuration. table 13.3 show s the register states in each operating mode. the pci configuration register address and its offset are used for little endian operation. table 13.2 list of pcic registers name abbreviation sh * 1 r/w pci * 1 r/w p4 address area 7 address access size * 2 control register space pcic enable control register pciecr r/w ? h'fe00 0008 h'1e00 00008 32 pci configuration register space pci vendor id register pcivid r r h'fe04 0000 h'1e04 0000 16 pci device id register pcidid r r h'fe04 0002 h'1e04 0002 16 pci command register pcicmd r/w r/w h'fe04 0004 h'1e04 0004 16 pci status register pcistatus r/wc r/wc h'fe04 0006 h'1e04 0006 16 pci revision id register pcirid r r h'fe04 0008 h'1e04 0008 8 pci program interface register pc ipif r/w r h'fe04 0009 h'1e04 0009 8 pci sub class code register pcis ub r/w r h'fe04 000a h'1e04 000a 8 pci base class code register pcib cc r/w r h'fe04 000b h'1e04 000b 8 pci cacheline size register pcicls r r h'fe04 000c h'1e04 000c 8 pci latency timer register pciltm r/w r/w h'fe04 000d h'1e04 000d 8 pci header type register pcihdr r r h'fe04 000e h'1e04 000e 8 pci bist register pcibist r r h'fe04 000f h'1e04 000f 8 pci i/o base address register pciibar r/w r/w h'fe04 0010 h'1e04 0010 32 pci memory base address register 0 pcimbar0 r/w r/w h'fe04 0014 h'1e04 0014 32 pci memory base address register 1 pcimbar1 r/w r/w h'fe04 0018 h'1e04 0018 32 pci subsystem vendor id register pcisvid r/w r h'fe04 002c h'1e04 002c 16 pci subsystem id register pcisid r/w r h'fe04 002e h'1e04 002e 16 pci capabilities pointer register pcicp r r h'fe04 0034 h'1e04 0034 8 pci interrupt line register pciintline r/w r/w h'fe04 003c h'1e04 003c 8 pci interrupt pin register pciintpin r/w r h'fe04 003d h'1e04 003d 8
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 450 of 1286 rej09b0158-0100 name abbreviation sh * 1 r/w pci * 1 r/w p4 address area 7 address access size * 2 pci minimum grant register pcim ingnt r r h'fe04 003e h'1e04 003e 8 pci maximum latency register pcimaxlat r r h'fe04 003f h'1e04 003f 8 pci capability id register pcicid r r h'fe04 0040 h'1e04 0040 8 pci next item pointer register pcinip r r h'fe04 0041 h'1e04 0041 8 pci power management capability register pcipmc r/w r/w h'fe04 0042 h'1e04 0042 16 pci power management control/status register pcipmcsr r/w r/w h'fe04 0044 h'1e04 0044 16 pci pmcsr bridge support extension register pcipmcsr bse r r h'fe04 0046 h'1e04 0046 8 pci power consumption/dissipation data register pcipcdd r/w r h'fe04 0047 h'1e04 0047 8 pci local register space pci control register pcicr r/w r h'fe04 0100 h'1e04 0100 32 pci local space register 0 pcilsr0 r/w r h'fe04 0104 h'1e04 0104 32 pci local space register 1 pcilsr1 r/w r h'fe04 0108 h'1e04 0108 32 pci local address register 0 pcilar0 r/w r h'fe04 010c h'1e04 010c 32 pci local address register 1 pcilar1 r/w r h'fe04 0110 h'1e04 0110 32 pci interrupt register pciir r/wc r h'fe04 0114 h'1e04 0114 32 pci interrupt mask register pciimr r/w r h'fe04 0118 h'1e04 0118 32 pci error address information register pciair r r h'fe04 011c h'1e04 011c 32 pci error command information register pcicir r r h'fe04 0120 h'1e04 0120 32 pci arbiter interrupt register pciaint r/wc r h'fe04 0130 h'1e04 0130 32 pci arbiter interrupt mask register pciaintm r/wc r h'fe04 0134 h'1e04 0134 32 pci arbiter bus master error information register pcibmir r r h'fe04 0138 h'1e04 0138 32 pci pio * 3 address register pcipar r/w ? h'fe04 01c0 h'1e04 01c0 32 pci power management interrupt register pcipint r/wc ? h'fe04 01cc h'1e04 01cc 32 pci power management interrupt mask register pcipintm r/w ? h'fe04 01d0 h'1e04 01d0 32
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 451 of 1286 rej09b0158-0100 name abbreviation sh * 1 r/w pci * 1 r/w p4 address area 7 address access size * 2 pci memory bank register 0 pcimbr0 r/w ? h'fe04 01e0 h'1e04 01e0 32 pci memory bank mask register 0 pcimbmr0 r/w ? h'fe04 01e4 h'1e04 01e4 32 pci memory bank register 1 pcimbr1 r/w ? h'fe04 01e8 h'1e04 01e8 32 pci memory bank mask register 1 pcimbmr1 r/w ? h'fe04 01ec h'1e04 01ec 32 pci memory bank register 2 pcimbr2 r/w ? h'fe04 01f0 h'1e04 01f0 32 pci memory bank mask register 2 pcimbmr2 r/w ? h'fe04 01f4 h'1e04 01f4 32 pci i/o bank register pciiobr r/w ? h'fe04 01f8 h'1e04 01f8 32 pci i/o bank master register pciio bmr r/w ? h'fe04 01fc h'1e04 01fc 32 pci cache snoop control register 0 pcicscr0 r/w ? h'fe04 0210 h'1e04 0210 32 pci cache snoop control register 1 pcicscr1 r/w ? h'fe04 0214 h'1e04 0214 32 pci cache snoop address register 0 pcicsar0 r/w ? h'fe04 0218 h'1e04 0218 32 pci cache snoop address register 1 pcicsar1 r/w ? h'fe04 021c h'1e04 021c 32 pci pio * 3 data register pcipdr r/w ? h'fe04 0220 h'1e04 0220 32 notes: 1. sh: superhyway bus (internal bus). pci: pci local bus. wc: cleared by writing 1 (writing of 0 is no effect). ?: accessing is prohibited. 2. when accessing a register, do not use a si ze smaller than the register's access size. 3. pio: programmed i/o.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 452 of 1286 rej09b0158-0100 table 13.3 register states in each operating mode name abbreviation power-on reset manual reset sleep mode control register space pcic enable control register pciecr h'0000 0000 retained retained pci configuration register space pci vendor id register pcivid h'1912 retained retained pci device id register pcidid h'0002 retained retained pci command register pcicmd h'0080 retained retained pci status register pcistatus h'0290 retained retained pci revision id register pc irid h'00 retained retained pci program interface register pcipif h'00 retained retained pci sub class code register pcisub h'00 retained retained pci base class code register pcibcc h'00 retained retained pci cache line size register pcicls h'20 retained retained pci latency timer register pciltm h'00 retained retained pci header type register pcihdr h'00 retained retained pci bist register pcibist h'00 retained retained pci i/o base address register pciibar h'0000 0001 retained retained pci memory base address register 0 pcimbar0 h'0000 0000 retained retained pci memory base address register 1 pcimbar1 h'0000 0000 retained retained pci subsystem vendor id register pcisvid h'0000 retained retained pci subsystem id register pcisid h'0000 retained retained pci capabilities pointer register pcicp h'40 retained retained pci interrupt line register pciintline h'00 retained retained pci interrupt pin register pciintpin h'01 retained retained pci minimum grant register pc imingnt h'00 retained retained pci maximum latency register pcimaxlat h'00 retained retained pci capability id register pcicid h'01 retained retained pci next item pointer register pcinip h'00 retained retained
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 453 of 1286 rej09b0158-0100 name abbreviation power-on reset manual reset sleep mode pci power management capability register pcipmc h'000a retained retained pci power management control/status register pcipmcsr h'0000 retained retained pci pmcsr bridge support extension register pcipmcsr bse h'00 retained retained pci power consumption/dissipation data register pcipcdd h'00 retained retained pci local register space pci control register pcicr h'0000 00xx retained retained pci local space register 0 pcilsr0 h'0000 0000 retained retained pci local space register 1 pcilsr1 h'0000 0000 retained retained pci local address register 0 pcilar0 h'0000 0000 retained retained pci local address register 1 pcilar1 h'0000 0000 retained retained pci interrupt register pciir h'0000 0000 retained retained pci interrupt mask register pciimr h'0000 0000 retained retained pci error address information register pciair h'xxxx xxxx retained retained pci error command information register pcicir h'xx00 000x retained retained pci arbiter interrupt register pciaint h'0000 0000 retained retained pci arbiter interrupt mask register pciaintm h'0000 0000 retained retained pci arbiter bus master error information register pcibmir h'0000 00xx retained retained pci pio address register pcipar h'80xx xxxx retained retained pci power management interrupt register pcipint h'0000 0000 retained retained pci power management interrupt mask register pcipintm h'0000 0000 retained retained pci memory bank register 0 pcimbr0 h'0000 0000 retained retained pci memory bank mask register 0 pcimbmr0 h'0000 0000 retained retained pci memory bank register 1 pcimbr1 h'0000 0000 retained retained pci memory bank mask register 1 pcimbmr1 h'0000 0000 retained retained
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 454 of 1286 rej09b0158-0100 name abbreviation power-on reset manual reset sleep mode pci memory bank register 2 pcimbr2 h'0000 0000 retained retained pci memory bank mask register 2 pcimbmr2 h'0000 0000 retained retained pci i/o bank register pciiobr h'0000 0000 retained retained pci i/o bank master register pciiobmr h'0000 0000 retained retained pci cache snoop control register 0 pcicscr0 h'0000 0000 retained retained pci cache snoop control register 1 pcicscr1 h'0000 0000 retained retained pci cache snoop address register 0 pcicsar0 h'0000 0000 retained retained pci cache snoop address register 1 pcicsar1 h'0000 0000 retained retained pci pio data register pcipdr h'xxxx xxxx retained retained [legend] x: undefined
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 455 of 1286 rej09b0158-0100 13.3.1 pcic enable control register (pciecr) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 enbl ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r/w r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 enbl 0 r/w pci enable bit. enable the pcic 0: pcic disable the access from both the cpu and external pci devices to the pcic is invalid (including the configuration and local re gister), except pciecr. 1: pcic enable
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 456 of 1286 rej09b0158-0100 13.3.2 configuration registers the configuration registers defines the programming model and usages for the configuration register space in a pci compliant device. for details, refer to ?pci local bus specification revision 2.2 chapter 6 configuration space ?. (1) pci vender id register (pcivid) this register identifies th e manufacturer of device. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 1 0 0 1 0 0 0 1 0 0 1 1 0 00 vid r r r r r r r r r r r r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 0 vid h'1912 sh: r pci: r pci vender id indicates the pci device manu facture identifier (vender id) that is allocated by pci-sig. renesas technology?s vendor id is h'1912. (2) pci device id register (pcidid) this register uniquely identifies this lsi amongst pci devices manufactured by the vendor. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 did r r r r r r r r r r r r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 0 did h'0002 sh: r pci: r pci device id these bits uniquely identify this lsi amongst pci devices manufactured by the vendor indicated by the pci vender field. the sh7780?s device id is h'0002.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 457 of 1286 rej09b0158-0100 (3) pci command register (pcicmd) the pci command register provides coarse control over a device's ability to generate and respond to pci cycles. when 0 is written to this register, the device is logically disconnected from the pci bus for all accesses except configuration accesses. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ios ms bm sc mwie vgaps per wcc serre fbbe ? ? ? ? ?? 0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 r/w r/w r/w r r r r/w r/w r/w r r r r r rr bit: initial value: sh r/w: r/w r/w r/w r r r r/w r/w r/w r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 10 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 9 fbbe 0 sh: r pci: r pci fast back-to-back enable controls whether or not a master can do fast back-to- back transactions to different device. 0: fast back-to-back transactions are only allowed to the same target 1: master is allowed to generate fast back-to-back transactions to different targets (not supported) 8 serre 0 sh: r/w pci: r/w pci serr output control controls the serr output. 0: serr output disabled 1: serr output enabled 7 wcc 1 sh: r/w pci: r/w wait cycle control controls the address/data stepping. when wcc = 1, both an address and data for a master write, only an address for a master read, and only data for a target read are output for at least two clock cycles. 0: address/data stepping control disabled 1: address/data stepping control enabled
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 458 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 per 0 sh: r/w pci: r/w parity error controls the device's response when the pcic detects a parity error or receives a parity error. when this bit is set to 1, the perr signal is asserted. 0: no response parity error 1: response parity error 5 vgaps 0 sh: r pci: r vga palette snoop control 0: vga compatible device 1: palette register writ e is not supported (not supported) 4 mwie 0 sh: r pci: r pci memory write and invalidate control controls issuance of a memory write and invalidate command in a master access. 0: memory write is used 1: memory write and invalidate command is executable (not supported) 3 sc 0 sh: r pci: r pci special cycles indicates whether or not to support the special cycle operations in a target access. 0: special cycles ignored 1: special cycles monito red (not supported) 2 bm 0 sh: r/w pci: r/w pci bus master control controls a bus master. 0: bus master function disabled 1: bus master function enabled 1 ms 0 sh: r/w pci: r/w pci memory space control controls accesses to memory space of this lsi. when this bit is cleared to 0, a me mory transfer to the pcic is terminated with a master abort. 0: does not respond to memory space accesses 1: respond to memory space accesses 0 ios 0 sh: r/w pci: r/w pci i/o space controls accesses to i/o space of this lsi. when this bit is cleared to 0, a i/o transfer to the pcic is terminated with a master abort. 0: does not respond to i/o space accesses 1: respond to i/o space accesses
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 459 of 1286 rej09b0158-0100 (4) pci status register (pcistatus) this status register is used to record status information for pc i bus related events. the definition of each of the bits is given in the table below. a device may not need to implement all the bits, depending on device functionality. for instance, since a device that acts as a target does not inform a target abort, bit 11 does not need to be implemented. reserved bits should be read-only and return zero when the bits are read. reads from this register operates no rmally. writes are slightly differe nt in that bits can be cleared, but not set. a one bit is cleared whenever the re gister is written to, and the write data in the corresponding bit location is a 1. for instance, to clear bit 14 and not affect any other bits, write the value of b'0100 0000 0000 0000 to the register. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? cl 66c ? fbbc mdpe devsel sta rta rma dpe sse 0 0 0 0 1 0 0 1 0 1 0 0 0 0 00 r r r r r r/w r/w r r/wc r r r/wc r/wc r/wc r/wc r/wc bit: initial value: sh r/w: r r r r r r r r r/wc r r r/wc r/wc r/wc r/wc r/wc pci r/w: bit bit name initial value r/w description 15 dpe 0 sh: r/wc pci: r/wc parity error detect status indicates that a parity error has been detected in read data when the pcic is a master or in write data when the pcic is a target. this bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. 0: device is not detecting parity error. 1: device is detecting parity error. 14 sse 0 sh: r/wc pci: r/wc system error output status indicates that the pcic has asserted the serr signal. 0: serr has not been asserted 1: serr has been asserted (the value retained until cleared)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 460 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 rma 0 sh: r/wc pci: r/wc master abort receive status indicates that the pcic has terminated a transaction with a master abort when the pcic is a master. 0: pcic has not terminated a transaction with a master abort 1: pcic has terminated a transaction with a master abort 12 rta 0 sh: r/wc pci: r/wc target abort receive status indicates that a transaction is terminated by a target device with a target abort when the pcic functions as a master. 0: transaction has not been terminated with a target abort 1: transaction has been terminated with a target abort 11 sta 0 sh: r/wc pci: r/wc target abort execution status indicates that the pcic has terminated a transaction with a target-abort when the pcic functions as a target. 0: pcic has not terminated a transaction with a target-abort 1: pcic has terminated a transaction with target-abort 10, 9 devsel 01 sh: r pci: r devsel timing status indicate the response timing status of the devsel signal when the pcic functions as a target. 00: fast (not support) 01: medium 10: slow (not support) 11: reserved 8 mdpe 0 sh: r/wc pci: r/wc data parity error indicates that the pcic has asserted the perr signal or detected the assertion of the perr signal if the pcic functions as a master. only when the parity response bit has been set to 1, this bit is set to 1. 0: data parity error has not been generated 1: data parity error has been generated
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 461 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 fbbc 1 sh: r pci: r fast back-to-back status indicates whether or not the pcic is capable of accepting fast back-to-back transactions when the transactions are not to the same agent if the pcic functions as a target. 0: fast back-to-back transactions to different agents not supported 1: fast back-to-back transactions to different agents supported 6 ? 0 sh: r/w pci: r reserved these bits are always read as 0. the write value should always be 0. 5 66c 0 sh: r/w pci: r 66mhz-operation capable status indicates whether or not the pcic is capable of running at 66mhz. 0: pcic runs at 33 mhz 1: pcic runs at 66 mhz 4 cl 1 sh: r pci: r pci power management (optional function) indicates whether or not the pci power management function is supported. 0: power management not supported 1: power management supported 3 to 0 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 462 of 1286 rej09b0158-0100 (5) pci revision id register (pcirid) this register specifies a devi ce specific revision identifier. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 rid r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 rid h'00 sh: r pci: r revision id indicates the pcic revision.the initial value is h'00.rid value varies according to the logic version of the pcic and it may be changed in the future. (6) pci program interface register (pcipif) this register is the programming interface for the ide controller class code. for details of the class code, refer to ?pci local bus specification revision 2.2 appendix d.? r r r r r r r r pci r/w: 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 omp pip oms pis ? ? ? mided r/w r/w r/w r/w r r r r/w bit: initial value: sh r/w: bit bit name initial value r/w description 7 mided 0 sh: r/w pci: r pci master ide device specifies the pci master ide device. 1: pci master ide device 0: pci slave ide device when the cfinit bit in pcicr is 0, this bit is writable. when the cfinit bit in pcicr is 1, writing is ignored. this bit is readable.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 463 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 to 4 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 3 pis 0 sh: r/w pci: r pci programmable indicator (secondary) when the cfinit bit in pcicr is 0, this bit is writable. when the cfinit bit in pcicr is 1, writing is ignored. this bit is readable. 2 oms 0 sh: r/w pci: r pci operating mode (secondary) when the cfinit bit in pcicr is 0, this bit is writable. when the cfinit bit in pcicr is 1, writing is ignored. this bit is readable. 1 pip 0 sh: r/w pci: r pci programmable indicator (primary) when the cfinit bit in cr is 0, this bit is writable. when the cfinit bit in pcicr is 1, writing is ignored. this bit is readable. 0 omp 0 sh: r/w pci: r pci operating mode (primary) when the cfinit bit in pcicr is 0, this bit is writable. when the cfinit bit in pcicr is 1, writing is ignored. this bit is readable.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 464 of 1286 rej09b0158-0100 (7) pci sub class code register (pcisub) this register identifies the sub class code. for de tails of the class code, refer to ?pci local bus specification revision 2.2 appendix d.? 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 sub r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 sub h'00 sh: r/w pci: r sub class code indicate the sub class code. the initial value is h'00. (8) pci base class code register (pcibcc) this register identifies the base class code. for de tails of the class code, refer to ?pci local bus specification revision 2.2 appendix d.? 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 bcc r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 bcc h'00 sh: r/w pci: r base class code indicates the base class co de. the initial value is h'00.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 465 of 1286 rej09b0158-0100 (9) pci cacheline size register (pcicls) 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 cls r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 cls h'20 sh: r pci: r cache line size: not supported a memory target does not support a cache. sdon and sbo are ignored. (10) pci latency timer register (pciltm) this register specifies, in units of pci bus clocks, the value of latency timer for this pci bus master. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 ltm r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r/w r/w r/w r/w r/w r/w r/w r/w pci r/w: bit bit name initial value r/w description 7 to 0 ltm h'00 sh: r/w pci: r/w pci latency timer specifies the maximum number of acquisition clocks of pci bus when the pcic is operating as the master.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 466 of 1286 rej09b0158-0100 (11) pci header type register (pcihdr) r r r r r r r r pci r/w: 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 hdr mfe r r r r r r r r bit: initial value: sh r/w: bit bit name initial value r/w description 7 mfe 0 sh: r pci: r multiple function enable 0: single function 1: multiple (from two to eight) functions (not supported) 6 to 0 hdr h'00 sh: r pci: r configuration layout indicates the layout type of configuration registers. h'00: type "00h" layout supported h'01: type "01h" layout s upported (not supported) (12) pci bist register (pcibist) r r r r r r r r pci r/w: 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? bistc r r r r r r r r bit: initial value: sh r/w: bit bit name initial value r/w description 7 bistc 0 sh: r pci: r this bit is used to control the bist function and status. 0: function not available 1: function available (not supported) 6 to 0 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 467 of 1286 rej09b0158-0100 (13) pci i/o base address register (pciibar) this register packages the i/o space base address re gister of the pci configur ation register that is prescribed with pci lo cal bus specification. refer to section 13.4.4 (1), a ccessing this lsi address space. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 asi ? iob (lower) iob (upper) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 iob (upper) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pci r/w: bit bit name initial value r/w description 31 to 8 iob (upper) h'000000 sh: r/w pci: r/w i/o space base address (upper 24 bits) specifies the upper 24 bi ts of i/o base address that corresponds the pcic local register space (pcic control register space). 7 to 2 iob (lower) 000000 sh: r pci: r i/o space base address (lower 6 bits) these bits are fixed 000000 by hardware. 1 ? 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 0 asi 1 sh: r pci: r address space indicator indicates whether the base address in this register indicates the i/o or memory space. 0: memory space 1: i/o space
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 468 of 1286 rej09b0158-0100 (14) pci memory base address register 0 (pcimbar0) this register packages the memory space base ad dress register of the pci configuration register that is prescribed with pci local bus specification. refer to section 13.4.4 (1), a ccessing this lsi address space. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 asi lat lap mba (lower) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r r r r r r r r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 mba (upper) mba (lower) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pci r/w: bit bit name initial value r/w description 31 to 20 mba (upper) h'000 sh: r/w pci: r/w memory space 0 base address (upper 12 bits) specifies the upper 12 bits of memory base address that corresponds the local address space 0 (superhyway bus address space of this lsi). update value pcilsr [28:20] address space effective bit of mba (upper) 0 0000 0000 1 mbyte [31:20] 0 0000 0001 2 mbytes [31:21] 0 0000 0011 4 mbytes [31:22] | | | 0 1111 1111 256 mbytes [31:28] 1 1111 1111 512 mbytes [31:29] 19 to 4 mba (lower) h'0000 sh: r pci: r memory space 0 base address (lower 16 bits) these bits are fixed h'0000 by hardware. 3 lap 0 sh: r pci: r prefetch control indicates whether or not local address space 0 is prefetchable. 0: not prefetchable 1: prefetchable (not supported)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 469 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2, 1 lat 00 sh: r pci: r memory type indicates the memory type of local address space 0. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-mbyte space (not supported) 10: 64-bit base address (not supported) 11: reserved 0 asi 0 sh: r pci: r address space indicator indicates whether the base address in this register indicates the i/o or memory space. 0: memory space 1: i/o space (15) pci memory base address register 1 (pcimbar1) this register packages the memory space base ad dress register of the pci configuration register that is prescribed with pci local bus specification. refer to section 13.4.4 (1), a ccessing this lsi address space. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 asi lat lap mba (lower) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r r r r r r r r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 mba (upper) mba (lower) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pci r/w:
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 470 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 20 mba (upper) h'000 sh: r/w pci: r/w pci memory space 1 base address (upper 12 bits) specifies the upper 12 bits of pci memory base address that corresponds the base address of local address space 1 (superhyway bus address space of this lsi). pcilse0 [28:20] address space effective bit of mba (upper) 0 0000 0000 1 mbyte [31:20] 0 0000 0001 2 mbytes [31:21] 0 0000 0011 4 mbytes [31:22] | | | 0 1111 1111 256 mbytes [31:28] 1 1111 1111 512 mbytes [31:29] 19 to 4 mba (lower) h'0000 sh: r pci: r memory space 1 base address (lower 16 bits) these bits are fixed h'0000 by hardware. 3 lap 0 sh: r pci: r prefetch control indicates whether or not local address space 1 is prefetchable. 0: not prefetchable 1: prefetchable (not supported) 2, 1 lat 00 sh: r pci: r memory type indicates the memory type of local address space 1. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-mbyte space (not supported) 10: 64-bit base address (not supported) 11: reserved 0 asi 0 sh: r pci: r address space indicator indicates whether the base address in this register indicates the i/o or memory space. 0: memory space 1: i/o space
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 471 of 1286 rej09b0158-0100 (16) pci subsystem vender id register (pcisvid) refer to miscellaneous registers section of pci local bus specification revision 2.2. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 svid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 0 svid h'0000 sh: r/w pci: r subsystem vendor id specifies the subsystem vendor id of the pcic. the initial value is h'0000. this field can be modified during initializing pcic registers (pcicr.cfinit = 0), but cannot be modified after initialized pcic register (pcicr.cfinit = 1) even if writing this field. (17) pci subsystem id register (pcisid) refer to section about miscellaneous registers of pci local bus specification revision 2.2. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ssid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 0 ssid h'0000 sh: r/w pci: r subsystem id specifies the subsystem id of the pcic. the initial value is h'0000. this field can be modified during initializing pcic registers (pcicr.cfinit = 0), but cannot be modified after initialized pcic register (pcicr.cfinit = 1) even if writing this field.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 472 of 1286 rej09b0158-0100 (18) pci capability pointer register (pcicp) this register is the expansion function pointer register of the pci configuration register that is prescribed in the pci power management specification. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 1 0 cp r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 cp h'40 sh: r pci: r capabilities pointer the offset address of the ex pansion function register. (19) pci interrupt line register (pciintline) 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 intline r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r/w r/w r/w r/w r/w r/w r/w r/w pci r/w: bit bit name initial value r/w description 7 to 0 intline h'00 sh: r/w pci: r/w pci interrupt line pci interrupt connected to the external interrupt of this lsi. specify these bits by system software during initialization. the initial value is h'00. the setting value of this field does not affect the operation of this lsi.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 473 of 1286 rej09b0158-0100 (20) pci interrupt pin register (pciintpin) 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 intpin r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 intpin h'01 sh: r/w pci: r interrupt pin select specifies which interrupt pin is used for connection when the pcic outputs interrupt request. h'00: does not connect intd to inta h'01: inta is used to request an interrupt h'02: intb is used to request an interrupt h'03: intc is used to request an interrupt h'04: intd is used to request an interrupt h'05 to h'ff: reserved (21) pci minimum grant register (pcimingnt) this register is not programmable. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 mingnt r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 mingnt h'00 sh: r pci: r minimum grant specify the burst time to be required by the master device (not supported).
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 474 of 1286 rej09b0158-0100 (22) pci maximum latency register (pcimaxlat) this register is not programmable. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 maxlat r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 maxlat h'00 sh: r pci: r maximum latency specify the worst time from the bus request by the pci master device to the bus acquisition (not supported). (23) pci capability identifier register (pcicid) when h'01 is read by system software, it indicates that the data structur e currently being pointed to is the pci power management data structure. each function of a pci device may have only one item in its capability list with pcicid set to h'01. 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 cid r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 cid h'01 sh: r pci: r expansion function id specifies the expansion function id. h'01: the expansion function is power management.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 475 of 1286 rej09b0158-0100 (24) pci next item pointer register (pcinip) pcinip gives the location of the next item in the function's capability list. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 nip r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 nip h'00 sh: r pci: r next item pointer specifies the offset to the next expansion function. h'00: power management function is listed as the last item.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 476 of 1286 rej09b0158-0100 (25) pci power management capability register (pcipmc) pcipmcs is a 16-bit register that provides information on the capabilities of the power management related functions. for details, refer to ?pci bus power management interface specification revision 1.1 chapter 3 pci power management interface?. this register must be set during initializing the pcic registers (pcicr.cfinit = 0). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 pmv pmec ? dsi ? ? ? d1s d2s pmcs 0 1 0 1 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r r r r r r/w r/w r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 to 11 pmcs 00000 sh: r pci: r pme_support this 5-bit field indicates the power states in which the function may assert pme . a value of 0b for any bit indicates that the function is not capable of asserting the pme signal while in that power state. bit11: xxxx1 - pme can be asserted from d0 bit12: xxx1x - pme can be asserted from d1 bit13: xx1xx - pme can be asserted from d2 bit14: x1xxx - pme can be asserted from d3 hot bit15: 1xxxx - pme can be asserted from d3 cold note: this lsi dose not have the pme pin. 10 d2s 0 sh: r/w pci: r when this bit is 1, this function supports the d2 power management state. when the d2 power management state is not suppor ted, this bit is read as 0. 9 d1s 0 sh: r/w pci: r when this bit is 1, this function supports the d1 power management state. when the d1 power management state is not suppor ted, this bit is read as 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 477 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 to 6 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 5 dsi 0 sh: r pci: r dsi specifies whether or not the device requires the specific initialization. 0: does not require the specific initialization 4 ? 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 3 pmec 1 sh: r/w pci: r pci pme clock specifies whether or not the device requires the clock to support pme generation. 1: requires the clock to support pme generation note: this lsi dose not have the pme pin. 2 to 0 pmv 010 sh: r/w pci: r version specifies the version of the power management specifications. 010: this lsi's power manag ement specification is conformed to revision 1.1
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 478 of 1286 rej09b0158-0100 (26) pci power management control/status register (pcipmcsr) this 16-bit register is used to manage the pci function's power management status as well as to enable/monitor pmes. for details, refer to ?pci bus power management interface specification revision 1.1 chapter 3 pci power management interface?. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ps ?? ? ? ? ? pme en dsl dsc pmes 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r r r r r r r r r r r r rr bit: initial value: sh r/w: r r r r r r r r r r r r r r rr pci r/w: bit bit name initial value r/w description 15 pmes 0 sh: r pci: r pme status indicates the state of the pme signal. (not supported) note: this lsi dose not have the pme pin. 14, 13 dsc 00 sh: r pci: r data scale specify the scaling of data field. (not supported) 12 to 9 dsl 0000 sh: r pci: r data select specify the data output in the data filed. 8 pmeen 0 sh: r pci: r pme enable controls the pme output. (not supported) note: this lsi dose not have the pme pin. 7 to 2 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 1, 0 ps 00 sh: r/w pci: r/w power state specifies the power state. if software attempts to write an unsupported, optional state to these bits, the writ e operation must complete normally on the bus; however, the data is discarded and no state change occurs. 00: d0 state 01: d1 state 10: d2 state 11: d3 hot state (power-down mode)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 479 of 1286 rej09b0158-0100 (27) pcipmcsr bridge support extension register (pcipmcsrbse) this register supports pci bridge specific functionality and is required for all pci-to-pci bridges. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 ? ? ? ? ? ? b2b3n bpc cen r r r r r r r r bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 bpccen 0 sh: r pci: r when the bus power/clock control mechanism is disabled, the power state bits in bridge's pcipmcsr cannot be used by the system software to control the power or clock of the bridge's secondary bus. 6 b2b3n 0 sh: r pci: r the state of this bit determines the action that is to occur as a direct result of programming the function to the d3 hot state. 0: indicates that when the bridge function is set to the d3 hot state, its second ary bus will have its power removed (b3). 1: indicates that when the bridge function is set to the d3 hot state, its secondary bus's pci clock will be stopped (b2). this bit is only valid if bit 7 (bpccen) is set to 1. 5 to 0 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 480 of 1286 rej09b0158-0100 (28) pci power consumption/radiation register (pcipcdd) the data register is an 8-bit register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. for details, refer to ?pci bus power management interface specification re vision 1.1 chapter 3 pci power management interface?. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pcdd r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: sh r/w: r r r r r r r r pci r/w: bit bit name initial value r/w description 7 to 0 pcdd h'00 sh: r/w pci: r this register is used to report the state dependent data requested by the pcipmcsr.dsl bits. the value of this register is scaled by the value reported by the pcipmcsr.dsc bits.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 481 of 1286 rej09b0158-0100 13.3.3 local register (1) pci control register (pcicr) pcicr is a 32-bit register which sp ecifies the operation of the pcic. the register is write protected; only writes in which the upper eight bits (that is, bits 31 to 24) have the value h'a5 are performed. all other writes are ignored. r/w r/w r/w r r r/w r r/w r/w r/w r/w r r rr sh r/w: r r r r r r r r r r r r r r rr pci r/w: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r rr sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? bit: initial value: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 ? ? 0 0 0 0 0 0 0 0 00 rst ctl cfi nit iocs r/w 0 serr ? ? bmam ? tbs pfe fto pfcs ? ? ?? bit: initial value: bit bit name initial value r/w description 31 to 24 ? h'00 sh: r/w pci: r reserved set these bits to h'a5 only when writing to bits 11 to 8, 6, and 3 to 0. these bits are always read as 0. 23 to 12 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 11 pfcs 0 sh: r/w pci: r pci pre-fetch command setting this bit is valid only when the pfe bit is 1. 0: always 8-byte pre-fetching 1: always 32-byte pre-fetching 10 fto 0 sh: r/w pci: r pci trdy control enable in a target access, negate the trdy , within 5 cycles before disconnection. 0: disabled 1: enabled 9 pfe 0 sh: r/w pci: r pci pre-fetch enable 0: disabled 1: enabled
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 482 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 tbs 0 sh: r/w pci: r byte swap specifies whether or not byte data is swapped when accessing to the pci local bus. 0: no swap 1: byte data is swapped for details, see section 13.4.3 (5), endian or section 13.4.4 (6), endian. 7 ? 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 6 bmam 0 sh: r/w pci: r bus master arbitration controls the pci bus arbitration mode when the pcic operates in host bus bridge mode. this bit is ignored when the pcic operates in normal mode. 0: fixed mode (pcic > device0 > device1 > device2 > device3) 1: pseudo round robin (the most recently granted device is assigned the lowest priority) 5, 4 ? undefined sh: r pci: r reserved these bits are always read as an undefined value. the write value should always be 0. 3 serr 0 sh: r/w pci: r serr output controls the serr output by software. this bit is valid only in normal mode (do not use in host bus bridge mode). this bit is valid only when the serre bit in pcicmd is 1. 0: makes serr output high-impedance state (driven high by pull-up register) 1: asserts serr output during one pciclk clock cycle (low level output) 2 iocs 0 sh: r/w pci: r inta output controls the inta output by software. this bit is valid only in normal mode. 0: makes inta output high-impedance state (driven high by pull-up registor) 1: asserts inta output (low level output)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 483 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 rstctl 0 sh: r/w pci: r pcireset output controls the pcireset output by software. this bit is valid when the pcic operates in host bus bridge mode. 0: negates pcireset output (high level output) 1: asserts pcireset output (low level output) note: the pcireset is also asserted during power- on reset. 0 cfinit 0 sh: r/w pci: r pci internal register initialize control set this bit to 1 after the initialization of the pcic internal registers are completed. setting this bit enables accesses from the pci bus. during initialization in host bus bridge mode, the bus is not given to the device on the pci bus. in normal mode, the pcic returns retry when it is accessed from the pci bus. 0: during initialization 1: initialization completed (2) pci local space register 0 (pcilsr0) refer to section 13.4.4 (1), a ccessing this lsi address space. sh r/w: pci r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r rr r r r r r r r r r r r r r r rr sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? lsr ? ?? bit: initial value: r/w r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 mba re ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value:
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 484 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 29 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 28 to 20 lsr 0 0000 0000 sh: r/w pci: r size of local address space 0 (9 bits) specify the size of local address space 0 (superhyway bus address space of this lsi) in units of mbyte. the value set in these bits must be the size minus 1 mbytes. setting all the bits to 0 ensures 1- mbyte space. 0 0000 0000: 1 mbyte 0 0000 0001: 2 mbytes 0 0000 0011: 4 mbytes 0 0000 0111: 8 mbytes 0 0000 1111: 16 mbytes 0 0001 1111: 32 mbytes 0 0011 1111: 64 mbytes 0 0111 1111: 128 mbytes 0 1111 1111: 256 mbytes 1 1111 1111: 512 mbytes other than above: setting prohibited 19 to 1 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 0 mbare 0 sh: r/w pci: r pci memory base address register 0 enable the local address space 0 can be accessed by setting this bit to 1. 0: pcimbar0 disabled 1: pcimbar0 enabled
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 485 of 1286 rej09b0158-0100 (3) pci local space register 1 (pcilsr1) refer to section 13.4.4 (1), a ccessing this lsi address space. sh r/w: pci r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r rr r r r r r r r r r r r r r r rr sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? lsr ? ?? bit: initial value: r/w r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 mba re ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 29 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 28 to 20 lsr 0 0000 0000 sh: r/w pci: r size of local address space 1 (9 bits) specify the size of local address space 1 (superhyway bus address space of this lsi) in units of mbyte. the value set in these bits must be the size minus 1 mbytes. setting all the bits to 0 ensures 1- mbyte space. 0 0000 0000: 1 mbyte 0 0000 0001: 2 mbytes 0 0000 0011: 4 mbytes 0 0000 0111: 8 mbytes 0 0000 1111: 16 mbytes 0 0001 1111: 32 mbytes 0 0011 1111: 64 mbytes 0 0111 1111: 128 mbytes 0 1111 1111: 256 mbytes 1 1111 1111: 512 mbytes other than above: setting prohibited 19 to 1 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 486 of 1286 rej09b0158-0100 bit bit name initial value r/w description 0 mbare 0 sh: r/w pci: r pci memory base address register 1 enable the local address space 1 can be accessed by setting this bit to 1. 0: pcimbar1 disabled 1: pcimbar1 enabled (4) pci local address register 0 (pcilar0) refer to section 13.4.4 (1), a ccessing this lsi address space. sh r/w: pci r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r r r r r r r rr sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? lar bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 20 lar h'000 sh: r/w pci: r local address (12 bits) specify bits 31 to 20 of the start address in local address space 0. the effective bits of lar depe nd on the capacity of local address space 0 as specified in pcilsr0. the effective bits are as follows: pcilsr0.ls0([28:20]) = 0 0000 0000 : effective bits are [31:20] pcilsr0.ls0([28:20]) = 0 0000 0001 : effective bits are [31:21] pcilsr0.ls0([28:20]) = 0 0000 0011 : effective bits are [31:22] | | pcilsr0.ls0([28:20]) = 0 1111 1111 : effective bits are [31:28] pcilsr0.ls0([28:20]) = 1 1111 1111 : effective bits are [31:29] 19 to 0 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 487 of 1286 rej09b0158-0100 (5) pci local address register 1 (pcilar1) refer to section 13.4.4 (1), a ccessing this lsi address space. sh r/w: pci r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r r r r r r r rr sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? lar bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 20 lar h'000 sh: r/w pci: r local address (12 bits) specify bits 31 to 20 of the start address in local address space 1. the effective bits of la r depend on the capacity of local address space 1 as specified in pcilsr1. the effective bits are as follows: pcilsr1.ls1([28:20]) = 0 0000 0000 : effective bits are [31:20] pcilsr1.ls1([28:20]) = 0 0000 0001 : effective bits are [31:21] pcilsr1.ls1([28:20]) = 0 0000 0011 : effective bits are [31:22] | | pcilsr0.ls1([28:20]) = 0 1111 1111 : effective bits are [31:28] pcilsr1.ls1([28:20]) = 1 1111 1111 : effective bits are [31:29] 19 to 0 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 488 of 1286 rej09b0158-0100 (6) pci interrupt register (pciir) pciir records the source of an interrupt. when multiple interrupts occur, only the first source is registered. when an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r r r r r r/wc r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 mrd pei mw pdi mad im ta d im dpei tr dpei tw se di ape di mdei tmt oi ? ? ? ? ? tta di r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 15 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 14 ttadi 0 sh: r/wc pci: r target target-abort interrupt indicates that the pcic has terminated a transaction with a target-abort when the pcic functions as a target. a target-abort is detected as an illegal byte enable when the lower two bits (bits 1 and 0) of the address and the byte enable do not match during an i/o transfer (target). 0: target-abort interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: target-abort interrupt occurs [set condition] when a target-abort interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 489 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 to 10 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 9 tmtoi 0 sh: r/wc pci: r target memory read retry timeout interrupt when the pcic functions as a target, the master did not attempt a retry within the prescribed number of pciclk clocks (2 15 ) (detected only in the case of memory read operations). 0: target memory read retry timeout interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: target memory read retry timeout interrupt occurs [set condition] when a target memory read retry timeout interrupt occurs. 8 mdei 0 sh: r/wc pci: r master function disable error interrupt the pcic attempted a ma ster access when such accesses are disabled, that is, when pcicmd.bm is cleared to 0. 0: master function disable error interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master function disable error interrupt occurs [set condition] when a master function disable error interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 490 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 apedi 0 sh: r/wc pci: r address parity error detection interrupt indicates an address parity error has been detected. when both the per and serre bits in the pci command register are set to 1, an address parity error is detected. 0: address parity error detection interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: address parity error detection interrupt occurs [set condition] when an address parity error detection interrupt occurs. 6 sedi 0 sh: r/wc pci: r serr detection interrupt indicates that the assertion of the serr signal has been detected when the pcic operates in host bus bridge mode. 0: serr detection interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: serr detection interrupt occurs [set condition] when a serr detection interrupt occurs. 5 dpeitw 0 sh: r/wc pci: r data parity error inte rrupt for target write indicates that a data parit y error has been detected during a target write access (only detected when pcicmd.per is set to 1) when the pcic functions as a target. 0: data parity error detection interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: data parity error detection interrupt occurs [set condition] when a data parity error detection interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 491 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 peditr 0 sh: r/wc pci: r data parity error in terrupt for target perr indicates that the perr signal has been received during a target read access (only detected when pcicmd.per is set to 1) when the pcic functions as a target. 0: perr detection interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: perr detection interrupt occurs [set condition] when a perr detection interrupt occurs. 3 tadim 0 sh: r/wc pci: r target-abort detection interrupt for master when the pcic functions as a master, it has detected a target-abort, that is, the transaction is terminated. 0: target-abort interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: target-abort interrupt occurs [set condition] when a target-abort interrupt occurs. 2 madim 0 sh: r/wc pci: r master-abort interrupt for master indicates that the pcic has terminated a transaction with a master-abort when the pcic functions as a master. 0: master-abort interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master-abort interrupt occurs [set condition] when a master-abort interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 492 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 mwpdi 0 sh: r/wc pci: r master write perr detection interrupt indicates that the perr signal has been received during a master write access (only detected when pcicmd.per is set to 1) when the pcic functions as a master. 0: master write perr interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master write perr interrupt occurs [set condition] when a master write perr interrupt occurs. 0 mrdpei 0 sh: r/wc pci: r master read data pa rity error interrupt indicates that a data parit y error has been detected during a master read access (only detected when pcicmd.per is set to 1) when the pcic functions as a master. 0: master read data perity error interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master read data perity error interrupt occurs [set condition] when a master read data perity error interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 493 of 1286 rej09b0158-0100 (7) pci interrupt mask register (pciimr) this register is the mask register for pciir. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r/w r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 mrd peim mw pdim mad imm ta d imm dpei trm dpei twm se dim ape dim mde im tmt oim ? ? ? ? ? tta dim r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 15 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 14 ttadim 0 sh: r/w pci: r target target-abort interrupt mask 0: pciir.ttadi disabled (masked) 1: pciir.ttadi enabled (not masked) 13 to 10 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 9 tmtoim 0 sh: r/w pci: r target retry time out interrupt mask 0: pciir.tmtoi disabled (masked) 1: pciir. tmtoi enabled (not masked) 8 mdeim 0 sh: r/w pci: r master function disable error interrupt mask 0: pciir.mdei disabled (masked) 1: pciir.mdei enabled (not masked) 7 apedim 0 sh: r/w pci: r address parity error de tection interrupt mask 0: pciir.apedi disabled (masked) 1: pciir.apedi enabled (not masked)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 494 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 sedim 0 sh: r/w pci: r serr detection interrupt mask 0: pciir.sedi disabled (masked) 1: pciir.sedi enabled (not masked) 5 dpeitwm 0 sh: r/w pci: r data parity error interrupt mask for target write 0: pciir.dpeitw disabled (masked) 1: pciir.dpeitw enabled (not masked) 4 peditrm 0 sh: r/w pci: r perr detection interrupt mask for target read 0: pciir.peditr disabled (masked) 1: pciir.peditr enabled (not masked) 3 tadimm 0 sh: r/w pci: r target-abort interrupt mask for master 0: pciir.tadim disabled (masked) 1: pciir.tadim enabled (not masked) 2 madimm 0 sh: r/w pci: r master-abort interrupt mask for master 0: pciir.madim disabled (masked) 1: pciir.madim enabled (not masked) 1 mwpdim 0 sh: r/w pci: r master write data pari ty error interrupt mask 0: pciir.mwpdi disabled (masked) 1: pciir.mwpdi enabled (not masked) 0 mrdpeim 0 sh: r/w pci: r master read data pari ty error interrupt mask 0: pciir.mrdpei disabled (masked) 1: pciir.mrdpei enabled (not masked)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 495 of 1286 rej09b0158-0100 (8) pci error address inform ation register (pciair) this register records pci address info rmation when an error is detected. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r ? ? ? ? ? ? ? ? ? ail ? ? ? ? ? ?? r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r ? ? ? ? ? ? ? ? ? ail ? ? ? ? ? ?? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 0 ail undefined sh: r pci: r address information log this register holds address information (the states of the ad signals) when an error occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 496 of 1286 rej09b0158-0100 (9) pci error command information register (pcicir) this register records the pci command in formation when an error is detected. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 ?0 ? ? ? ? ? ? ? ? ? ? rw tet ? ? ? mtem ? r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r ? ? ? ? 0 0 0 0 0 0 0 0 0 0 00 ecl ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 mtem undefined sh: r pci: r master error indicates that an error has occurred during a master access. 0: master error does not occur 1: master error occurs 30 to 27 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 26 rwtet undefined sh: r pci: r target error indicates that an error has occurred during a target read or a target write access. 0: target error does not occur 1: target error occurs 25 to 4 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 3 to 0 ecl undefined sh: r pci: r command log hold pci command information (the state of the cbe[3:0] signal) when an error occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 497 of 1286 rej09b0158-0100 (10) pci arbiter interru pt register (pciaint) in host bus bridge mode, this register records source of an interrupt. when multiple interrupts occur, only the first source is registered. when an interrupt is disabled, source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/wc r/wc r/wc r/wc r r r r r r r r/wc r/wc r/wc rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wd pei rd pei mai ta i ? ? ? ? ? ? ? mb toi tb toi mbi ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 14 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 13 mbi 0 sh: r/wc pci: r master-broken interrupt an interrupt is detected when the pciframe signal is not asserted within 16 clo ck cycles, although the pcic gave a master the bus. 0: master-broken interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master-broken interrupt occurs [set condition] when a master-broken interrupt occurs.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 498 of 1286 rej09b0158-0100 bit bit name initial value r/w description 12 tbtoi 0 sh: r/wc pci: r target bus time-out interrupt an interrupt is detected when the trdy or stop signal is not asserted withi n 16 clock cycles on the first data transfer. an interrupt is detected when the trdy or stop signal is not asserted withi n eight clock cycles during the data transfer subs equent to the 2nd. 0: target bus time-out interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: target bus time-out interrupt occurs [set condition] when a target bus time-out interrupt occurs. 11 mbtoi 0 sh: r/wc pci: r master bus time-out interrupt an interrupt is detected when the irdy signal is not asserted within 8 clock cycles. 0: master bus time-out interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master bus time-out interrupt occurs [set condition] when a master bus time-out interrupt occurs. 10 to 4 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 499 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 tai 0 sh: r/wc pci: r target-abort interrupt indicates that a transaction is terminated with a target-abort when a device other than the pcic functions as a bus master. 0: target-abort interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: target-abort interrupt occurs [set condition] when a target-abort interrupt occurs. 2 mai 0 sh: r/wc pci: r master-abort interrupt indicates that a transaction is terminated with a master-abort when a device other than the pcic functions as a bus master. 0: master-abort interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: master-abort interrupt occurs [set condition] when a master-abort interrupt occurs. 1 rdpei 0 sh: r/wc pci: r read parity error interrupt the perr assertion is detected during a data read when a device other than the pcic functions as a bus master. 0: read parity error interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: read parity error interrupt occurs [set condition] when a read parity error interrupt is detected by the perr assertion.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 500 of 1286 rej09b0158-0100 bit bit name initial value r/w description 0 wdpei 0 sh: r/wc pci: r write parity error interrupt the perr assertion is detected during a data write when a device other than the pcic functions as a bus master. 0: write parity error interrupt does not occur [clear condition] write 1 to this bit (write clear). 1: write parity error interrupt occurs [set condition] when a write parity error interrupt is detected by the perr assertion. (11) pci arbiter interrupt mask register (pciaintm) this register is the mask register for pciaint. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r r r r r r r r/w r/w r/w rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wdp eim rdp eim maim ta i m ? ? ? ? ? ? ? mbt oim tbt oim mbim ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 14 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 501 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 mbim 0 sh: r/wc pci: r master-broken interrupt mask 0: pciaint.mbi disabled (masked) 1: pciaint.mbi enabled (not masked) 12 tbtoim 0 sh: r/wc pci: r target bus time-out interrupt mask 0: pciaint.tbtoi disabled (masked) 1: pciaint.tbtoi enabled (not masked) 11 mbtoim 0 sh: r/wc pci: r master bus time-out interrupt mask 0: pciaint.mbtoi disabled (masked) 1: pciaint.mbtoi enabled (not masked) 10 to 4 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 3 taim 0 sh: r/wc pci: r target-abort interrupt mask 0: pciaint.tai disabled (masked) 1: pciaint.tai enabled (not masked) 2 maim 0 sh: r/wc pci: r master-abort interrupt mask 0: pciaint.mai disabled (masked) 1: pciaint.mai enabled (not masked) 1 rdpeim 0 sh: r/wc pci: r read data parity error interrupt mask 0: pciaint.rdpei disabled (masked) 1: pciaint.rdpei enabled (not masked) 0 wdpeim 0 sh: r/wc pci: r write data parity error interrupt mask 0: pciaint.wdpei disabled (masked) 1: pciaint.wdpei enabled (not masked)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 502 of 1286 rej09b0158-0100 (12) pci arbiter bus master in formation register (pcibmir) in host bridge mode, this register records when the interrupt is invoked by pciaint. when multiple interrupts occur, only the first source is registered. when an interrupt is masked, the source is register ed in corresponding bit (set to 1), however, an interrupt occurs. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r r r ? ? ? ? ? 0 0 0 0 0 0 0 0 0 00 req0 bme req1 bme req2 bme req3 bme req4 bme ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 5 ? all 0 sh: r pci: r reserved these bits are always read as 0. the write value should always be 0. 4 req4bme undefined sh: r pci: r req4 error an error occurs when the pcic functions as a bus master. 3 req3bme undefined sh: r pci: r req3 error an error occurs when device 3 ( req3 ) functions as a bus master 2 req2bme undefined sh: r pci: r req2 error an error occurs when device 2 ( req2 ) functions as a bus master 1 req1bme undefined sh: r pci: r req1 error an error occurs when device 1 ( req1 ) functions as a bus master 0 req0bme undefined sh: r pci: r req0 error an error occurs when device 0 ( req0 ) functions as a bus master
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 503 of 1286 rej09b0158-0100 (13) pci pio address register (pcipar) this register is config uration address register. refer to section 13.4.5 (2), configuration space access. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 10 bn ? ? ? ? ? ? ccie ? r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? cra fn dn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 ccie 1 sh: r pci: ? configuration cycle issue enable enables a configurati on cycle to be issued. 1: indicates the configuration cycle generation enable 30 to 24 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 23 to 16 bn undefined sh: r/w pci: ? pci bus number specify the pci bus number for a configuration access. the pcic is connected to bus number 0. bus numbers ranging from 0 to 255 are represented in 8 bits.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 504 of 1286 rej09b0158-0100 bit bit name initial value r/w description 15 to 11 dn undefined sh: r/w pci: ? device number specify the device number for a configuration access. device numbers ranging from 0 to 31 are represented in five bits. a single bit of bits 31 to 16 of the ad signals is driven to high level instead of the idsel assertion. the bit driven to high level corresponds to the device number set in these bits. the correspondence between the device number and idsel (ad[31:16]) is shown below. if a device number is equal to h'10 or greater, all bits 31 to 16 of the ad signals are driven to low level. device no. idsel device no. idsel h'0: ad[16] = high level h'8: ad[24] = high level h'1: ad[17] = high level h'9: ad[25] = high level h'2: ad[18] = high level h'a: ad[26] = high level h'3: ad[19] = high level h'b: ad[27] = high level h'4: ad[20] = high level h'c: ad[28] = high level h'5: ad[21] = high level h'd: ad[29] = high level h'6: ad[22] = high level h'e: ad[30] = high level h'7: ad[23] = high level h'f: ad[31] = high level other than above ad[31:16] lines are driven to high level. 10 to 8 fn undefined sh: r/w pci: ? function number specify the function number for a configuration access. the function numbers ranging from 0 to 7 are represented in three bits. 7 to 2 cra undefined sh: r/w pci: ? configuration register address specify the register for a configuration access at a longword boundary. 1, 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 505 of 1286 rej09b0158-0100 (14) pci power management interrupt register (pcipint) this register controls the power management interrupt. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/wc r/wc r/wc r/wc r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pmd 0 pmd 1 pmd 2 pmd 3h ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 4 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 3 pmd3h 0 sh: r/wc pci: ? pci power management d3 hot status transition interrupt 0: interrupt request for a transition to d3 is not detected 1: interrupt request for a transition to d3 is detected 2 pmd2 0 sh: r/wc pci: ? pci power management d2 status transition interrupt 0: interrupt request for a transition to d2 is not detected 1: interrupt request for a transition to d2 is detected 1 pmd1 0 sh: r/wc pci: ? pci power management d1 status transition interrupt 0: interrupt request for a transition to d1 is not detected 1: interrupt request for a transition to d1 is detected 0 pmd0 0 sh: r/wc pci: ? pci power management d0 status transition interrupt 0: interrupt request for a transition to d0 is not detected 1: interrupt request for a transition to d0 is detected
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 506 of 1286 rej09b0158-0100 (15) pci power manage ment interrupt mask register (pcipintm) this is the mask register for pcipint. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w r/w r/w r/w r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pmd 0m pmd 1m pmd 2m pmd 3hm ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 4 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 3 pmd3hm 0 sh: r/w pci: ? pci power management d3 hot status transition interrupt mask 0: pcipint.pm d3h disabled (masked) 1: pcipint.pm d3h enabled (not masked) 2 pmd2m 0 sh: r/w pci: ? pci power management d2 status transition interrupt mask 0: pcipint.pmd2 disabled (masked) 1: pcipint.pmd2 enabled (not masked) 1 pmd1m 0 sh: r/w pci: ? pci power management d1 status transition interrupt mask 0: pcipint.pmd1 disabled (masked) 1: pcipint.pmd1 enabled (not masked) 0 pmd0m 0 sh: r/w pci: ? pci power management d0 status transition interrupt mask 0: pcipint.pmd0 disabled (masked) 1: pcipint.pmd0 enabled (not masked)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 507 of 1286 rej09b0158-0100 (16) pci memory bank register 0 (pcimbr0) this register specifies the upper 14-bit address of the pci memory space 0 (address bits 31 to 18). refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? pmsba0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 18 pmsba0 h'0000 sh: r/w pci: ? pci memory space 0 bank address specify the bank address in pci memory space 0 for a master access. 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 508 of 1286 rej09b0158-0100 (17) pci memory bank mask register 0 (pcimbmr0) this register specifies the si ze of the pci memory space 0. refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r rr r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? msbam0 ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 24 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 23 to 18 msbam0 000000 sh: r/w pci: ? pci memory space 0 bank address mask 0000 00 : 256 kbytes 0000 01 : 512 kbytes 0000 11 : 1 mbyte 0001 11 : 2 mbytes 0011 11 : 4 mbytes 0111 11 : 8 mbytes 1111 11 : 16 mbytes other than above: setting prohibited 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 509 of 1286 rej09b0158-0100 (18) pci memory bank register 1 (pcimbr1) this register specifies the upper 14-bit address of the pci memory space 1 (address bits 31 to 18). refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r rr r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmsba1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 18 pmsba1 all 0 sh: r/w pci: ? pci memory space 1 bank address specify the bank address in pci memory space 1 for a master access. 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 510 of 1286 rej09b0158-0100 (19) pci memory bank mask register 1 (pcimbmr1) this register specifies the size of the pci memory space 1. refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? r r r/w r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 msbam1 ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 26 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 25 to 18 msbam1 all 0 sh: r/w pci: ? pci memory space 1 bank address mask (8 bits) 00 0000 00: 256 kbytes 00 0000 01: 512 kbytes 00 0000 11: 1 mbyte 00 0001 11: 2 mbytes 00 0011 11: 4 mbytes 00 0111 11: 8 mbytes 00 1111 11: 16 mbytes 01 1111 11: 32 mbytes 11 1111 11: 64 mbytes other than above: setting prohibited 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 511 of 1286 rej09b0158-0100 (20) pci memory bank register 2 (pcimbr2) this register specifies the upper 14-bit address of the pci memory space 2 (address bits 31 to 18). refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r rr r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmsba2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 18 pmsba2 all 0 sh: r/w pci: ? pci memory space 2 bank address specify the bank address in pci memory space 2 for a master access. 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 512 of 1286 rej09b0158-0100 (21) pci memory bank mask register 2 (pcimbmr2) this register specifies the size of the pci memory space 2. refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r rr r/w r/w r/w r/w r/w r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msbam2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 29 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 28 to 18 msbam2 all 0 sh: r/w pci: ? pci memory space 2 bank address mask 0 0000 0000 00: 256 kbytes 0 0000 0000 01: 512 kbytes 0 0000 0000 11: 1 mbyte 0 0000 0001 11: 2 mbytes 0 0000 0011 11: 4 mbytes 0 0000 0111 11: 8 mbytes 0 0000 1111 11: 16 mbytes 0 0001 1111 11: 32 mbytes 0 0011 1111 11: 64 mbytes 0 0111 1111 11: 128 mbytes 0 1111 1111 11: 256 mbytes 1 1111 1111 11: 512 mbytes other than above: setting prohibited 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 513 of 1286 rej09b0158-0100 (22) pci i/o bank register (pciiobr) this register specifies the upper 14-bit address of the pci i/o space (address bits 31 to 18). refer to section 13.4.3 (3 ), accessing pci i/o space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r/w r/w r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r rr r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? piosba 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 18 piosba all 0 sh: r/w pci: ? pci i/o space bank address (14 bits) specify the bank address in pci i/o space for a master access. 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 514 of 1286 rej09b0158-0100 (23) pci i/o bank mask register (pciiobmr) this register specifies the size of the pci i/o space. refer to section 13.4.3 (2), accessing pci memory space. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? r r r r r r r r r r rr r r r/w r/w r/w r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iobamr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 21 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 20 to 18 iobamr all 0 sh: r/w pci: ? pci i/o space bank address mask (3 bits) 000: 256 kbytes 001: 512 kbytes 011: 1 mbyte 111: 2 mbytes other than above: setting prohibited 17 to 0 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 515 of 1286 rej09b0158-0100 (24) pci cache snoop control register 0 (pcicscr0) an external device can access local memory of th is lsi via the pcic. when an external pci device accesses cacheable areas of this lsi, the pc ic can support cache snoop function to the on- chip caches. the pcicscr0 specifies this functi on that uses cache snoop address registers 0. refer to section 13.4.4 (7), cache coherency. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 snpmd range r/w r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 5 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 4 to 2 range all 0 sh: r/w pci: ? address range to be compared specify the address range of pcicsar0 to be compared. 000: pcicsar[n].cadr[31:12] compared (4 kbytes) 001: pcicsar[n].cadr[31:16] compared (64 kbytes) 010: pcicsar[n].cadr[31:20] compared (1 mbyte) 011: pcicsar[n].cadr[31:24] compared (16 mbytes) 100: pcicsar[n].cadr[31:25] compared (32 mbytes) 101: pcicsar[n].cadr[31:26] compared (64 mbytes) 110: pcicsar[n].cadr[31:27] compared (128 mbytes) 111: pcicsar[n].cadr[31:28] compared (256 mbytes) valid only when pcicscr0.snpmd = 10 or 11.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 516 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1, 0 snpmd all 0 sh: r/w pci: ? snoop mode for pcicsar0 specify if pcicsar0 is compared with address requested by an external device. also, specify how snoop function is executed when pcicsar0 is compared. 00: pcicsar0 not compared 01: reserved (setting prohibited) 10: pcicsar0 compared. if hit, snoop function is not executed, otherwise executed. 11: pcicsar0 compared. if hit, snoop function is executed, otherwis e not executed.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 517 of 1286 rej09b0158-0100 (25) pci cache snoop control register 1 (pcicscr1) an external device can access local memory of th is lsi via the pcic. when an external pci device accesses cacheable areas of this lsi, the pc ic can support cache snoop function to the on- chip caches. the pcicscr1 specifies this functi on that uses cache snoop address registers 1. refer to section 13.4.4 (7), cache coherency. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 snpmd range r/w r r r r r r r r r rr r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: bit bit name initial value r/w description 31 to 5 ? all 0 sh: r pci: ? reserved these bits are always read as 0. the write value should always be 0. 4 to 2 range all 0 sh: r/w pci: ? address range to be compared specify the address range of pcicsar1 to be compared. 000: pcicsar[n].cadr[31:12] compared (4 kbytes) 001: pcicsar[n].cadr[31:16] compared (64 kbytes) 010: pcicsar[n].cadr[31:20] compared (1 mbyte) 011: pcicsar[n].cadr[31:24] compared (16 mbytes) 100: pcicsar[n].cadr[31:25] compared (32 mbytes) 101: pcicsar[n].cadr[31:26] compared (64 mbytes) 110: pcicsar[n].cadr[31:27] compared (128 mbytes) 111: pcicsar[n].cadr[31:28] compared (256 mbytes) valid only when pcicscr1.snpmd = 10 or 11.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 518 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1, 0 snpmd all 0 sh: r/w pci: ? snoop mode for pcicsar1 specify if pcicsar1 is compared with address requested by an external device. also, specify how snoop function is executed when pcicsar1 is compared. 00: pcicsar1 not compared 01: reserved (setting prohibited) 10: pcicsar1 compared. if hit, snoop function is not executed, otherwise executed. 11: pcicsar1 compared. if hit, snoop function is executed, otherwis e not executed.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 519 of 1286 rej09b0158-0100 (26) pci cache snoop address register 0 (pcicsar0) pcicsar0 specifies the address to be compared with the pci address requested by an external device. refer to section 13.4.4 (7), cache coherency. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cadr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cadr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? bit bit name initial value r/w description 31 to 0 cadr all 0 sh: r/w pci: ? address to be compared specify address to be compared with the pci address requested by external pci devices
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 520 of 1286 rej09b0158-0100 (27) pci cache snoop address register 1 (pcicsar1) pcicsar1 specifies the address to be compared with the pci address requested by an external device. refer to section 13.4.4 (7), cache coherency. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cadr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cadr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? bit bit name initial value r/w description 31 to 0 cadr all 0 sh: r/w pci: ? address to be compared specify address to be compared with the pci address requested by external pci devices
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 521 of 1286 rej09b0158-0100 (28) pci pio data register (pcipdr) when accessed, this register will cause the genera tion of a configuration cycle on the pci bus. refer to section 13.4.5 (2), configuration space access. sh r/w: pci r/w: sh r/w: pci r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: pdr pdr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit bit name initial value r/w description 31 to 0 pdr undefined sh: r/w pci: ? pci pio data register a read from or write to this register will cause a pci configuration cycl e on the pci bus.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 522 of 1286 rej09b0158-0100 13.4 operation 13.4.1 supported pci commands table 13.4 supported bus commands cbe[3:0] command type pci master pci target 0000 interrupt ackn owledge cycle no ? 0001 special cycle yes * 1 ? 0010 i/o read yes yes * 2 0011 i/o write yes yes * 2 0100 reserved ? ? 0101 reserved ? ? 0110 memory read yes yes 0111 memory write yes yes 1000 reserved ? ? 1001 reserved ? ? 1010 configuration read yes * 1 yes * 2 1011 configuration write yes * 1 yes * 2 1100 memory read multiple no partially yes * 3 1101 dual address cycle no no 1110 memory read line no partially yes * 3 1111 memory write and invalidate no partially yes * 4 [legend] 0: low level 1: high level notes: 1. only the host bus bridge mode is supported. 2. single transfer only is performed. 3. operation is the same as that for the memory read command. 4. operation is the same as t hat for the memory write command.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 523 of 1286 rej09b0158-0100 13.4.2 pcic initialization after a power-on reset, the pcic enable bit (enbl) of the pcic enable control register (pciecr) and the internal register initialization bit (cfinit) of the pci control register (pcicr) is cleared. at this point, if the pcic is operating as the pci bus host (host bus bridge mode), the bus privileges are permanently granted to the pcic, and no device arbitration is performed on the pci bus. when the pcic is not operating as host (n ormal mode), retries are returned without accepting access from pci external devices connected to th e pci bus. in addition, all accesses to the pcic from the cpu are invalid except the access to the pciecr if the pciecr.enbl is cleared to 0. a write access is invalid and a read access will read 0, none of the registers ca n be modified, and any access to the pci bus will not be executed. to initialize the pcic, first setting the enable bit in the pciecr to 1. the pcic's internal configuration registers and local registers must be initialized before setting the cfinit bit in the pcicr to 1 (while the cfinit bit is cleared to 0) . on completion of initialization, set the cfinit bit to 1. when operating as host, arbitration is en abled; when operating as non-host, the pcic can be accessed from the pci bus. regardless of whether the pcic is operating as th e host or normal, extern al pci devices cannot be accessed from the pcic while the cfinit bit is being cleared. set the cfinit bit to 1 before accessing an external pcic device. be sure to initialize the following registers while th e cfinit bit is being cleared (before setting to 1): pci command (pcicmd), pci status (pcistatus), pci sub system vender id (pcisvid), pci subsystem id (pcisid), pci local space regi ster 0/1 (pcilsr 0/1) and pci local address register 0/1.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 524 of 1286 rej09b0158-0100 13.4.3 master access this section describes how the pcic is accessed by software in this lsi and the restrictions on usage, such as buffering and synchronization with other devices, when the pcic is used in both the host bus bridge and normal modes. (1) address space of pcic table 13.5 shows the pcic address map. table 13.5 pcic address map physical address memory area 29-bit address mode 32-bit address extended mode * space size pci memory space1 (area 4) h'1000 0000 to h'13ff ffff h'1000 0000 to h'13ff ffff 64 mbytes pci memory space 2 (only 32-bit address extended mode) ? h'c000 0000 to h'dfff ffff 512 mbytes pci memory space 0 h'fd00 0000 to h'fdff ffff h'fd00 0000 to h'fdff ffff 16 mbytes control register h'fe00 0000 to h'fe03 ffff h'fe00 0000 to h'fe03 ffff 256 kbytes pcic internal register (configuration and local registers) h'fe04 0000 to h'fe07 ffff h'fe04 0000 to h'fe07 ffff 256 kbytes reserved h'fe08 0000 to h'fe1f ffff h'fe08 0000 to h'fe1f ffff 1.5 mbytes pci i/o space h'fe20 0000 to h'fe3f ffff h'fe20 0000 to h'fe3f ffff 2 mbytes note: * for details, see section 7.7, 32-bit address extended mode. the address space of the pcic is divided into four main spaces (six spaces, altogether): the control register space (pciecr), pci internal control regi ster (pci configuration and pci local registers) space, i/o space, and pci memory (pci memory space 0, pci memory space 1, and pci memory space 2).
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 525 of 1286 rej09b0158-0100 (2) accessing pci memory space figure 13.2 shows the method for accessing the pci bus allocated to the pci memory space from the superhyway bus. h'0000 0000 h'1000 0000 h'c000 0000 h'fd00 0000 h'fe00 0000 h'fe20 0000 superhyway bus address space (4gb) pci local bus address space (4gb) 16 mbytes 64 mbytes 512 mbytes pci memory space 1 64 mbytes pci memory space 2 512 mbytes pci memory space 0 16 mbytes register 2 mbytes pci i/o 2 mbytes figure 13.2 superhyway bus to pci local bus access to access to the pci memory addr ess space, use the pci memory bank register (pcimbr) and pci memory bank mask register (pcimbmr). these registers should have an address space ranging from 16 mbytes to 512 mbytes. pci addresses can be allocated to by software. the pcic supports burst tran sfers to memo ry transfer. consecutive accesses with the superhyway load 32-byte or superhyway store 32-byte command result in a burst transfer of 32-byte or more (64-byte, 96-byte, etc.). the pci memory spaces are allocated from h'fd 00 0000 to h'fdff ffff for pci memory space 0 (16 mbytes), h'1000 0000 to h'13ff ffff for pci memory space 1 (area 4, 64 mbytes, selection of the pcic, ddrif and lbsc spaces), and h'c000 0000 to h'dfff ffff for pci memory space 2 (512 mbytes, available only in 32-bit address extended mode). address translation from superhyway bus to pci local bus the lower 15 bits ([17:3]) of a superhyway bus address are sent without translation.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 526 of 1286 rej09b0158-0100 for pci memory space 0 accesses, bits 23 to 18 of a superhyway bus addr ess are controlled by pci memory bank mask register 0 (pcimbmr0). note: in the following items and figures, ?sh? means the superhyway bus of this lsi and ?pci? means the pci local bus. ? pcimbmr0 [23:18] b'1111 11: pci address [23:18] = sh address [23:18] ? pcimbmr0 [23:18] b'0111 11: pci address [23:18] = pcimbr0 [23], sh address [22:18] ? pcimbmr0 [23:18] b'0000 01: pci address [23:18] = pcimbr0 [23:19], sh address [18] ? pcimbmr0 [23:18] b'0000 00: pci address [23:18] = pcimbr0 [23:18] the upper eight bits ([31 :24]) of a superhyway bus address are replaced with bits 31 to 24 in pci memory bank register 0 (pcimbr0). 31 31 24 23 18 17 0 0 24 23 18 17 pcimbmr0 mask sh address msbam0 31 24 23 18 17 0 31 24 23 18 17 0 pcimbr0 pci address pmsba0 figure 13.3 superhyway bus to pci local bus address translation (pci memory space 0) for pci memory space 1 accesses, bits 25 to 18 of a superhyway address are controlled by pci memory bank mask register 1 (pcimbmr1). ? pcimbmr1 [25:18] b'11 1111 11: pci address [25:18] = sh address [25:18] ? pcimbmr1 [25:18] b'01 1111 11: pci address [25:18] = pcimbr1 [25], sh address [24:18] ? pcimbmr1 [25:18] b'00 0000 01: pci address [25:18] = pcimbr1 [25:19], sh address [18] ? pcimbmr1 [25:18] b'00 0000 00: pci address [25:18] = pcimbr1 [25:18] the upper six bits ([31:26]) of a superhyway bus address are replaced with bits 31 to 26 in pci memory bank register 1 (pcimbr1).
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 527 of 1286 rej09b0158-0100 31 31 26 25 18 17 0 0 26 25 18 17 pcimbmr1 sh address mask 31 26 25 18 17 0 31 26 25 18 17 0 pcimbr1 pci address msbam1 pmsba1 figure 13.4 superhyway bus to pci local bus address translation (pci memory space 1) for pci memory space 2 accesses, bits 28 to 18 of a superhyway address are controlled by the pci memory bank mask register 2 (pcimbmr2). ? pcimbmr2 [28:18] b'1 1111 1111 11: pci address [28:18] = sh address [28:18] ? pcimbmr2 [28:18] b'0 1111 1111 11: pci address [28:18] = pcimbr2 [28], sh address [27:18] ? pcimbmr2 [28:18] b'0 0000 0000 01: pci address [28:18] = pcimbr2 [28:19], sh address [18] ? pcimbmr2 [28:18] b'0 0000 0000 00: pci address [28:18] = pcimbr2[28:18] the upper three bits ([31:29]) of a superhyway bus address are replaced with bits 31 to 29 in pci memory bank register 2 (pcimbr2). 31 31 29 28 18 17 0 0 29 28 18 17 pcimbmr2 sh address mask 31 29 28 18 17 0 31 29 28 18 17 0 pcimbr2 pci address msbam2 pmsba2 figure 13.5 superhyway bus to pci local bus address translation (pci memory space 2)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 528 of 1286 rej09b0158-0100 (3) accessing pci i/o space access within the size of 4-byte. burst i/o transfers are not supported. the pci i/o address space is allocated from h' fd20 0000 to h'fe3f ffff (2 mbytes). address translation from superhyway bus to pci local bus the lower 15 bits ([17:3]) of a superhyway bus address are sent without translation. bits 20 to 18 of a superhyway bus address are controlled by the pci i/o bank mask register (pciiobmr). note: in the following item and figure, ?sh? mean s the superhyway bus of this lsi and ?pci? means the pci local bus. ? pciiomr0 [20:18] b'111: pci address [20:18] = sh address [20:18] ? pciiomr0 [20:18] b'011: pci address [20:18] = pciiobr [20], sh address [19:18] ? pciiomr0 [20:18] b'001: pci address [20:18] = pciiobr [20:19], sh address [18] ? pciiomr0 [20:18] b'000: pci address [20:18] = pciiobr [20:18] the upper 11 bits ([31:21 ]) of a superhyway bus address are re placed with bits 31 to 21 in the pci i/o bank register (pciiobr). 31 31 11111110001 21 20 18 17 0 0 21 20 18 17 pciiobmr 31 29 28 18 17 0 31 29 28 18 17 0 pciiobr sh address pci address mask iobam piosba figure 13.6 superhyway bus to pci local bus address translation (pci i/o)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 529 of 1286 rej09b0158-0100 (4) accessing internal registers of this lsi all internal registers, that is, pciecr, pci conf iguration registers, and pci local registers are accessible from the cpu. 4-byte, 2-byte, and byte transmission are supported. (5) endian the pcic of this lsi supports both the big endian and little endian formats. since pci local bus is inherently little endian, the pcic supports both byte swapping and non-byte swapping. the endian format is specified by the setting of the tbs bit in the pci control register (pcicr) at a reset. note: in the following figures, ?sh? means th e superhyway bus of this lsi and ?pci? means the pci local bus. ?msbyte? means the most significant byte and ?lsbyte? means the least significant byte.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 530 of 1286 rej09b0158-0100 31 0 sh data pci data 1. little endian a' b' c' d' a bc d buffer data a' b' c' d' a bc d a bc d pci address[2] = 1 pci address[2] = 0 msbyte 31 0 lsbyte msbyte lsbyte sh data pci data note: pci address [2]: ad[2] (address) 2. big endian a b c d a' b' c' d' buffer data a b c d a' b' c' d' a bc d pci address[2] = 0 pci address[2] = 1 figure 13.7 endian conversion from superhyway bus to pci local bus (non-byte swapping: tbs = 0)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 531 of 1286 rej09b0158-0100 31 0 a' b' c' d' a bc d a' b' c' d' a bc d a bc d pci address[2] = 1 pci address[2] = 0 msbyte 31 0 lsbyte msbyte lsbyte d c b a d' c' b' a' abc d a' b' c' d' a bc d pci address[2] = 1 pci address[2] = 0 sh data pci data 1. little endian buffer data sh data pci data 2. big endian buffer data note: pci address [2]: ad[2] (address) figure 13.8 endian conversion from superhyway bus to pci local bus (byte swapping: tbs = 1)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 532 of 1286 rej09b0158-0100 13.4.4 target access this section describes how the pcic of this lsi is accessed by an external pci local bus master when the pcic is used in both the host bus bridge and normal modes. (1) accessing this lsi address space accesses to the address space of this lsi by an external pci bus master are described here. h'0000 0000 memory base 0 local address space 0 (base 0) local address space 1 (base 1) i/o space (4 mbytes) memory base 1 i/o base 1 pci i/o space pci local bus address space (4 gbytes) superhyway bus address space (4 gbytes) h'ffff ffff h'0000 0000 h'ffff ffff h'fe00 0000 h'fe3f ffff figure 13.9 pci local bus to superhyway bus memory map
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 533 of 1286 rej09b0158-0100 to access the address space of this lsi, us e the pci memory base address register (pcimbar0/1), pci local space register (pcilsr0/1), and pci local address register (pcilar0/1). the address spaces are mapped by software. th e pcic includes two memory mapping registers. setting these two registers enables the use of two spaces. the size of these address spaces are selectable from 1 mbyte to 512 mbytes by setting the pci local space register (pcilsr0/1). single longword and burst transfers are supported for the memory data transfer to a pci target. a certain range of the address space on the pci lo cal bus corresponds to th e local address space on the superhyway bus. the local address space 0 is controlled by the pcimbar0, pcilsr0 and pcilar0. and the local address space 1 is controlled by the pcimbar1, pcilsr1 and pcilar1. figure 13.10 sh ows the method of accessing the local address space. the pcimbar0/1 indicates the star ting address of the memory space used by the pci device. the pcilar0/1 specifies the starti ng address of the local address space 0/1. the pcilsr0/1 expresses the size of the memo ry used by the pci device. address translation from pci local bus to superhyway bus for the pcimbar0/1 and pcilar0/1, the more signi ficant address bits that are higher than the memory size set in the pcilsr0/1 becomes valid . the more significant address bits of the pcimbar0/1 and the same field lin e bits of the pci local bus addr ess output from an external pci device are compared for the purpose of dete rmining whether the access is made to the pcic. when the addresses correspond, the access to the pcic is recognized, and a local address is generated from the more significant address bits of the pcilar0/1 and the less significant bits of the pci local bus address output from the external pci device. th e pci command is executed for this local address. if the more significant address bits of the pci local bus address output from the external pci device does not correspond with the more significant address bits of the pcimbar0/1, the pcic does not respond to the pci command. note: in the following figures, ?sh? means th e superhyway bus of this lsi and ?pci? means the pci local bus.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 534 of 1286 rej09b0158-0100 sh address pcilar0/1 pci address compare 31 20 19 2928 0 pcimbar0/1 31 2019 29 28 0 000 001 100 0 pcilsr0/1 31 2019 2928 0 1 31 2019 2928 0 31 2019 2928 0 lar mba (upper) 0/1 figure 13.10 pci local bus to superhyway bus address translation (local address space 0/1) when all the mbare bits in pcilsr0/1 are 0, the pci local bus address is sent to the superhyway bus without translation. data prefetching for memory read commands is supported. when a pci burst read is performed, 8 bytes, or 32 bytes of data block is prefetched. (this depends on the settings of the pfe and pfcs bits in pcicr). (2) accessing pcic i/o space allocate a 256-byte area to the i/o address space. address translation from pci local bus to superhyway bus the lower 8 bits ([7:0]) are sent to the superhyway bus without translation. when bits 31 to 8 of a pci local bus address match bits 31 to 8 in a pci i/o base address register (pciibar), the upper 24 bits of a pci local bus address are replaced with h'fe04 01.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 535 of 1286 rej09b0158-0100 31 8 7 0 pci address 31 8 7 0 pciibar 31 8 7 0 sh address h'fe04 01 iob (upper) compare figure 13.11 pci local bus to superhyway bus address translation (pcic i/o space) (3) accessing pcic registers configuration registers: access the configuration registers using an offset from the pci configuration register space base address with the configuration read or write command. only a single access which size should be unde r longword is performed. if a bu rst transfer is attempted, it is terminated to end the transaction. local registers: access the local registers using an offset from a pci local register space base address with the i/o read or i/o write command. on ly a single longword access is performed. if a burst transfer is attempted, it is terminated to end the transaction. control register (pciecr): do not read or write access to the pciecr from the pci local bus. (4) access to this lsi address space memory space: refer to section 13.4.4 (1 ), accessing this lsi addr ess space. area 0 to area 2 and area 4 to area 6 and ddr- sdram space on this lsi ad dress space can be accessed. on-chip io space: do not read or write access to the on -chip io space using memory read or memory write command via pci local bus. the operation of this read/write is not guaranteed.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 536 of 1286 rej09b0158-0100 (5) exclusive access the lock access on the pc i bus is supported. when the pci local bus is locked, the pcic is accessible from the device that activates the lock signal. superhyway bus resource lock does not occur. (another on-chip module can access the pcic during a lock transfer.) (6) endian this lsi supports both the big and little endian formats. since the pci local bus is inherently little endian, the pcic supports both byte swapping and non-byte swapping. the endian format is specified by the setting of the tbs bit in the pci control register (pcicr). note: in the following figures, ?msbyte? mean s the most significant byte and ?lsbyte? means the least significant byte.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 537 of 1286 rej09b0158-0100 31 msbyte lsbyte msbyte lsbyte 0 pci data sh data 1. little endian a' b' c' d' a bc d buffer data a' b' c' d' a bc d a bc d pci address[2] = 1 pci address[2] = 0 31 0 pci data sh data a b c d a' b' c' d' buffer data a b c d a' b' c' d' a bc d pci address[2] = 0 pci address[2] = 1 2. big endian note: pci address [2]: ad[2] (address) figure 13.12 endian conversion from pci local bus to superhyway bus (non-byte swapping: tbs = 0)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 538 of 1286 rej09b0158-0100 31 msbyte lsbyte msbyte lsbyte 0 a' b' c' d' a bc d a' b' c' d' d bc d a bc d pci address[2] = 1 pci address[2] = 0 31 0 d c b a d' c' b' a' d c b a d' c' b' a' a bc d pci address[2] = 0 pci address[2] = 1 pci data sh data 1. little endian buffer data pci data sh data buffer data 2. big endian note: pci address [2]: ad[2] (address) figure 13.13 endian conversion from pci local bus to superhyway bus (non-byte swapping: tbs = 1)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 539 of 1286 rej09b0158-0100 (7) cache coherency the pcic supports cache snoop function. when the pcic functions as a target device, cache coherency is guaranteed for accesses from a master device connected to a pci bus in both the host bus bridge mode and normal mode. when accessing this lsi cacheable area, set th e cache snoop registers: the pci cache snoop control registers (pcicscr0 and pcicscr1) and pci cache snoop address register (pcicsar0 and pcicsar1). usage notes ? up to 2 conditions can be set as snoop address. address comparison is logical or of setting 2 conditions. ? when using this function, execute memory read or write after flush/purge request issued to the cpu cache in the access of cache hit. it reduces pci bus transfer speed and cpu performance. ? when using this function, do not use the prefetch function. (do not set pfe bit in the pcicr to 1.) ? do not use this function when the cpu is sleep st ate. if cache hit occurs in sleep state, it becomes an error access on the superhyway bus, and memory read or me mory write does not execute. specify the snpmd bit in the pcicscr to 00 before the cpu enters sleep mode. to keep the coherency before and after the cpu sleep, cache purge should be executed before sleep instruction executed. ? do not use ether of the following functions and the cache shoop fu nction simultaneously. ? debug function using an emulator (disable this function when using an emulator). ? l memory or memory mapped cache access from the dmac.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 540 of 1286 rej09b0158-0100 pci address superhyway address cache snoop address register cache snoop control register set issue the flush/purge issue the read/write issue the read/write compare hit no hit figure 13.14 cache flush/pu rge execution flow for pci lo cal bus to superhyway bus
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 541 of 1286 rej09b0158-0100 13.4.5 host bus bridge mode (1) pci host bus bridge mode operation the pcic supports a subset of the pci local bu s specification revision 2.2 and can be connected to a device with a pci bus interface. while the pcic is set in host bus bridge mode, or while set in normal mode, operation differs according to whether or not bus parking is performed, and whet her or not the pci bus arbiter function is enabled or not. in host bus bridge mode, the ad, cbe, par signal lines are driven by the pcic when transfers are not being performed on the pci bus. when the pcic subsequently starts transfers as master, these signal lines continue to be driven until the end of the address phase. the arbiter in the pcic and the req and gnt betw een pcic are connected internally. here, pins req0 / reqout , req1 , req2 , and req3 function as the req inputs from the external masters 0 to 3. similarly, gnt0 / gntin , gnt1 , gnt2 , and gnt3 function as the gnt outputs to external masters 0 to 3. including the pcic, arb itration of up to five masters is possible. (2) configuration space access the pcic supports configuration mechanism #1. the pci pio address register (pcipar) and pci pio data register (pcipdr) corr espond to the configuration addr ess register and configuration data register, respectively. when pcipdr is read from or written to after pcipar has been set, a configuration cycle is issued on a pci bus. for a type 0 transfer, bits 10 to 2 of the configuration address register are sent without translation and bits 31 to 11 are transl ated so that these bits can be used as the idsel signal. bit 16 of the ad signal is driven to 1 and the other bits are made 0 by setting the device number to 0. bit 17 of the ad signal is driven to 1 and the other bits are made 0 by setting the device number to 1. similarly, setting the device number to 2 drives bit 18 of the ad signal to 1 and setting the device number to 3 drives bit 19 of the ad signal to 0. bit 31 of the ad signal is driven to 1 and the other bits are made 0 by setting the device number to 16. for details, refer to "pci local bus specification revision 2.2, section 3.2.2.3 configuration space decoding".
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 542 of 1286 rej09b0158-0100 31 30 24 23 16 15 11 10 8 7 2 1 0 31 11 10 16 15 8 7 2 1 0 configuration address register (pcipar) ccie reserved bn dn fn cra only one '1' 00000 00 00 pci local bus address (ad31 to ad0) figure 13.15 address generation for type 0 conf iguration access in configuration accesses, a pci master abort (n o device connected) will not cause an interrupt. configuration writes will end normally. conf iguration reads will return a value of 0. (3) special cycle generation when the pcic operates as the host device, a special cycle is generated by setting h'8000 ff00 in the pcipar and writing to the pcipdr. (4) arbitration in host bus bridge mode, the pci bus arbiter in the pcic is activated. the pcic supports four external masters (i.e., four req and gnt pairs). if use of the bus is simultaneously requested by more than one device, the bus is granted to the device with the highest priority. the pci bus arbiter supports two modes to determine the priority of devices: fixed priority and pseudo-round-robin. the mode is selected by the bmam bit in pcicr. fixed priority: when the bmam bit in pcicr is cleared to 0, the priorities of devices are fixed the following default values. pcic > device 0 > device 1 > device 2 > device 3 the pcic always gains use of the bus over other devices. pseudo-round-robin: when the bmam bit in pcicr is se t to 1, the most recently granted device is assigned the lowest priority. the initial priority is the same as the fixed priority mode.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 543 of 1286 rej09b0158-0100 after device 1 has claimed and granted the bus, an d transferred data, the pr iority is as follows: pcic > device 0 > device 2 > device 3 > device 1 then, after the pcic has claimed and granted the bus, and transferred data, the priority is changed to: device 0 > device 2 > device 3 > device 1 > pcic after device 3 has claimed and granted the bus, and transferred data, the priority is changed to: device 0 > device 2 > device 1 > pcic > device 3 in host bus bridge mode, bus parking is always controlled by the pcic. (5) interrupts ? 10 interrupts are available (these signals are connected to the intc of this lsi) ? interrupts are enabled/disabled and their priority levels are specified by the intc of this lsi ? when the pcic operates normal mode, inta output is available to the host device on the pci bus. the inta pin is specified assert or negate by the iocs bit in the pcicr. table 13.6 interrupt priority signal interrupt source priority pciserr serr assertion detected in host bus bridge mode high pciinta pci interrupt a ( inta ) detected in host bus bridge mode pciintb pci interrupt b ( intb ) detected in host bus bridge mode pciintc pci interrupt c ( intc ) detected in host bus bridge mode pciintd pci interrupt d ( intd ) detected in host bus bridge mode pcieer error on pci bus occurs and reflected in pciir and pciaint. the interrupt can be masked. pcipwd3 power state transition to d3 caused by pcipint. the interrupt can be masked. pcipwd2 power state transition to d2 caused by pcipint. the interrupt can be masked. pcipwd1 power state transition to d1 caused by pcipint. the interrupt can be masked. pcipwd0 power state transition to d0 caused by pcipint. the interrupt can be masked. low
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 544 of 1286 rej09b0158-0100 the pcic can store the error information on the pci bus. if an error occurs, the error address is stored in the pci error address information register (pciair), the types of transfer and command information are stored in the pci error comman d information register. and then if the pcic operates host bus bridge mode, the bus master info rmation is stored in the pci error bus master information register. error information is stored only one information. this causes only to store the first occurred error information, and not to store after second error in formation. the error information is initialized by a power-on reset. 13.4.6 normal mode when operating in normal mode, the pci bus arbitration function in the pcic is disabled and pci bus arbitration is performed according to the specifications of the externally connected pci bus arbiter. in normal mode, the master performs bus parking is decided by the grant si gnal that asserted from the external bus arbiter. if the master that performing bus parking is different from the next transaction master, the bus will be high-impedance state for minimum one clock cycle before the address phase. in normal mode, the gnt0 / gntin pin is used for the grant input signal to the pcic, and the req0 / reqout pin is used for the request output signal from the pcic. 13.4.7 power management the pcic supports pci power management revision 1.1. supported features are shown below. ? support for the pci power management control configuration register. ? support for the power-down/restore request interrupts from hosts on the pci bus. there are seven configuration registers for pci power management control. pci capabilities pointer register shows the address offset of the configuration registers for power management. in the pcic, this offset is fixed at cp = h'40. pci capability id (pcicid), next item pointer (pcinip), power management capability (pci pmc), power management control/status (pcipmcsr), pmcsr bridge support extension (pcipmcsrbse) and power consumption/dissipation (pcipcdd) are power management registers. they support four states: power state d0 (normal) power stat e d1 (bus idle) power state d2 (clock stop) and power state d3 (power down mode). figure 13.16 shows the pci local bus power down state transition.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 545 of 1286 rej09b0158-0100 d0 (normal) d2 (clock stop) d1 (bus idle) d3 (power down) figure 13.16 pci local bus power down state transition the pcic detects when the powe r state (ps) bit of the pci power management control/status register changes (when it is written to from an external pci device), and issues a power management interrupt. to control the power management interrupts, there are the pci power management interrupt register (pcipint) and pci power management interrupt mask register (pcipintm). of the power management interrupt s, the power state d0 interrupt (pcipwd0) detects a transition from the power state d1/d 2/d3 to d0, while power state d1 interrupt (pcipwd1) detects a transition from the power st ate d0 to d1, while power state d2 interrupt (pcipwd2) detects a transi tion from the power state d0/d1 to d2, while power state d3 interrupt (pcipwd3) detects a transi tion from the power state d0/d1/d2 to d3. interrupt masks can be set for each interrupt. no power state d0 interrupt is generated at a power-on reset. the following cautions should be noted when the pcic is operating in normal mode and a power down interrupt is received from the host: in pc i power management, the pci local bus clock stops within a minimum of 16 clocks after the host device has instructed a transition to power state d3. after detecting a power state d3 interrupt, do not , therefore, attempt to read or write to local registers and configuration regi sters that can be accessed from the superhyway bus and pci local bus access (i/o and memory spaces). because th ese accesses operate using the pci local bus clock, the cycle for these accesses will not be completed if the clock stops and may be hung-up on the superhyway bus. 13.4.8 pci local bus basic interface the pcic of this lsi conforms to the pci local bus specification revision 2.2 stipulations and can be connected to a device with a pci local bus in terface. the following figu res show the timing for each operation mode.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 546 of 1286 rej09b0158-0100 (1) master read/write cycle timing figures13.17 is an example of a single-write cycle in host bus bridge mode. figure 13.18 is an example of a single read cycle in host bus bridge mode. figure 13.19 is an example of a burst write cycle in normal mode. and figure 13.20 is an example of a burst read cycle in normal mode. note that the response speed of devsel and trdy differs according to the connected target device. in host bus bridge mode , master accesses always use single read/write cycles. the issuing of configuration transfers is only possible in host bus bridge mode. pciclk ad[31:0] pa r cbe[3:0] (c/ be[3:0] ) pciframe irdy devsel trdy lock idsel req gnt [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable d0 addr dp0 ap be0 com figure 13.17 master write cycle in host bus bridge mode (single)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 547 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy lock idsel req gnt d0 dp0 addr ap be0 com cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.18 master read cycle in host bus bridge mode (single)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 548 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy lock idsel req gnt ap com addr d0 d1 dn be0 be1 ben dp0 dpn dpn-1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.19 master write cy cle in normal mode (burst)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 549 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy lock idsel req gnt ap com addr d0 d1 dn be0 be1 ben dp0 dpn dpn-1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.20 master read cycle in normal mode (burst)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 550 of 1286 rej09b0158-0100 (2) target read/write cycle timing the pcic responds to target memo ry burst read accesses from an external master by retries until 8 longword (32-bit) data are prepared in the pcic's internal fifo. that is, it always responds to the first target burst read with a retr y. for a single read access, the pcic reaponds as soon as the data is prepared. also, when a target memory write access is made, the content of th e data is guaranteed until the write data is completely written to the local memory if reading the target write data immediately after write access. only single transfers are supported in the case of target accesses of the configuration space and i/o space. if there is a burst access request, the ex ternal master is disconnected on completion of the first transfer. note that the devsel response speed is fixed at 2 clocks (medium) in the case of target access to the pcic. figure 13.21 shows an example ta rget single read cycle in norm al mode. figure 13.22 shows an example target single write cycl e in normal mode. figure 13.23 is an example of a target burst read cycle in host bus bridge mode. and figure 13.2 4 is an example of a targ et burst write cycle in host bus bridge mode.
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 551 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy stop lock idsel reqout gntin addr ap d0 dp0 com locked at configuration access disconnect be0 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.21 target read cy cle in normal mode (single)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 552 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy stop lock idsel reqout gntin addr ap d0 dp0 com be0 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable locked at configuration access disconnect figure 13.22 target write cy cle in normal mode (single)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 553 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy stop lock idsel req gnt addr ap d0 dp0 com be0 d1 dn ben dpn dpn-1 be1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable locked disconnect figure 13.23 target memo ry read cycle in host bus bridge mode (burst)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 554 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy stop lock idsel req gnt addr ap d0 dp0 com be0 d1 dn ben dpn dpn-1 be1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable locked disconnect figure 13.24 target memory write cy cle in host bus bridge mode (burst)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 555 of 1286 rej09b0158-0100 (3) address/data stepping timing by writing 1 to the sc bit in pcicmd, a wait (stepping) of one clock can be inserted when the pcic is driving the ad bus. as a result, the pcic drives the ad bus over 2 clocks. this function can be used when there is a heavy load on th e pci bus and the ad bus does not achieve the stipulated logic level in one clock. when the pcic operates as the host bus bridge mode, it is recommended to use this function for the issuance of config uration transfers. figure 13.25 is an example of burst memory write cycle with stepping. figu re 13.26 is an example of target burst read cycle with stepping. pciclk ad[31:0] pa r pciframe irdy devsel trdy addr d0 dn com be0 ben ap dp0 dpn dpn-1 d1 be1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.25 master write cy cle in host bus bridge mode (burst, with stepping)
section 13 pci controller (pcic) rev.1.00 dec. 13, 2005 page 556 of 1286 rej09b0158-0100 pciclk ad[31:0] pa r pciframe irdy devsel trdy addr d1 d0 com be0 ben ap dn dpn dp0 dpn-1 be1 cbe[3:0] (c/ be[3:0] ) [legend] addr: ap: com: dn: dpn: ben: pci space address address parity command nth data nth data parity nth data byte enable figure 13.26 target memory read cycle in host bus bridge mode (burst, with stepping)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 557 of 1286 rej09b0158-0100 section 14 direct memory access controller (dmac) this lsi includes the direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (dma transfer end notification), external memory, on-chip memory, memory-mapped external devices, and peripheral modules. 14.1 features ? twelve channels (four channels can receive an external request: channel 0 to 3) ? 4-gbyte physical address space ? data transfer unit is selectable: byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32 bytes ? maximum transfer count: 16,777,216 transfers ? address mode: dual address mode ? transfer requests: external request (channel 0 to 3), peripheral module request (channel 0 to 5), or auto request can be selected. the following modules can issue an peripheral module request. ? scif0, scif1, hac, hspi, siof, ssi, flctl, and mmcif ? selectable bus modes: cycle steal mode (normal mode and intermittent mode) or burst mode can be selected. ? selectable channel priority levels: the channel priority levels are selectable between fixed mode and round-robin mode. ? interrupt request: an interrupt request can be ge nerated to the cpu after half of the transfers ended, all transfers ended, or an address error occurred. ? external request detection: there are following four types of dreqn input detection. (n = 0 to 3) ? low level detection (initial value) ? high level detection ? rising edge detection ? falling edge detection ? transfer end notification signal: active levels for both dackn and drakn can be set independently. (n = 0 to 3, initial value: low active)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 558 of 1286 rej09b0158-0100 figure 14.1 shows the block diagram of the dmac. iteration control dmac channels 6 to 11 dmac sarm darm tcrm chcrm dmaor1 sarbn darbn tcrbn register control start-up control request priority control bus interface iteration control dmac channels 0 to 5 sarm darm tcrm chcrm dmaor0 dmars0-2 sarbn darbn tcrbn register control start-up control request priority control bus interface on-chip memory peripheral module interrupt controller peripheral bus bridge peripheral bus dma transfer request signal dmintm [legend] m: 0,1,2,3,4,5 for channels 0 to 5; 6,7,8,9,10,11 for channels 6 to 11 n: 0,1,2,3 for channels 0 to 5; 6,7,8,9 for channels 6 to 11 note: * the half-end interrupt request is available in channels 0 to 3. chcrm: darbn: darm: dmae: dmaor0 and dmaor1: dma channel control register dma destination address register b dma destination address register dma address error interrupt request dma operation registers 0 and 1 dmars0 to dmars2: dmintm: sarbn: sarm: tcrbn: tcrm: dma extended resource selectors 0 to 2 dma transfer end/half-end interrupt request from channel m * dma source address register b dma source address register dma transfer count register b dma transfer count register dmae dmintm dreq0 to dreq3 drak0 to drak3 dack0 to dack3 dma transfer acknowledge signal external rom external ram external i/o (memory mapped) local bus state controller ddr-sdram interface pci controller external i/o (with acknowledge- ment) superhyway bus figure 14.1 block diagram of dmac
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 559 of 1286 rej09b0158-0100 14.2 input/output pins the external pins for the dmac are described below. table 14.1 lists the configuration of the pins that are connected to external device. the dmac ha s pins for four channels (channel 0 to 3) for external bus use. table 14.1 pin configuration channel pin name function i/o description dreq0 * 1 * 3 dma transfer request input dma transfer request input from external device to channel 0 drak0 * 2 * 4 dreq0 acceptance confirmation output notifies acceptance of dma transfer request and start of execution from channel 0 to external device 0 dack0 * 2 * 5 dma transfer end notification output strobe output from channel 0 to external device which has output, regarding dma transfer request dreq1 * 1 * 6 dma transfer request input dma transfer request input from external device to channel 1 drak1 * 2 * 7 dreq1 acceptance confirmation output notifies acceptance of dma transfer request and start of execution from channel 1 to external device 1 dack1 * 2 * 8 dma transfer end notification output strobe output from channel 1 to external device which has output, regarding dma transfer request dreq2 * 1 * 9 dma transfer request input dma transfer request input from external device to channel 2 drak2 * 2 * 10 dreq2 acceptance confirmation output notifies acceptance of dma transfer request and start of execution from channel 2 to external device 2 dack2 * 2 * 11 dma transfer end notification output strobe output from channel 2 to external device which has output, regarding dma transfer request
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 560 of 1286 rej09b0158-0100 channel pin name function i/o description dreq3 * 1 * 12 dma transfer request input dma transfer request input from external device to channel 3 drak3 * 2 * 13 dreq3 acceptance confirmation output notifies acceptance of dma transfer request and start of execution from channel 3 to external device 3 dack3 * 2 * 14 dma transfer end notification output strobe output from channel 3 to external device which has output, regarding dma transfer request notes: 1. initial value is low level detection. 2. initial value is low active. 3. this pin is multiplexed with port k7 (gpio) input/output pin. 4. this pin is multiplexed with mode2 input pin and port l1 (gpio) output pin. 5. this pin is multiplexed with mode0 input pin and port l3 (gpio) output pin. 6. this pin is multiplexed with port k6 (gpio) input/output pin. 7. this pin is multiplexed with mode7 input pin and port l0 (gpio) output pin. 8. this pin is multiplexed with mode1 input pin and port l2 (gpio) output pin. 9. this pin is multiplexed with intb (pcic) input pin, audata0 (h-udi) output pin, and port k5 (gpio) input/output pin. 10. this pin is multiplexed with ce2a (lbsc) output pin, audck (h-udi) output pin, and port k1 (gpio) output pin. 11. this pin is multiplexed with mresetout (reset) output pin, audata2 (h-udi) output pin, and port k3 (g pio) input/output pin. 12. this pin is multiplexed with intc (pcic) input pin, audata1 (h-udi) output pin, and port k4 (gpio) input/output pin. 13. this pin is multiplexed with ce2b (lbsc) output pin, audsync output pin, and port k0 (gpio) output pin. 14. this pin is multiplexed with irqout (intc) output pin, auda ta3 (h-udi) output pin, and port k2 (gpio) input/output pin.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 561 of 1286 rej09b0158-0100 14.3 register descriptions table 14.2 shows the configuration of registers of the dmac. table 14.3 shows the register states in each processing mode. table 14.2 register co nfiguration of dmac channel name abbrev. r/w p4 address area 7 address access size * 3 0 dma source address register 0 sar0 r/w h'fc80 8020 h'1c80 8020 32 dma destination address register 0 dar0 r/w h'fc80 8024 h'1c80 8024 32 dma transfer count register 0 tcr0 r/w h'fc80 8028 h'1c80 8028 32 dma channel control register 0 chcr0 r/w * 1 h'fc80 802c h'1c80 802c 32 1 dma source address register 1 sar1 r/w h'fc80 8030 h'1c80 8030 32 dma destination address register 1 dar1 r/w h'fc80 8034 h'1c80 8034 32 dma transfer count register 1 tcr1 r/w h'fc80 8038 h'1c80 8038 32 dma channel control register 1 chcr1 r/w * 1 h'fc80 803c h'1c80 803c 32 2 dma source address register 2 sar2 r/w h'fc80 8040 h'1c80 8040 32 dma destination address register 2 dar2 r/w h'fc80 8044 h'1c80 8044 32 dma transfer count register 2 tcr2 r/w h'fc80 8048 h'1c80 8048 32 dma channel control register 2 chcr2 r/w * 1 h'fc80 804c h'1c80 804c 32 3 dma source address register 3 sar3 r/w h'fc80 8050 h'1c80 8050 32 dma destination address register 3 dar3 r/w h'fc80 8054 h'1c80 8054 32 dma transfer count register 3 tcr3 r/w h'fc80 8058 h'1c80 8058 32 dma channel control register 3 chcr3 r/w * 1 h'fc80 805c h'1c80 805c 32 0 to 5 dma operation register 0 dmaor0 r/w * 2 h'fc80 8060 h'1c80 8060 16 4 dma source address register 4 sar4 r/w h'fc80 8070 h'1c80 8070 32 dma destination address register 4 dar4 r/w h'fc80 8074 h'1c80 8074 32 dma transfer count register 4 tcr4 r/w h'fc80 8078 h'1c80 8078 32 dma channel control register 4 chcr4 r/w * 1 h'fc80 807c h'1c80 807c 32 5 dma source address register 5 sar5 r/w h'fc80 8080 h'1c80 8080 32 dma destination address register 5 dar5 r/w h'fc80 8084 h'1c80 8084 32 dma transfer count register 5 tcr5 r/w h'fc80 8088 h'1c80 8088 32 dma channel control register 5 chcr5 r/w * 1 h'fc80 808c h'1c80 808c 32
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 562 of 1286 rej09b0158-0100 channel name abbrev. r/w p4 address area 7 address access size * 3 0 dma source address register b0 sarb0 r/w h'fc80 8120 h'1c80 8120 32 dma destination address register b0 darb0 r/w h'fc80 8124 h'1c80 8124 32 dma transfer count register b0 tcrb0 r/w h'fc80 8128 h'1c80 8128 32 1 dma source address register b1 sarb1 r/w h'fc80 8130 h'1c80 8130 32 dma destination address register b1 darb1 r/w h'fc80 8134 h'1c80 8134 32 dma transfer count register b1 tcrb1 r/w h'fc80 8138 h'1c80 8138 32 2 dma source address register b2 sarb2 r/w h'fc80 8140 h'1c80 8140 32 dma destination address register b2 darb2 r/w h'fc80 8144 h'1c80 8144 32 dma transfer count register b2 tcrb2 r/w h'fc80 8148 h'1c80 8148 32 3 dma source address register b3 sarb3 r/w h'fc80 8150 h'1c80 8150 32 dma destination address register b3 darb3 r/w h'fc80 8154 h'1c80 8154 32 dma transfer count register b3 tcrb3 r/w h'fc80 8158 h'1c80 8158 32 0, 1 dma extended resource selector 0 dmars0 r/w h'fc80 9000 h'1c80 9000 16 2, 3 dma extended resource selector 1 dmars1 r/w h'fc80 9004 h'1c80 9004 16 4, 5 dma extended resource selector 2 dmars2 r/w h'fc80 9008 h'1c80 9008 16 6 dma source address register 6 sar6 r/w h'fc81 8020 h'1c81 8020 32 dma destination address register 6 dar6 r/w h'fc81 8024 h'1c81 8024 32 dma transfer count register 6 tcr6 r/w h'fc81 8028 h'1c81 8028 32 dma channel control register 6 chcr6 r/w * 1 h'fc81 802c h'1c81 802c 32 7 dma source address register 7 sar7 r/w h'fc81 8030 h'1c81 8030 32 dma destination address register 7 dar7 r/w h'fc81 8034 h'1c81 8034 32 dma transfer count register 7 tcr7 r/w h'fc81 8038 h'1c81 8038 32 dma channel control register 7 chcr7 r/w * 1 h'fc81 803c h'1c81 803c 32 8 dma source address register 8 sar8 r/w h'fc81 8040 h'1c81 8040 32 dma destination address register 8 dar8 r/w h'fc81 8044 h'1c81 8044 32 dma transfer count register 8 tcr8 r/w h'fc81 8048 h'1c81 8048 32 dma channel control register 8 chcr8 r/w * 1 h'fc81 804c h'1c81 804c 32 9 dma source address register 9 sar9 r/w h'fc81 8050 h'1c81 8050 32 dma destination address register 9 dar9 r/w h'fc81 8054 h'1c81 8054 32 dma transfer count register 9 tcr9 r/w h'fc81 8058 h'1c81 8058 32 dma channel control register 9 chcr9 r/w * 1 h'fc81 805c h'1c81 805c 32
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 563 of 1286 rej09b0158-0100 channel name abbrev. r/ w p4 address area 7 address access size * 3 6 to 11 dma operation register 1 dmaor1 r/w * 2 h'fc81 8060 h'1c81 8060 16 10 dma source address register 10 sar10 r/w h'fc81 8070 h'1c81 8070 32 dma destination address register 10 dar10 r/w h'fc81 8074 h'1c81 8074 32 dma transfer count register 10 tcr10 r/w h'fc81 8078 h'1c81 8078 32 dma channel control register 10 chcr10 r/w * 1 h'fc81 807c h'1c81 807c 32 11 dma source address register 11 sar11 r/w h'fc81 8080 h'1c81 8080 32 dma destination address register 11 dar11 r/w h'fc81 8084 h'1c81 8084 32 dma transfer count register 11 tcr11 r/w h'fc81 8088 h'1c81 8088 32 dma channel control register 11 chcr11 r/w * 1 h'fc81 808c h'1c81 808c 32 6 dma source address register b6 sarb6 r/w h'fc81 8120 h'1c81 8120 32 dma destination address register b6 darb6 r/w h'fc81 8124 h'1c81 8124 32 dma transfer count register b6 tcrb6 r/w h'fc81 8128 h'1c81 8128 32 7 dma source address register b7 sarb7 r/w h'fc81 8130 h'1c81 8130 32 dma destination address register b7 darb7 r/w h'fc81 8134 h'1c81 8134 32 dma transfer count register b7 tcrb7 r/w h'fc81 8138 h'1c81 8138 32 8 dma source address register b8 sarb8 r/w h'fc81 8140 h'1c81 8140 32 dma destination address register b8 darb8 r/w h'fc81 8144 h'1c81 8144 32 dma transfer count register b8 tcrb8 r/w h'fc81 8148 h'1c81 8148 32 9 dma source address register b9 sarb9 r/w h'fc81 8150 h'1c81 8150 32 dma destination address register b9 darb9 r/w h'fc81 8154 h'1c81 8154 32 dma transfer count register b9 tcrb9 r/w h'fc81 8158 h'1c81 8158 32 notes: 1. writing 0 after read 1 of he or te bit of chcr is possible to clear the flag. 2. writing 0 after read 1 of ae or nmif bi t of dmaor is possible to clear the flag. 3. accessing with other access sizes is prohibited.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 564 of 1286 rej09b0158-0100 table 14.3 register states in each processing mode channel name abbrev. power-on reset by preset /wdt/ h-udi manual reset by wdt/multiple exceptions sleep by sleep instruction module standby 0 dma source address register 0 sar 0 undefined undefined retained retained dma destination address register 0 dar0 undefined undefined retained retained dma transfer count register 0 tcr0 undefined undefined retained retained dma channel control register 0 chcr0 h'4000 0000 h'4000 0000 retained retained 1 dma source address register 1 sar 1 undefined undefined retained retained dma destination address register 1 dar1 undefined undefined retained retained dma transfer count register 1 tcr1 undefined undefined retained retained dma channel control register 1 chcr1 h'4000 0000 h'4000 0000 retained retained 2 dma source address register 2 sar 2 undefined undefined retained retained dma destination address register 2 dar2 undefined undefined retained retained dma transfer count register 2 tcr2 undefined undefined retained retained dma channel control register 2 chcr2 h'4000 0000 h'4000 0000 retained retained 3 dma source address register 3 sar 3 undefined undefined retained retained dma destination address register 3 dar3 undefined undefined retained retained dma transfer count register 3 tcr3 undefined undefined retained retained dma channel control register 3 chcr3 h'4000 0000 h'4000 0000 retained retained 0 to 5 dma operation register 0 dmaor0 undefined undefined retained retained 4 dma source address register 4 sar 4 undefined undefined retained retained dma destination address register 4 dar4 undefined undefined retained retained dma transfer count register 4 tcr4 undefined undefined retained retained dma channel control register 4 chcr4 h'4000 0000 h'4000 0000 retained retained 5 dma source address register 5 sar 5 undefined undefined retained retained dma destination address register 5 dar5 undefined undefined retained retained dma transfer count register 5 tcr5 undefined undefined retained retained dma channel control register 5 chcr5 h'4000 0000 h'4000 0000 retained retained
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 565 of 1286 rej09b0158-0100 channel name abbrev. power-on reset by preset /wdt/ h-udi manual reset by wdt/multiple exceptions sleep by sleep instruction module standby 0 dma source address register b0 sarb0 undefined undefined retained retained dma destination address register b0 darb0 undefined undefined retained retained dma transfer count register b0 tcrb0 undefined undefined retained retained 1 dma source address register b1 sarb1 undefined undefined retained retained dma destination address register b1 darb1 undefined undefined retained retained dma transfer count register b1 tcrb1 undefined undefined retained retained 2 dma source address register b2 sarb2 undefined undefined retained retained dma destination address register b2 darb2 undefined undefined retained retained dma transfer count register b2 tcrb2 undefined undefined retained retained 3 dma source address register b3 sarb3 undefined undefined retained retained dma destination address register b3 darb3 undefined undefined retained retained dma transfer count register b3 tcrb3 undefined undefined retained retained 0, 1 dma extended resource selector 0 dmars0 h'0000 0000 h'0000 0000 retained retained 2, 3 dma extended resource selector 1 dmars1 h'0000 0000 h'0000 0000 retained retained 4, 5 dma extended resource selector 2 dmars2 h'0000 0000 h'0000 0000 retained retained 6 dma source address register 6 sar6 undefined undefined retained retained dma destination address register 6 dar6 undefined undefined retained retained dma transfer count register 6 tcr6 undefined undefined retained retained dma channel control register 6 chcr6 h'4000 0000 h'4000 0000 retained retained 7 dma source address register 7 sar7 undefined undefined retained retained dma destination address register 7 dar7 undefined undefined retained retained
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 566 of 1286 rej09b0158-0100 channel name abbrev. power-on reset by preset /wdt/ h-udi manual reset by wdt/multiple exceptions sleep by sleep instruction module standby 7 dma transfer count register 7 tcr7 undefined undefined retained retained dma channel control register 7 chcr7 h'4000 0000 h'4000 0000 retained retained 8 dma source address register 8 sar 8 undefined undefined retained retained dma destination address register 8 dar8 undefined undefined retained retained dma transfer count register 8 tcr8 undefined undefined retained retained dma channel control register 8 chcr8 h'4000 0000 h'4000 0000 retained retained 9 dma source address register 9 sar 9 undefined undefined retained retained dma destination address register 9 dar9 undefined undefined retained retained dma transfer count register 9 tcr9 undefined undefined retained retained dma channel control register 9 chcr9 h'4000 0000 h'4000 0000 retained retained 6 to 11 dma operation register 1 dmaor 1 undefined undefined retained retained 10 dma source address register 10 sar10 undefined undefined retained retained dma destination address register 10 dar10 undefined undefined retained retained dma transfer count register 10 tcr10 undefined undefined retained retained dma channel control register 10 chcr10 h'4000 0000 h'4000 0000 retained retained 11 dma source address register 11 sar11 undefined undefined retained retained dma destination address register 11 dar11 undefined undefined retained retained dma transfer count register 11 tcr11 undefined undefined retained retained dma channel control register 11 chcr11 h'4000 0000 h'4000 0000 retained retained 6 dma source address register b6 sarb6 undefined undefined retained retained dma destination address register b6 darb6 undefined undefined retained retained dma transfer count register b6 tcrb6 undefined undefined retained retained
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 567 of 1286 rej09b0158-0100 channel name abbrev. power-on reset by preset /wdt/ h-udi manual reset by wdt/multiple exceptions sleep by sleep instruction module standby 7 dma source address register b7 sarb7 undefined undefined retained retained dma destination address register b7 darb7 undefined undefined retained retained dma transfer count register b7 tcrb7 undefined undefined retained retained 8 dma source address register b8 sarb8 undefined undefined retained retained dma destination address register b8 darb8 undefined undefined retained retained dma transfer count register b8 tcrb8 undefined undefined retained retained 9 dma source address register b9 sarb9 undefined undefined retained retained dma destination address register b9 darb9 undefined undefined retained retained dma transfer count register b9 tcrb9 undefined undefined retained retained 14.3.1 dma source address regist ers 0 to 11 (sar0 to sar11) sar are 32-bit readable/writable registers that specify the source addr ess of a dma transfer. during a dma transfer, these register s indicate the next source address. to transfer data in word or in longword units, specify the address with word or longword address boundary. when transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. the initial value is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: sar sar ???????????????? ????????????????
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 568 of 1286 rej09b0158-0100 14.3.2 dma source address registers b0 to b3, b6 to b9 (sarb0 to sarb3, sarb6 to sarb9) sarb are 32-bit readable/writable re gisters that specify the source address of a dma transfer that is set in sar again in repeat/reload mode. data to be written from the cpu to sar is also written to sarb. to set sarb address that differs from sar address, wr ite data to sarb after sar. to transfer data in word or in longword units, specify the address with wo rd or longword address boundary. when transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. the initial value is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: sarb sarb ???????????????? ???????????????? 14.3.3 dma destination address registers 0 to 11 (dar0 to dar11) dar are 32-bit readable/writable registers that sp ecify the destination address of a dma transfer. during a dma transfer, these registers in dicate the next destination address. to transfer data in word or in longword units, specify the address with wo rd or longword address boundary. when transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the destination address value. the initial value is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: initial value: r/w: bit: initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dar dar ???????????????? ????????????????
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 569 of 1286 rej09b0158-0100 14.3.4 dma destination address re gisters b0 to b3, b6 to b9 (darb0 to darb3, darb6 to darb9) darb are 32-bit readable/writable registers th at specify the destina tion address of a dma transfer that is set in dar agai n in repeat/reload mode. data to be written from the cpu to dar is also written to darb. to set darb address that differs from dar address, write data to darb after dar. to transfer data in word or in longword units, specify the address with word or longword address boundary. when transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary must be set for the source address value. the initial value is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: initial value: r/w: bit: initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w darb darb ???????????????? ????????????????
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 570 of 1286 rej09b0158-0100 14.3.5 dma transfer count registers 0 to 11 (tcr0 to tcr11) tcr are 32-bit readable/writable registers that specify the dma transfer count. the number of transfers is 1 when the setting is h'00000001, 16,777,215 when h'00ffffff is set, and 16,777,216 (the maximum) when h'00000000 is set. during a dma transfer, these registers indicate the remaining transfer count. the upper eight bits of tcr (bits 31 to 24) are always read as 0, and the write value should always be 0. the initial value is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: initial value: r/w: bit: initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcr tcr ???????????????? ????????????????
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 571 of 1286 rej09b0158-0100 14.3.6 dma transfer count registers b0 to b3, b6 to b9 (tcrb0 to tcrb3, tcrb6 to tcrb9) tcrb are 32-bit readable/writable registers. data to be written from the cpu to tcr is also written to tcrb. while the half-end* function is used, tcrb are used as the initial value hold registers to detect half-end. also, tcrb specify the number of dma tran sfers which are set in tcr in repeat mode. tcrb specify the number of dma transfers and are us ed as transfer count counters in reload mode. note: * the "half-end" means the transfer is half finished. in reload mode, the lower 8 bits (bits 7 to 0) operate as transfer count counters, values of sar and dar are updated after the value of the bits 7 to 0 b ecame 0, and then the value of the bits 23 to 16 of tcrb are loaded to the bits 7 to 0. in bits 23 to 16, set the number of transfers which starts reloading. in reload mode, a value from h'ff (255 times) to h'01 (1 time) can be specified to the bits 23 to 16 and 7 to 0 of tcrb, and set the same number in both bits 23 to 16 and bits 7 to 0 and clear to h'00 in bits 15 to 8. also, set the hie bit in chcr to 0 and do not use the half end function. the upper eight bits of tcrb (bits 31 to 24) ar e always read as 0, and the write value should always be 0. the initial value of tcrb is undefined. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: initial value: r/w: bit: initial value: r/w: rrrrrrrrr/wr/wr/wr/wr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcrb tcrb ???????????????? ????????????????
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 572 of 1286 rej09b0158-0100 14.3.7 dma channel control registers 0 to 11 (chcr0 to chcr11) chcr are 32-bit readable/writable register s that control the dma transfer mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 151413121110987654321 0 0100000000000000 r r/w r r r/w r/w r/w r r/w r/w r r/w r/(w) * r/w r/w r/w r/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/(w) * note: * writing 0 is possible to clear the flag. bit: initial value: r/w: bit: initial value: r/w: lckn rpt[2:0] do rl ts2 he hie am al dm[1:0] sm[1:0] rs[3:0] dl ds tb ts[1:0] ie te de bit bit name initial value r/w descriptions 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 lckn 1 r/w bus lock signal disable specifies whether enable or disable the bus lock signal output when a read instructio n for the superhyway bus. this bit is effective in cycle steal mode, and should be cleared to 0 in burst mode. to disable the bus lock signal, the bus request from the bus master other than the dmac could be received, and so improve the bus usage efficiency. 0: bus lock signal output enabled 1: bus lock signal output disabled 29, 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 573 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 27 to 25 rpt[2:0] 000 r/w dma setting renewal specify these bits are enabled in chcr0 to chcr3 and chcr6 to chcr9. 000: normal mode (dmac operation) 001: repeat mode sar/dar/tcr used as repeat area 010: repeat mode dar/tcr used as repeat area 011: repeat mode sar/tcr used as repeat mode 100: reserved (setting prohibited) 101: reload mode sar/dar used as reload area 110: reload mode dar used as reload area 111: reload mode sar used as reload area 24 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 23 do 0 r/w dma overrun selects whether dreq is detected by overrun 0 or by overrun 1. this bit is valid only in chcr0 to chcr3. 0: detects dreq by overrun 0 1: detects dreq by overrun 1 22 rl 0 r/w request check level selects whether the drak signal is an active-high or active-low output. this bi t valid only in chcr0 to chcr3. 0: drak is an active-low output ( drak ) 1: drak is an active-high output 21 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 574 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 20 ts2 0 r/w dma transfer size specify with ts1 and ts0 (bits 4 and 3), this bit specifies the dma transfer size. when the transfer source or transfer destination is a register of an peripheral module that access size is designated, the transfer size for the register should be the same value of its access size. for the transfer source or destination address specified by sar or dar, an address boundary should be set according to the transfer data size. ts[2:0] 000: byte units transfer 001: word (2-byte) units transfer 010: longword (4-byte) units transfer 011: 16-byte units transfer 100: 32-byte units transfer other than above: setting prohibited
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 575 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 19 he 0 r/(w) * half end flag after hie (bit 18) is set to 1 and the number of transfers become half of tcr (1 bit shift to right) which is set before transfer starts, he becomes 1. this bit is set to 1 when the tcr value is equal to any of the following: ? (tcr set before transfer)/2 (tcr: even number) ? (tcr set before transfer - 1)/2 (tcr: odd number) ? 8,388,608 (h'0080 0000) (tcr: maximum number h'0000 0000) the he bit is not set when transfers are ended by an nmi interrupt or address error, or by clearing the de bit or the dme bit in dmaor before the number of transfers is decreased to half of the tcr value set preceding the transfer. the he bit is kept set when the transfer ends by an nmi interrupt or address error, or clearing the de bit (bit 0) or the dme bit in dmaor after the he bit is set to 1. to clear the he bit, write 0 after reading 1 in the he bit. this bit is valid only in chcr0 to chcr3 and chcr6 to chcr9. 0: during the dma transfer or dma transfer has been interrupted tcr > (tcr set before transfer)/2 [clearing condition] writing 0 after he = 1 is read. 1: tcr = (tcr set before transfer)/2
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 576 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 18 hie 0 r/w half end interrupt enable specifies whether an interrupt request is generated to the cpu when the number of transfers is decreased to half of the tcr value (a read transfer cycle end) set preceding the transfer. when the hie bit is set to 1 and the he bit is set, an interrupt request is generated to the cpu. to confirm the half end of the transfer, execute a dummy read of the destination space and issue the synco instruction. clear this bit to 0 while reload mode is se t. this bit is va lid in chcr0 to chcr3 and chcr6 to chcr9. 0: disables the half end interrupt 1: enables the half end interrupt 17 am 0 r/w acknowledge mode selects whether dack is outpu t in data read cycle or in data write cycle. this bit is valid only in chcr0 to chcr3. 0: dack output in read cycle 1: dack output in write cycle 16 al 0 r/w acknowledge level specifies whether the dack signal output is high active or low active. this bit is valid only in chcr0 to chcr3. 0: low-active output of dack ( dack ) 1: high-active output of dack
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 577 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 15, 14 dm[1:0] 00 r/w destination address mode 1, 0 specify whether the dma destination address is incremented, decremented, or left fixed. 00: fixed destination address 01: destination address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer +16 in 16-byte units transfer +32 in 32-byte units transfer 10: destination address is decremented ?1 in byte units transfer ?2 in word units transfer ?4 in longword units transfer setting prohibited in 16/32-byte units transfer 11: setting prohibited 13, 12 sm[1:0] 00 r/w source address mode 1, 0 specify whether the dma source address is incremented, decremented, or left fixed. 00: fixed source address 01: source address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer +16 in 16-byte units transfer +32 in 32-byte units transfer 10: source address is decremented ?1 in byte units transfer ?2 in word units transfer ?4 in longword units transfer setting prohibited in 16/32-byte units transfer 11: setting prohibited
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 578 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 11 to 8 rs[3:0] 0000 r/w resource select 3 to 0 specify which transfer requests will be sent to the dmac. the changing of transfer request source should be done in the state that the dma enable bit (de) is cleared to 0. 0000: external request, dual address mode 0100: auto request 1000: selected by dma extended resource selector (for peripheral modules) other than above: setting prohibited note: external request specification is valid only in chcr0 to chcr3. none of the external request can be selected in chcr4 to chcr11. dma extended resource selector is valid only in chcr0 to chcr5). 7 6 dl ds 0 0 r/w r/w dreq level and dreq edge select specify the detecting method of the dreq pin input and the detecting level. these bits are valid only in chcr0 to chcr3. in channels 0 to 3, also, if the transfer request source is specified as a peripheral module or if an auto-request is specified, these bits are invalid. 00: dreq detected in low level ( dreq ) 01: dreq detected at falling edge 10: dreq detected in high level 11: dreq detected at rising edge 5 tb 0 r/w transfer bus mode specifies the bus mode when dma transfers data. 0: cycle steal mode 1: burst mode select the cycle steal mode when the peripheral module requests. 4, 3 ts[1:0] 00 r/w dma transfer size specify see the description of ts2 (bit 20).
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 579 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 2 ie 0 r/w interrupt enable specifies whether or not an interrupt request is generated to the cpu at the end of the final dma transfer. setting this bit to 1 generates an interrupt request (dmint) to the cpu when the te bit is set to 1 and the final dma transfer of read cycle ended. to confirm the final end of t he transfer, execute a dummy read of the destination space and issue the synco instruction. 0: interrupt request is disabled. 1: interrupt request is enabled. 1 te 0 r/(w) * transfer end flag shows that dma transfer ends. the te bit is set to 1 when tcr becomes to 0 (and the dmac starts executing the final dma transfer). the te bit is not set to 1 in either of the following cases. ? dma transfer ends due to an nmi interrupt or dma address error before tcr is cleared to 0. ? dma transfer is ended by clearing the de bit and dme bit in dmaor. to clear the te bit, the te bit should be written to 0 after reading 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: during the dma transfer or dma transfer has been interrupted [clearing condition] writing 0 after te = 1 read 1: tcr = 0 (during the final dma transfer or the dma transfer ends)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 580 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 0 de 0 r/w dma enable enables or disables the dma transfer. in auto request mode, dma transfer starts by setting the de bit and dme bit in dmaor to 1. in this time, all of the bits te, nmif, and ae in dmaor must be 0. in an external request or peripheral module request, dma transfer starts if dma transfer request is generated by the devices or peripheral modules after setting the bits de and dme to 1. in this case, however, all of the bits te, nmif, and ae must be 0, which is the same as in the case of auto request mode. clearing the de bit to 0 can terminate the dma transfer. 0: dma transfer disabled 1: dma transfer enabled note: * writing 0 is possible to clear the flag.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 581 of 1286 rej09b0158-0100 14.3.8 dma operation register 0, 1 (dmaor0 and dmaor1) dmaor is a 16-bit readable/writable register that specifies the priority level of channels at the dma transfer. this register show s the dma transfer status. dmaor 0 is for channel 0 to 5, and dmaor1 is for channel 6 to11. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r r r/w r/w r r r/w r/w r r r r r r/(w) * r/(w) * r/w cms[1:0] pr[1:0] ae nmif dme bit: initial value: r/w: bit bit name initial value r/w descriptions 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13, 12 cms[1:0] 00 r/w cycl e steal mode select 1, 0 select either normal mode or intermittent mode in cycle steal mode. it is necessary that all channels 0 to 5 (dmaor0) or 6 to 11 (dmaor1) bus modes are set to cycle steal mode to make valid intermittent mode. 00: normal mode 01: setting prohibited 10: intermittent mode 16 issues a bus request after waiting 16 bck clocks and executes one dma transfer. 11: intermittent mode 64 issues a bus request after waiting 64 bck clocks and executes one dma transfer. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 582 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 9, 8 pr[1:0] 00 r/w priority mode 1, 0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: ch0 > ch1 > ch2 > ch3 > ch4 > ch5 (dmaor0) ch6 > ch7 > ch8 > ch9 > ch10 > ch11 (dmaor1) 01: ch0 > ch2 > ch3 > ch1 > ch4 > ch5 (dmaor0) ch6 > ch8 > ch9 > ch7 > ch10 > ch11 (dmaor1) 10: setting prohibited 11: round-robin mode when round-robin mode is specified, do not mix the cycle steal mode and the burst mode in channels 0 to 5 or 6 to 11 respectively. 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ae 0 r/(w) * address error flag indicates that an address error occurred during dma transfer. this bit is set under following conditions: ? the value set in sar or dar does not match to the transfer size boundary. ? the transfer source or transfer destination is invalid space. ? the transfer source or transfer destination is in module stop mode if this bit is set, the corresponding channels (channels 0 to 5 or 6 to 11) dma transfer are all disabled even if the de bit in each chcr and the dme bit in corresponding dmaor are set to 1. 0: no dmac address error [clearing condition] writing ae = 0 after ae = 1 read 1: dmac address error occurs
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 583 of 1286 rej09b0158-0100 bit bit name initial value r/w descriptions 1 nmif 0 r/(w) * nmi flag indicates that an nmi interrupt occurred. if this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. when the nmi is input, the dma transfer in progress can be done in at least one transfer unit. when the dmac is not in operational, the nmif bit is set to 1 even if the nmi interrupt was input. 0: no nmi interrupt [clearing condition] writing nmif = 0 after nmif = 1 read 1: nmi interrupt occurs 0 dme 0 r/w dma master enable enables or disables dma transfers on all channels 0 to 5 (dmaor0) or 6 to 11 (dmaor1). if the dme bit and the de bit in chcr are set to 1, transfer is enabled. in this time, all of the bits te in chcr, nmif, and ae in dmaor must be 0. if this bit is cleared during transfer, transfers in all channels 0 to 5 (dmaor0) or 6 to 11 (dmaor1) are terminated. 0: disables dma transfers on all channels (channels 0 to 5 by dmaor0, 6 to 11 by dmaor1) 1: enables dma transfers on all channels (channels 0 to 5 by dmaor0, 6 to 11 by dmaor1) note: * writing 0 is possible to clear the flag.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 584 of 1286 rej09b0158-0100 14.3.9 dma extended resource se lectors (dmars0 to dmars2) dmars are 16-bit readable/writable registers th at specify the dma tr ansfer sources from peripheral modules in each channel. dmars0 speci fies for channels 0 an d 1, dmars1 specifies for channels 2 and 3, and dmars2 specifies for channels 4 and 5. this register can set the transfer request of scif0, scif1, hac, hspi, siof, ssi, flctl, and mmcif. when mid/rid other than the values listed in table 14.4 is set, the operation of this lsi is not guaranteed. the transfer request fr om dmars is valid only when th e resource select bits rs[3:0] has been set to b'1000 for chcr0 to chcr5 registers. otherwise, even if dmars has been set, transfer request so urce is not accepted. ? dmars0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: c1mid[5:0] c1rid[1:0] c0mid[5:0] c0rid[1:0] bit bit name initial value r/w descriptions 15 to 10 c1mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 1 (mid) see table 14.4. 9, 8 c1rid[1:0] 00 r/w transfer reques t register id1 and id0 for dma channel 1 (rid) see table 14.4. 7 to 2 c0mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 0 (mid) see table 14.4 1, 0 c0rid[1:0] 00 r/w transfer reques t register id1 and id0 for dma channel 0 (rid) see table 14.4.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 585 of 1286 rej09b0158-0100 ? dmars1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: c3mid[5:0] c3rid[1:0] c2mid[5:0] c2rid[1:0] bit bit name initial value r/w descriptions 15 to 10 c3mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 3 (mid) see table 14.4. 9, 8 c3rid[1:0] 00 r/w transfer reques t register id1 and id0 for dma channel 3 (rid) see table 14.4. 7 to 2 c2mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 2 (mid) see table 14.4. 1, 0 c2rid[1:0] 00 r/w r/w transfer request register id1 and id0 for dma channel 2 (rid) see table 14.4.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 586 of 1286 rej09b0158-0100 ? dmars2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: c5mid[5:0] c5rid[1:0] c4mid[5:0] c4rid[1:0] bit bit name initial value r/w descriptions 15 to 10 c5mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 5 (mid) see table 14.4. 9, 8 c5rid[1:0] 00 r/w transfer reques t register id1 and id0 for dma channel 5 (rid) see table 14.4. 7 to 2 c4mid[5:0] 000000 r/w transfer req uest module id5 to id0 for dma channel 4 (mid) see table 14.4. 1, 0 c4rid[1:0] 00 r/w transfer reques t register id1 and id0 for dma channel 4 (rid) see table 14.4.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 587 of 1286 rej09b0158-0100 table 14.4 transfer request sources peripheral module setting value for one channel (mid and rid fields) mid[5:0] rid[1:0] function h'21 b'01 transmit scif0 h'22 b'001000 b'10 receive h'29 b'01 transmit scif1 h'2a b'001010 b'10 receive h'41 b'01 transmit hac h'42 b'010000 b'10 receive h'45 b'01 transmit hspi h'46 b'010001 b'10 receive h'51 b'01 transmit siof h'52 b'010100 b'10 receive ssi h'73 b'011100 b'11 transmit and receive h'83 b'100000 b'11 transmit and receive the data part. flctl h'87 b'100001 b'11 transmit and receive the control code part. mmcif h'93 b'100100 b'11 transmit and receive
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 588 of 1286 rej09b0158-0100 14.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. transfers can be requested in three modes: auto request, external request, and peripheral module request. in bus mode, burst mode or cycle steal mode can be selected. 14.4.1 dma transfer requests dma transfer requests are basically generated in e ither the data transfer source or destination, but they can also be generated by external devices or peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto request, external request, and peripheral module request. the request mode is selected in the bits rs[3:0] in chcr0 to chcr11 respectively, and dmars0 to dmars2 when peripheral module request is used. auto-request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip module unable to request a transfer, auto-request mode allows th e dmac to automatically generate a transfer request signal internally. specify b'0100 to the rs [3:0] bits in chcrn (n = 0 to 11) of the using dma channel. when the de bit in chcr for corresponding channel and the dme bit in dmaor0 for channels 0 to 5, dmaor1 for channels 6 to11 are set to 1, the transfer begins so long as the ae and nmif bits in that dmaor are all 0. external request mode: in this mode, a transfer is performe d at the request signal (dreq) of an external device. this mode is valid only in channel 0 to 3. specify b'0000 to the rs [3:0] bits in chcrn (n = 0 to 3) of the using dma channel. wh en this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. choose to detect dreq by either the edge or level of the signal input with the dl bit and ds bit in chcrn (n = 0 to 3) as shown in table 14.5. the source of the transfer request does not have to be the data transfer source or destination.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 589 of 1286 rej09b0158-0100 table 14.5 selecting external request detection with dl, ds bits chcrn (n = 0 to 3) dl ds detection of external request 0 low level detection (initial value; dreq ) 0 1 falling edge detection 0 high level detection 1 1 rising edge detection when dreq is accepted, the dreq pin becomes request accept disabled state. after issuing acknowledge signal dack for the accepted dreq, the dreq pin again becomes request accept enabled state. when dreq is used by level detection, there ar e following two cases by the timing to detect the next dreq after outputting dack. ? overrun 0: transfer is aborted after the same number of transfer has been performed as requests. ? overrun 1: transfer is aborted after transfers have been performed for the number of requests plus 1 times. the do bit in chcr selects this overrun 0 or overrun 1. table 14.6 selecting external request detection with do bit chcr do external request 0 overrun 0 (initial value) 1 overrun 1 peripheral module request mode: in this mode, a transfer is pe rformed at the transfer request signal of an peripheral module. this mode is valid only in channel 0 to 5. specify b'1000 to the rs [3:0] bits in chcrn (n = 0 to 5) of the usin g dma channel. transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the scif0, scif1, hac, hspi, siof, ssi, and mmcif set by dmars0/1/2, and transfer requests from the flctl. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon the input of a transfer request signal.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 590 of 1286 rej09b0158-0100 when a transmit data empty transfer request of the scif0 is set as the transf er request, the transfer destination must be the scif0's transmit data register. likewise, when receive data full transfer request of the scif0 is set as the transfer request , the transfer source must be the scif0's receive data register. these conditions also apply to th e scif1, hac, hspi, siof, ssi, and mmcif.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 591 of 1286 rej09b0158-0100 table 14.7 peripheral module request modes dmars mid rid dma transfer request source dma transfer request signal source destination bus mode 01 sci f0 transmitter txi (transmit fifo data empty interrupt) any scftdr0 cycle steal 001000 10 scif0 receiver rxi (receive fifo data full interrupt) scfrdr0 any cycle steal 01 sci f1 transmitter txi (transmit fifo data empty interrupt) any scftdr1 cycle steal 001010 10 scif1 receiver rxi (receive fifo data full interrupt) scfrdr1 any cycle steal 01 hac transmitter transmit data empty request any hacpcml, hacpcmr cycle steal 010000 10 hac receiver receive data is not read hacpcml, hacpcmr any cycle steal 01 hspi transmitter transmit data any sptbr cycle steal 010001 10 hspi receiver receive data sprbr any cycle steal 01 siof transmitter txi (transmit fifo data empty interrupt) any sitdr cycle steal 010100 10 siof receiver rxi (receive fifo data full interrupt) sirdr any cycle steal ssi transmitter transmit mode : dmrq = 1 (transmit data empty request) any ssitdr cycle steal 011100 11 ssi receiver receive mode : dmrq = 1 (receive data is not read) ssirdr any cycle steal flctl data part transmit transmit fifo data empty request any fldtfifo cycle steal 100000 11 flctl data part receive receive fifo data full request fldtfifo any cycle steal flctl management code part transmit transmit fifo data empty request any flecfifo cycle steal 100001 11 flctl management code part receive receive fifo data full request flecfifo any cycle steal mmcif data part transmit fifo data write request any dr cycle steal 100100 11 mmcif data part receive fifo data read request dr any cycle steal
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 592 of 1286 rej09b0158-0100 14.4.2 channel priority when the dmac receives simultaneous transfer re quests on two or more channels, it transfers data according to a predetermine d priority. two modes (fixed mo de and round-robin mode) are selected by the bits pr[1:0] in dmaor0 for channels 0 to 5 and dmaor1 for channels 6 to 11. if the dmac receives simultaneous transfer requests from both any channels 0 to 5 and 6 to 11 respectively, then executes each channels 0 to 5 or 6 to 11 request alternately (initial state: channel 0 to 5 is higher priority). fixed mode: in this mode, the priority levels among the channels remain fixed. there are two kinds of fixed modes as follows: channels 0 to 5 ? ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ? ch0 > ch2 > ch3 > ch1 > ch4 > ch5 channels 6 to 11 ? ch6 > ch7 > ch8 > ch9 > ch10 > ch11 ? ch6 > ch8 > ch9 > ch7 > ch10 > ch11 these are selected by the bits pr[1:0] in dmaor0 and dmaor1. round-robin mode: in round-robin mode each time data of one transfer unit (byte, word, longword, 16-byte, or 32-byte unit) is transferred on one channel, the priority is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority. the round- robin mode operation is shown in figure 14.2. the priority of round-robin mode is ch0 > ch1 > ch2 > ch3 > ch4 > ch5, and ch6 > ch7 > ch8 > ch9 > ch10 > ch11 immediately after reset. when round-robin mode is specified, do not mi x the cycle steal mode and the burst mode in channels 0 to 5 or 6 to 11 respectively.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 593 of 1286 rej09b0158-0100 ch1 > ch2 > ch3 > ch4 > ch5 > ch0 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch2 > ch3 > ch4 > ch5 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch3 > ch4 > ch5 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 (1) when channel 0 transfers initial priority order initial priority order initial priority order initial priority order priority order after transfer priority order does not change. channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 5 only, channel 5 becomes bottom priority and the priority of channels 3 and 4, which were higher than channel 5, are also shifted. channel 1 becomes bottom priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes bottom priority priority order after transfer priority order after transfer priority order after transfer post-transfer priority order when there is an immediate transfer request to channel 5 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 5 transfers figure 14.2 round-robin mode (example of channel 0 to 5)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 594 of 1286 rej09b0158-0100 figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 > 4 > 5 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 4 > 5 > 0 2 > 3 > 4 > 5 > 0 > 1 4 > 5 > 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 14.3 changes in channe l priority in round-robin mode (example of channel 0 to 5)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 595 of 1286 rej09b0158-0100 14.4.3 dma transfer types dma transfer type is dual address mode transfer. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. dual address modes: in dual address mode, both the transfer source and destination are accessed by an address. the source and destination can be located externally or internally. dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a da ta write cycle. at this time, transfer data is temporarily stored in the dmac. in the transfer between external memories as shown in figure 14.4, data is read to the dmac from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. first bus cycle second bus cycle the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 14.4 data flow of dual address mode
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 596 of 1286 rej09b0158-0100 auto request, external request, and peripheral modul e request are available for the transfer request. dack can be output in read cycle or write cy cle in dual address mode. chcr can specify whether the dack is output in read cycle or write cycle. figure 14.5 shows an example of dma transfer timing in dual address mode. clkout a25 to a0 note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn . d31 to d0 we rd dack low-active csn transfer source address transfer destination address data read cycle data write cycle (1st cycle) (2nd cycle) figure 14.5 example of dma transf er timing in dual address mode (source: ordinary memory, dest ination: ordinary memory)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 597 of 1286 rej09b0158-0100 bus modes: there are two bus modes: cycle steal mode and burst mode. select the mode in the tb and lckn bits in chcr. more over, cycle steal mode has normal and intermittent modes that are specified by the cms bits in dmaor. ? cycle-steal mode ? normal mode1 (dmaor.cms = 00, chcr.lckn = 0, chcr.tb = 0) in cycle-steal normal mode, th e superhyway bus mastership is given to another bus master after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit) dma transfer. when the next transfer request occurs, the dmac issues the ne xt transfer request, the bus mastership is obtained from the other bus master and a transfer is performed for one- transfer unit. when that transf er ends, the bus mastership is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. in cycle-steal normal mode, tr ansfer areas are not affected regardless of settings of the transfer request source, transfer source, and tr ansfer destination. figure 14.6 shows an example of dma transfer timing in cycl e-steal normal mode. transfer conditions shown in the figure are: cpu cpu cpu dmac dmac cpu dmac dmac cpu d req superhyway bus cycle bus mastership returned to cpu once read/write read/write figure 14.6 dma transfer timing example in cycle-steal normal mode 1 (dreq low level detection) ? normal mode 2 (dmaor.cms = 00, chcr.lckn = 1, chcr.tb = 0) in cycle steal normal mode 2, the dmac does not keep the superhyway bus mastership, is to obtain the bus mastership in every on e transfer unit of re ad or write cycle. figure 14.7 shows an example of dma transf er timing in cycle st eal normal mode 2.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 598 of 1286 rej09b0158-0100 cpu cpu cpu dmac cpu dmac cpu cpu dmac dmac dreq read bus mastership retured to cpu once read write write cpu superhyway bus cycle figure 14.7 dma transfer timing example in cycle-steal normal mode 2 (dreq low level detection) ? intermittent mode 16 (dmaor.cms = 10, chcr.lckn = 0 or 1, chcr.tb = 0), intermittent mode 64 (dmaor.cms = 11 , chcr.lckn = 0 or 1, chcr.tb = 0) in intermittent mode of cycle steal, the dmac returns the superhyway bus mastership to other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte unit) is complete. if the next transfer request occurs after th at, the dmac issues the next transfer request after waiting for 16 or 64 clocks in bck count, and obtains the bus mastership from other bus master. the dmac th en transfers data of one-transfer unit and returns the bus mastership to other bus master. these operations are repeated until the transfer end condition is satisfied. it is thus possible to make lower the ratio of bus occupation by dma transfer than cycle-steal normal mode. when the dmac issues again the transfer request, dma transfer can be postponed in case of entry updating due to cache miss. the intermittent modes, however, must be cycle steal mode in all channels 0 to 5 or 6 to11 for the corresponding transfer channel. figure 14.8 shows an example of dma transf er timing in cycle steal intermittent mode. transfer conditions shown in the figure are: dreq cpu cpu cpu more than 16 or 64 bck dmac dmac cpu cpu dmac dmac cpu read/write read/write superhyway bus cycle figure 14.8 example of dm a transfer timing in cycle steal intermittent mode (dreq low level detection)
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 599 of 1286 rej09b0158-0100 ? burst mode (lckn = 0, tb = 1) in burst mode, once the dmac obtains the s uperhyway bus mastersh ip, the transfer is performed continuously without releasing the bu s mastership until the transfer end condition is satisfied. in external request mode with level detection of the dreq pin, however, when the dreq pin is not active, the bus mastership pa sses to the other bus master after the dmac transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. burst mode cannot be used when the periphera l module is the transf er request source. figure 14.9 shows dma transfer timing in burst mode. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq read read read write write write superhyway bus cycle figure 14.9 dma transfer ti ming example in burst mode (dreq low level detection) dma transfer matrix: table 14.8 shows the dm a transfer matrix in auto-request mode and table 14.9 shows the dma transfer matrix in external request mode, and table 14.10 shows the peripheral module request. table 14.8 dma transfer matrix in auto-request mode (all channels) transfer destination transfer source lbsc space ddrif space pcic space peripheral module * l ram, superhyway ram lbsc space yes yes yes yes yes ddrif space yes yes yes yes yes pcic space yes yes yes yes yes peripheral module * yes yes yes yes yes l ram, superhyway ram yes yes yes yes yes [legend] yes: transfer is available. note: * when the transfer source or destination is peripheral module register, the transfer size should be the same value of its access size.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 600 of 1286 rej09b0158-0100 table 14.9 dma transfer matrix in external request mode (only channels 0 to 3) transfer destination transfer source lbsc space ddrif space pcic space peripheral module * 1 l ram, superhyway ram lbsc space yes yes * 2 yes * 2 yes yes ddrif space yes * 3 no yes * 4 yes * 3 yes * 3 pcic space yes * 3 yes * 5 yes * 6 yes * 3 yes * 3 peripheral module * 1 yes yes * 2 yes * 2 yes yes l ram, superhyway ram yes yes * 2 yes * 2 yes yes [legend] yes: transfer is available. no: transfer is not available. notes: 1. when the transfer source or destination is peripheral module register, the transfer size should be the same value of its access size. 2. transfer is available when the am bit in chcr is cleared to 0. 3. transfer is available when the am bit in chcr is set to 1. 4. transfer is available when the am bit in chcr is set to 1 and the destination address of the pcic is h'fd00 0000 to h'fdff ffff (pci memory space 0). 5. transfer is available when the am bit in chcr is cleared to 0 and the source address of the pcic is h'fd00 0000 to h'fdff ffff (pci memory space 0). 6. transfer is available when the source or destination, or both t he source and destination address of the pcic is h'fd00 0000 to h'fdff ffff (pci memory space 0). when the transfer source address is h 'fd00 0000 to h'fdff ffff, the am bit in chcr is cleared to 0, when the transfer destination address is h'fd00 0000 to h'fdff ffff the am bit in chcr is set to 1.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 601 of 1286 rej09b0158-0100 table 14.10 dma transfer matrix in peripheral module request mode transfer destination transfer source lbsc space ddrif space pcic space peripheral module * l ram, superhyway ram lbsc space no no no yes no ddrif space no no no yes no pcic space no no no yes no peripheral module * yes yes yes yes yes l ram, superhyway ram no no no yes no [legend] yes: transfer is available. no: transfer is not available. note: * when the transfer source or the destination is an peripheral module, the transfer size should be the same value of its register access size. the transfer source or the transfer destinat ion should be a register of request source in peripheral module request mode. this transfer is available only cycle steal mode, and when the transfer request source is an peripheral module, the transfer is available in channel 0 to 5. bus mode and channel priority: when the priority is set in fixed mode (ch0 > ch1) and channel 1 is transferring in burst mode, if there is a transfer request to channel 0 with a higher priority, the transfer of channel 0 will begin immediately. at this time, if channel 0 is also operating in burs t mode, the channel 1 transfer will continue after the channel 0 transfer has completely finished. when channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of one transfer unit and the channel 1 transfer is continuously performed without releasing the bus mastership. the bus mastership will then switch between the two in the order channel 0, channel 1, channel 0, and channel 1. this example is shown in figure 14.9. when multip le channels are operating in burst modes, the channel with the highest priority is executed first. when dma transfer is executed in the multiple channels, the bus mastership will not be given to the bus master until all competi ng burst transfer s are complete.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 602 of 1286 rej09b0158-0100 dma ch1 burst mode priority: ch0: ch1: ch0 > ch1 cycle steal mode burst mode dma ch0 and ch1 burst mode dma ch1 burst mode ch0 transfer source superhyway bus cycle ch1 transfer source cpu dma ch1 dma ch1 dma ch0 dma ch1 dma ch0 dma ch1 dma ch1 cpu figure 14.10 bus state when mu ltiple channels are operating in round-robin mode, the priority changes according to the specification shown in figure 14.2. however, the channel in cycle steal mode cannot be mixed with the channel in burst mode. 14.4.4 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), dma operation register (dmaor), and dma exte nded resource selector s (dmars) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request occurs while transfer is enabled, the dmac tr ansfers one transfer unit of data (depending on the ts0 and ts1 settings). in auto request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. th e actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfer ha ve been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit in chcr is set to 1 at this time, a dmint interrupt is sent to the cpu. 4. when an address error or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit in chcr or the dme bit in dmaor is changed to 0. figure 14.11 shows a flowchart of this procedure.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 603 of 1286 rej09b0158-0100 start initial settings (sar, dar, tcr, chcr, dmaor, sarb, darb, tcrb, dmars) de, dme = 1 and te, ae, nmif = 0? no no no no yes yes yes yes transfer request occurs? transfer (1 transfer unit); tcr ? 1 tcr, sar, and dar updated reload mode: tcr[7:0] tcrbl no yes no no no no no sarb/darb load tcr[23:16] tcr[7:0] load te = 1 transfer end normal end bus mode, dreq detection system, transfer request mode * 4 * 3 * 2 * 1 * 6 * 5 * 6 sarb/darb load tcrb tcr load * 5 yes yes reload mode? tcr[7:0] = 0? dmint interrupt request (ie = 1) nmif = 1 or ae =1 or de = 0 or dme = 0? hie = 0 or he = 1? tcr = tcrb/2? yes yes yes tcr = 0? repeat mode? nmif = 1 or ae = 1 or de = 0 or dme = 0? he = 1, dmint interrupt request (hie = 1) notes: 1. in repeat mode, a transfer request is acceptted with te =1 when hie = 1 and he = 0 (half end interrupt is enable and clear the he to 0 after he is set to 1). 2. in auto-request mode, transfer starts when bits nmif, ae, and te are all 0 or bits te and hie are 1 and he is 0 (in repeat mode), and bits de and dme are set to 1. 3. dreq is level detection (external requesrt) in burst mode or cycle-steral mode. 4. dreq is edge detection (external request) or auto request in burst mode. 5. loading to sar and dar differs according to the operating conditions in each mode. figure 14.11 dma transfer flowchart
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 604 of 1286 rej09b0158-0100 14.4.5 repeat mode transfer in a repeat mode transfer, a dma transfer is re peated without specifying the transfer settings every time before executing a transfer. using a repeat mode transfer with the half end fu nction allows a double buffer transfer executed virtually. following processings can be executed effectively by using a repeat mode transfer. as an example, operation of recei ving voice data from the voice codec and compressing it is explained. in the following example, processing of compressing 40-word voice data every data reception is explained. in this case, it is assumed that voice data is received by means of siof. 1. dmac settings ? set address of the siof receive data register in sar ? set address of an internal me mory data store area in dar ? set tcr to h ' 50 (80 times) ? satisfy the following settings of chcr bits rpt[2:0] = b ' 010: repeat mode (use dar as a repeat area) bit hie = b ' 1: tcr/2 interrupt generated bits dm[1:0] = b ' 01: dar incremented bits sm[1:0] = b ' 00: sar fixed bit ie = b ' 1: interrupt enabled bit de = b ' 1: dma transfer enabled ? set such as bits tb and ts[2 :0] according to use conditions ? set bits cms[1:0] and pr[1:0] in dmaor according to use cond itions and set the dme bit to b ' 1 2. voice data is received and then transferre d by siof/dmac 3. tcr is decreased to half of its initial value and an interrupt is generated after reading chcr to confirm that the he bit is set to 1 by an interrupt processing, clear the he bit to 0 and compress 40-word voice data from the address set in dar. 4. tcr is cleared to 0 and an interrupt is generated after reading chcr to confirm that the te bit is set to 1 by an interrupt processing, clear the te bit to 0 and compress 40-word voice data from the address set in dar + 40. after this operation, the value of darb is copied to dar in dmac and initialized, and the value of tcrb is copied to tcr and initialized to 80. 5. hereafter, steps 2 and 4 are repeated until the dme or de bi t is cleard to 0, or an nmi interrupt is generated. note that if the he bit is not cleared in the procedure 3 or if the te bit is
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 605 of 1286 rej09b0158-0100 not cleared in the procedure 4, then the transfer is stopped according to the condition of both the he and the te bits are set to 1. as explained above, a repeat mode transfer enables sequential voice compression by changing buffer for storing data received consequentially and a data buffer for processing signals alternately. 14.4.6 reload mode transfer in a reload mode transfer, according to the settings of bits rpt[2:0] in chcr, the value set in sarb/darb is set to sar/dar and the value of bits tcrb[23:16] is set in bits tcrb[7:0] at each transfer set in the bits tcrb[7:0], and the transfer is repeated until t cr becomes 0 without specifying the transfer settings again. a reload mo de transfer is effective when repeating data transfer with sp ecific area. figure 14.12 shows the operation of reload mode transfer. dmac bits rpt[2:0] shwy bus chcr tcr tcrb sar/dar sarb/darb reload controller reload signal reload counter transfer counter transfer request figure 14.12 reload mode transfer when a reload mode transfer is executed, tcrb is used as a reload counter. set tcrb according to section 14.3.6, dma transfer count registers b0 to b3, b6 to b9 (tcrb0 to tcrb3, tcrb6 to tcrb9).
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 606 of 1286 rej09b0158-0100 14.4.7 dreq pin sampling timing figures 14.13 to 14.16 show the sample timing of the dreq input in each bus mode, respectively. cpu cpu dreq (falling edge) drak (low-active) dack (low-active) bus cycle ckout acceptance started 1st acceptance 2nd acceptance : non-sensitive period dmac figure 14.13 example of dreq input det ection in cycle steal mode edge detection cpu cpu dmac clkout cpu cpu dmac clkout dreq (overrun 0, low-level) dack (low-active) drak (low-active) drak (low-active) bus cycle acceptance started 1st acceptance 2nd acceptance dreq (overrun 1, low-level) dack (low-active) bus cycle acceptance started 1st acceptance 2nd acceptance : non-sensitive period figure 14.14 example of dreq input det ection in cycle steal mode level detection
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 607 of 1286 rej09b0158-0100 cpu dmac dmac clkout drak (low-active) dreq (falling edge) dack (low-active) bus cycle burst acceptance : non-sensitive period figure 14.15 example of dreq input de tection in burst mode edge detection cpu dmac clkout cpu clkout dreq (overrun 0, low-level) drak (low-active) bus cycle acceptance started 1st acceptance dreq (overrun 1, low-level) drak (low-active) dack (low-active) dack (low-active) bus cycle 1st acceptance 3rd acceptance acceptance started acceptance started : non-sensitive period 2nd acceptance 2nd acceptance dmac dmac figure 14.16 example of dreq input detection in burst mode level detection
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 608 of 1286 rej09b0158-0100 14.5 usage notes pay attentions to the following notes when the dmac is used. 14.5.1 module stop while the dmac is in operation, modules should not be stopped by setting mstpcr (transition to the module standby st ate) .when modules are stopped, transf er contents cannot be guaranteed. 14.5.2 address error when a dma address error is occurred, after exec ute the following procedure, and then start a transfer. 1. dummy read for the be low listed registers. bcr (lbsc) pciecr (pcic) mim (ddrif) intc2b3 (intc) 2. issue the synco instruction. 3. set registers of all channels again. if the ae bit in dmaor0 is set to 1, channels 0 to 5 should be set again. if the ae bit in dmaor1 is set to 1, channels 6 to 11 should be set again. 14.5.3 notes on burst mode transfer during a burst mode transfer, following operation should not be executed until the transfer of corresponding channel has completed. ? frequency should not be changed. ? transition to sleep mode should not be made.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 609 of 1286 rej09b0158-0100 14.5.4 dack ou tput division the dack output is divided to align the data unit like the csn output when a dma transfer unit is divided with multiple bus cycles, for example when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit exte rnal device is accessed in word units, and the csn output is negated between these bus cycles. 14.5.5 clear dmint interrupt to ensure that a dmint interrupt source that should have been cleared is not inadvertently accepted again, clear the bl bit after confirming the corresponding flag in int2b3 register becomes 0 or issue the rte instruction. 14.5.6 cs output settings and transfer size larger than external bus width when one dma transfer is performed by multiple bus cycles* 1 , the csn output should be set not to negate between bus cycles* 2 . for detail of settings, refer to table 11.11 to 11.14. if set the csn output is negated between bus cycles, the dreq signal is not sampled correctly and malfunction may occur. notes: 1. when a dma transfer is performed with larger transfer size than the bus width. for example, performing the 16-/32-byte transfer to the 8-/16-/32-bit bus width lbsc space, longword (32-bit) tran sfer to the 8-/16-bit bus wi dth lbsc space, or word (16- bit) transfer to the 8-bit bus width lbsc space. note that except for a 32-bit access to the mpx interface. this access genera tes only one bus cycle (burst). 2. when the csn output is negated between bus cycles, then the dack output is also negated between bus cycles (dack output is also divided). 14.5.7 dack assertion and dreq sampling the dack signal may be asserted ceaselessly dur ing two or more times dma transfer when the dreq level detection with overrun 1 and the dreq edge detection. in this case, the dma transfer is suspended and do not perform correctly, to avoid this insert one or more idle cycle between the dma transfer. the transfer source is the lbsc space and the dack is output during the read cycle: (1) set b'001 to b'111 (i.e., other than 000) to the iwrrd bits in csnbcr (2) set b'001 to b'111 (i.e., other than 000) to the iwrrs bits in csnbcr
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 610 of 1286 rej09b0158-0100 the transfer destination is the lbsc space an d the dack is output during the write cycle: (1) set b'001 to b'111 (i.e., other than 000) to the iww bits in csnbcr note: * the transfer source is the lbsc space and the dack is ou tput during the read cycle or the transfer destination is the lbsc space and the dack is output during the write cycle. and then specifies no idle cy cle (csnbcr.iwrrd, iwrrs, iww are cleared to b'000). note that the case that both the transfer source and th e transfer destination are the lbsc spaces, does not apply this. table 14.11 to 14.14 shows the register settings that whether or not the negation of the dack output with the number of bus cycle generation of the dma transfer. the dack is not negated when the number of the bu s cycle that generated in the dma transfer is 1. note that, in the following settings, when either the transfer source or the tr ansfer destination is the lbsc space, to avoid the dack is asserted ceas elessly during between the two or more times dma transfer, set b'001 to b'111 to the iwrrd , iwrrs or iww bits in csnbcr. in this setting, if the 16-byte dma transfer is performed, multiple bus cycles are generated and the csn is negated between bus cycles, the dreq signal is not sampled correctly and malfunction may occur.
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 611 of 1286 rej09b0158-0100 table14.11 register settings for sram, burs t rom, byte contro l sram interface register settings of csn is not negated bus width [bit] dma transfer access size bus cycle number csnbcr.iwrrd, iwrrs or iww csnwcr.ads and adh byte 1 any any word 2 any b'000 longword 4 any b'000 16-byte 16 b'000 b'000 8 32-byte 32 any b'000 byte 1 any any word 1 any any longword 2 any b'000 16-byte 8 b'000 b'000 16 32-byte 16 any b'000 byte 1 any any word 1 any any longword 1 any any 16-byte 4 b'000 b'000 32 32-byte 8 any b'000
section 14 direct memory access controller (dmac) rev.1.00 dec. 13, 2005 page 612 of 1286 rej09b0158-0100 table14.12 register setting s for pcmcia interface register settings of csn is not negated bus width [bit] dma transfer access size bus cycle number csnbcr.iwrrd,iwrrs or iww byte 1 any word 2 any longword 4 any 16-byte 16 b'000 8 32-byte 32 any byte 1 any word 1 any longword 2 any 16-byte 8 b'000 16 32-byte 16 any table14.13 register settings for mpx interface (read access) register settings of csn is not negated bus width [bit] dma transfer access size bus cycle number csnbcr.iwrrd, or iwrrs byte 1 any word 1 any longword 1 any 16-byte 4 impossible (negated) 32 32-byte 1 any table14.14 register settings for mpx interface (write access) register settings of csn is not negated bus width [bit] dma transfer access size bus cycle number csnbcr.iww csnwcr.iw[1:0] byte 1 any any word 1 any any longword 1 any any 16-byte 4 b'000 b'11 to b'01 32 32-byte 1 any any
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 613 of 1286 rej09b0158-0100 section 15 clock pulse generator (cpg) the cpg generates clocks provided to both the inside and outside of the sh7780, and controls the power-down mode function. the cpg comprises a crystal oscillator circuit, plls, and a divider. 15.1 features the cpg has the following features. ? generates sh7780 internal clocks sh7780 internal clocks are: th e cpu clock (ick) which is used in the cpu, fpu, cache, and tlb; the shwy clock (shck) which is used by the superhyway bus; and peripheral clocks (pck) which are used to interface w ith on-chip periph eral modules. ? generates sh7780 external bus clocks. sh7780 external bus clocks are the bus clock (bck ) which is used to interface with the external devices and memory clocks (ddrck) which are used in the ddrif. ? selects two clock modes selects a crystal resonator or an externa lly input clock as the cpg clock input. ? changes frequencies changes frequencies of the internal clocks by the divider in the cpg. the divider is controlled with the frequency control register (frqcr) set by software. ? provides the clock stop and module standby functions in control sleep mode control sleep mode is the cpu stop mode. in control module standby mode, specific modules can be stopped.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 614 of 1286 rej09b0158-0100 figure 15.1 is a block diagram of the cpg. pll circuit 1 ( 24) pll circuit 2 ( 1) clock frequency controller frqcr clock controller divider ( 1/2) ( 1/4) ( 1/5) ( 1/6) ( 1/8) ( 1/12) ( 1/16) ( 1/24) oscillator xtal clkout bus clock (bck) cpu clock (ick) superhyway clock (shck) peripheral clock (pck) ddr clock (ddrck) mode 7 mode 2 mode 1 mode 0 mode8 extal pllcr mstpcr bus interface peripheral bus [legend] frqcr: frequency control register mstpcr: standby control register (see section 17, power-down mode) pllcr: pll control register figure 15.1 block diagram of cpg
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 615 of 1286 rej09b0158-0100 the function of each block is described below. ? pll circuit 1 pll circuit 1 multiplies the frequency of the external crystal oscillator and the clock input on the extal pin by 24. ? pll circuit 2 pll circuit 2 coordinates the phases of the bus clock (bck) and the clock signal output from the clkout pin that is used as the external peripheral interface clock. ? crystal oscillator circuit used when a crystal resonator is connected to the xtal and extal pins. use of the crystal oscillator circuit can be sel ected with the mode8 pin. ? divider the divider generates the cpu clock (ick), superhyway clock (shck), on-chip peripheral module clock (pck), ddr memory clock (ddrck), and external bus clock (bck). the division ratio is selected by the mode pin mode0, mode1, mode2, mode7.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 616 of 1286 rej09b0158-0100 15.2 input/output pins table 15.1 lists the cpg pin configuration. table 15.1 cpg pin configuration pin name function i/o description mode0, mode1, mode2, and mode7 * 1 mode control pins 0,1,2,7 input select the clock operat ing mode of after power-on reset. mode8 * 2 mode control pins 8 input selects use/non-use of crystal resonator. when mode8 is "low", external clock is input from the extal pin. when mode8 is "high", crystal resonator connected directly to the extal and xtal pins. xtal output this pin is connected to a crystal resonator. extal input this pin is connected to a crystal oscillator to input an external clock or is connected to a crystal resonator. clkout clock pins output this pin is used to output the external bus clock. notes: 1. these pins are multiple xed with the dmac and gpio pins. 2. this pin is multiplexed with the scif0, hspi, flctl and gpio pin.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 617 of 1286 rej09b0158-0100 15.3 clock operating modes the correspondence between settings of the mode control pins (mode7 and mode2 to mode0) and clock operating modes after power-on reset is shown in table 15.2. table 15.2 clock operating modes mode control pin setting * frequency multiplication ratio (to input clock) clock operating mode mode7 mode2 mode1 mode0 pll1, pll2 ick shck pck ddrck bck frqcr initial value 0 low low low low on 12 6 3/2 24/5 3 h'1023 3335 1 low low low high on 12 6 1 24/5 2 h'1024 4336 2 low low high low on 12 6 3/2 24/5 3/2 h'1025 5335 3 low low high high on 12 6 1 24/5 1 h'1026 6336 12 high high low low on 12 4 1 4 2 h'1044 4346 note: other than above: setting prohibited.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 618 of 1286 rej09b0158-0100 15.4 register descriptions table 15.3 shows the cpg register configuration. table 15.4 show s the register states in each processing mode. table 15.3 register configuration register name abbreviation r/w p4 address area 7 address access size sync clock frequency control register frq cr r/w h'ffc8 0000 h'1fc8 0000 32 p ck pll control register pllcr r/w h'ffc8 0024 h'1fc8 0024 32 p ck standby control register mstpcr r/w h'ffc8 0030 h'1fc8 0030 32 p ck note: for mstpcr, see section 17, power-down mode. table 15.4 register states of cpg in each processing mode register name abbreviation power-on reset by preset pin power-on reset by wdt/h-udi manual reset by wdt/ multiple exception sleep by sleep instruction frequency control register frqcr h'1xxx x3xx * 2 h'1xxx x3xx * 2 retained retained pll control register pllcr h'0000 e001 retained retained retained standby control register * 1 mstpcr h'0000 0000 retained retained retained notes: 1. for mstpcr, see section 17, power-down mode. 2. the initial value of frqcr after pow er-on reset depends on the mode pins setting (see table 15.2).
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 619 of 1286 rej09b0158-0100 15.4.1 frequency cont rol register (frqcr) frqcr is a 32-bit readable/writable register that selects the frequency division ratio of the superhyway clock (shck), the peripheral clock (pck), the ddr clock (ddrck) and the bus clock (bck). refer to the clock operating mode table about the frequency multiplication ratio. frqcr can only be accessed in longwords. frqcr is initialized by a power-on reset via the preset pin and wdt over-flow. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 1 0 00 cfc[3:0] * bfc[3:0] * ifc0 * ? ? ? ? ? ? ?? r r r r r/w r/w r/w r/w r/w r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 0 0 1 1 0 0 0 p1fc[3:0] * ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? r r r r r r r r r r r r r r rr bit: note: the initial values of these fields after power-on reset depend on the mode pins setting (see table 15.2). initial value: r/w: bit bit name initial value r/w description 31 to 28 ? 0001 r reserved these bits are always read as 0001. the write value should always be 0001. 27 to 25 ? 000 r reserved these bits are always read as 0. the write value should always be 0. writing to other than 000, t he operation of this lsi is not guaranteed. 24 ifc0 * undefined r/w 23 22 21 20 cfc3 * cfc2 * cfc1 * cfc0 * 0 undefined undefined 0 r/w cpu clock (ick) and superhyway clock (shck) frequency division ratio setting 00010: 12 (ick), 6 (shck) clock operating mode 0, 1, 2 or 3 (after power-on reset) 00100: 12 (ick), 4 (shck) clock operating mode 12 (after power-on reset) 10000: 6 (ick), 6 (shck) register setting (register setting after initialized) other than above: setting prohibited the initial value of this field after power-on reset depends on the mode pins setting (see table 15.2).
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 620 of 1286 rej09b0158-0100 bit bit name initial value r/w description 19 18 17 16 bfc3 bfc2 bfc1 bfc0 0 undefined undefined undefined r r r r bus clock (b ck ) frequency division ratio setting 0011: 3 0100: 2 0101: 3/2 0110: 1 other than above: setting prohibited the initial value of this field after power-on reset depends on the mode pin setting (see table 15.2). writing is ignored. 15 to 12 ? 0 undefined undefined undefined r reserved the initial value of this field after power-on reset depends on the mode pins setting (see table 15.2). writing is ignored. 11 to 8 ? 0011 r reserved these bits are always read as 0011. the write value should always be 0011. 7 to 4 ? 0 undefined undefined undefined r reserved the initial value of this field after power-on reset depends on the mode pins setting (see table 15.2). writing is ignored. 3 2 1 0 p1fc3 p1fc2 p1fc1 p1fc0 0 1 undefined undefined r r r r indicates the division ratio of the external bus clock frequency. 0101: 3/2 0110: 1 the initial value of this field after power-on reset depends on the mode pin setting (see table 15.2). writing is ignored. note: * bits ifc and cfc in frqcr should be modified together.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 621 of 1286 rej09b0158-0100 15.4.2 pll control register (pllcr) pllcr is a 32-bit readable/writabl e register that controls the cl ock output on the clkout pin. this register can only be accessed in longwords. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 0 0 0 0 0 0 0 0 0 0 0 0 1 11 ? ckoff ? ? ? ? ? ? ? ? ? ? ? ? ?? r r/w r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 13 ? all 1 r reserved this bit is always read as 1. the write value should always be 1. writing 0 to any of these bits, the operation of this lsi is not guaranteed. 12 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 ckoff 0 r/w clkout output stop stops the clock output on the clkout pin. 0: clock is output on the clkout pin 1: clock is not output on the clkout pin 0 ? 1 r reserved this bit is always read as 1. the write value should always be 1.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 622 of 1286 rej09b0158-0100 15.5 notes on board design when using crystal resonator: place the crystal resonator and capacitors close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. xtal r sh7780 note: the value of cl1, cl2 and the damping resistance should be determined after consultation with the crystal resonator manufacturer. extal cl2 cl1 crystal resonator avoid crossing signal lines recommended values cl1 = cl2 = 0 to 33 pf r = 0 ? figure 15.2 points for attention when using crystal resonator when inputting external clock from extal pin: make no connection to the xtal pin. when using pll and dll circuit: separate each vdd-pll, v dd-dll, vss-pll, and vss- dll from the other vdd and vss lines at the bo ard power supply source, and insert resistors (rcb and rd) and bypass capacitors (cpb and cd) close to the pll and dll pins as noise filters.
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 623 of 1286 rej09b0158-0100 vdd-pll1 vss-pll1 sh7780 vdd-pll2 vss-pll2 vdd-pll3 vss-pll3 cpb11 0.1 f cpb12 rcb1 recommended values rcb1 = rcb2 = rcb3 = 4.7 ? cpb11 = cpb21 = cpb31 = 0.1 f cpb12 = cpb22 = cpb32 = 1 f rd1 = rd2 = 20 ? cd11 = cd21 = 0.1 f cd12 = cd22 = 1 f 1.25v 1 f 4.7 ? 4.7 ? 4.7 ? cpb21 0.1 f cpb22 rcb2 1 f cpb31 0.1 f cpb32 rcb3 1 f vdd-dll1 vss-dll1 vdd-dll2 vss-dll2 1.25v 20 ? 20 ? cd11 0.1 f cd12 rd1 1 f cd21 0.1 f cd22 rd2 1 f figure 15.3 points for attentio n when using pll and dll circuit
section 15 clock pulse generator (cpg) rev.1.00 dec. 13, 2005 page 624 of 1286 rej09b0158-0100
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 625 of 1286 rej09b0158-0100 section 16 watchdog timer and reset the reset and watchdog timer (wdt) control circuit comprises the reset control unit and wdt control unit which control the power-on reset sequence and a reset for on-chip peripheral modules and external devices. the wdt is a one-channel timer which can be used as the watchdog timer or interval timer. 16.1 features ? the watchdog timer unit monitors a system crash using a timer co unting at specified intervals. ? the watchdog timer unit generates a reset for on-chip peripheral modules when a wdt overflow occurs. ? a power-on reset or a manual reset can be sel ectable, when a manual reset is selected, the mresetout pin is asserted. ? generates the interval timer interrupt when counter overflow occurs in interval timer mode. ? the maximum time until the watchdog timer overflows is approximately 21 seconds (when the peripheral clock pck is 50 mhz). ? writing to wdt-related registers is not normally a llowed. a specified code in the upper bits of write data enables writing to the registers. wtcnt and wtcsr differ from other registers in being more difficult to write to. the procedure for writing to these registers is given below.
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 626 of 1286 rej09b0158-0100 figure 16.1 shows a block diagram of the wdt. preset mresetou t watchdog timer and reset status[1:0] internal reset request 2 wdtcnt wdtcsr wdtst comparator reset control circuit cpg internal reset request interrupt control circuit intc peripheral clock [legend] wdtbcnt: watchdog timer base counter wdtbst: watchdog timer base stop time register wdtcnt: watchdog timer counter wdtcsr: watchdog timer control/status register wdtst: watchdog timer stop time register wdtbcnt wdtbst overflow count-up signal clear figure 16.1 block diagram of wdt
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 627 of 1286 rej09b0158-0100 16.2 input/output pins table 16.1 shows the pin configuration of the reset control unit. table 16.1 pin configuration pin name function i/o description preset reset input power-on reset mresetout * 1 manual reset output output low level output during manual reset execution status1 * 2 processing state 1 indicate t he processor's operating status status0 * 3 processing state 0 output status1 high high low status0 high low low operating status reset sleep mode normal operation notes: 1. this pin is multiplexed with the dmac, h-udi and gpio pin. 2. this pin is multiplexed with the cmt channel 1 pin. 3. this pin is multiplexed with the cmt channel 0 pin.
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 628 of 1286 rej09b0158-0100 16.3 register descriptions table 16.2 shows the registers of the reset and watchdog timer. table 16.3 shows the register states in each processing mode. table 16.2 register configuration register name abbreviation r/w p4 address area 7 address access size sync clock watchdog timer stop time register wd tst r/w h'ffcc 0000 h'1fcc 0000 32 pck watchdog timer control/status register wdtcsr r/w h'ffcc 0004 h'1fcc 0004 32 pck watchdog timer base stop time register wdtbst r/w h'ffcc 0008 h'1fcc 0008 32 pck watchdog timer counter wdtcnt r h'ffcc 0010 h'1fcc 0010 32 pck watchdog timer base counter wdtbcnt r h'ffcc 0018 h'1fcc 0018 32 pck table 16.3 register states in each processing mode register name abbreviation power-on reset by preset pin power-on reset by wdt/h-udi manual reset by wdt/ multiple exception sleep by sleep instruction watchdog timer stop time register wdts t h'0000 0000 retained retained retained watchdog timer control/status register wdtcsr h'0000 0000 retained retained retained watchdog timer base stop time register wdtbst h'0000 0000 retained retained retained watchdog timer counter wdtcnt h'0000 0000 retained retained retained watchdog timer base counter wdtbcnt h'0000 0000 retained retained retained
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 629 of 1286 rej09b0158-0100 16.3.1 watchdog timer st op time register (wdtst) wdtst is a readable/writable 32 -bit register that specifies the time until a watchdog timer overflows. the time until wdtcnt overflows becomes the minimum value when set h'001 to the bits 11 to 0, and the maximum value when set h'000 to the bits 11 to 0. use a longword access to write to the wdtst, with h'5a in the bits 31 to 24. the reading value of bits 31 to 24 is always h'00. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: (given code) r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wdtst ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 24 (given code) h'00 r/w reserved (given code for writing) these bits are always read as h'00. to write to this register, the write value must be h'5a. 23 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 wdtst all 0 r/w counter value
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 630 of 1286 rej09b0158-0100 16.3.2 watchdog timer contro l/status register (wdtcsr) wdtcsr is a readable/writable 32-bit register that comprises the timer mode-selecting bit and overflow flags. use a longword acces s to write to the wdtcsr, with h'a5 in the bits 31 to 24. the reading value of bits 31 to 24 is always h'00. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? iovf wovf rsts wt/it tme ? ? ? ? ? ? ?? r r r r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: (given code) bit bit name initial value r/w description 31 to 24 (given code) h'00 r/w reserved (given code for writing) these bits are always read as h'00. to write to this register, the write value must be h'a5. 23 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 tme 0 r/w timer enable specifies starting and stopp ing of timer operation. 0: stops counting up 1: starts counting up 6 wt/it 0 r/w timer mode select specifies whether the wdt is used as a watchdog timer or interval timer. up counting may not be performed correctly if this bit is modified while the wdt is running. 0: interval timer mode 1: watchdog timer mode
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 631 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 rsts 0 r/w reset select specifies the kind of reset to be performed when wdtcnt overflows in watchdog timer mode. this setting is ignored in interval timer mode. 0: power-on reset 1: manual reset 4 wovf 0 r/w watchdog timer overflow flag indicates that wdtcnt has overflowed in watchdog timer mode. this flag is not set in interval timer mode. 0: an overflow has not occurred 1: an overflow on wdtcnt has occurred 3 iovf 0 r/w interval timer overflow flag indicates that wdtcnt has overflowed in interval timer mode. this flag is not set in watchdog timer mode. 0: an overflow has not occurred 1: an overflow on wdtcnt has occurred 2 to 0 ? r all 0 reserved these bits are always read as 0. the write value should always be 0. 16.3.3 watchdog timer base st op time register (wdtbst) wdtbst is a readable/writable 32-bit register that clears wdtbcnt. use a longword write access to clear the wdtbcnt, with h' 55 in the bits 31 to 24. the r eading value of this register is always h'00. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: ?? ? ? ? ?? ? ? ?? ?? ? ? ? ? ?? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r r r r r r r r r r r r r r rr bit: initial value: r/w: (given code)
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 632 of 1286 rej09b0158-0100 16.3.4 watchdog timer counter (wdtcnt) wdtcnt is a 32-bit read-only regi ster that comprises 12-bit watc hdog timer counter and counts up on the wdtbcnt overflow signal. when wdtcnt overflows, a reset is generated in watchdog timer mode, or an interrupt is generate d in interval timer mode. writing to wdtcnt is invalid. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wdtcnt ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 16.3.5 watchdog timer base counter (wdtbcnt) wdtbcnt is a 32-bit read-only register that comprises 18-bit counter and counts up on the peripheral clock (pck). when wdtbcnt overflows, wdtcnt is counted up and wdtbcnt is cleared to 0. writing to wdtbcnt is invalid. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wdtbcnt ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 wdtbcnt r r r r r r r r r r r r r r rr bit: initial value: r/w:
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 633 of 1286 rej09b0158-0100 16.4 operation 16.4.1 reset request power-on reset and manual reset are available. these sources are follows. (1) power-on reset ? input low level via preset pin. ? the wdtcnt overflows when the wt/it bit in the wtcsr is 1, and the rsts bit is 0. ? the h-udi reset occurs (for details, see section 30, user debugging inte rface (h-udi)). power_on_reset() { expevt = h'0000 0000; vbr = h'0000 0000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.(i0-i3) = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(poweron); pc = h'a000 0000; } (2) manual reset ? when a general exception other than a user break occurs while the bl bit is set to 1 in sr ? when the wdtcnt overflows while the wt/it b it and the rsts bit are set to 1 in wtcsr.
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 634 of 1286 rej09b0158-0100 manual_reset() { expevt = h'0000 0020; vbr = h'0000 0000; sr.md = 1; sr.rb = 1; sr.bl = 1; sr.(i0-i3) = b'1111; sr.fd = 0; initialize_cpu(); initialize_module(manual); pc = h'a000 0000; } 16.4.2 using watchdog timer mode 1. set the wdtcnt overflow interval value in wdtst. 2. set the wt/it bit in wdtcsr to 1, select the type of reset with the rsts bit. 3. when the tme bit in wtcsr is set to 1, the wdt count starts. 4. during operation in watchdog timer mode, clear to the wdtcnt or wdtbcnt periodically so that wdtcnt does not overflow. see se ction 16.4.5, clearing wdt counter for wdt counter clear method. 5. when the wdtcnt overflows, the wdt se ts the wovf flag in wdtcsr to 1, and generates a reset of the type specified by the rsts bit. after reset operation, the wdtcnt and wdtbcnt continues counting again. 16.4.3 using interval timer mode when the wdt is operating in interval timer mode , an interval timer interrupt is generated each time the counter overflows. this enables interrupts to be generated at fixed intervals. 1. set the wdtcnt overflow time in wdtst. 2. clear the wt/it bit in wdtcsr to 0. 3. when the tme bit in wdtcsr is set to 1, the wdt count starts. 4. when the wdtcnt overflows, the wdt sets th e iovf flag in wdtcsr to 1, and sends an interval timer interrupt (iti) request to intc. the counter continues counting.
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 635 of 1286 rej09b0158-0100 figure 16.2 shows a wdt counting up operation. setting value of wdtst h'0000 0000 counting up with overflow signal of wdtbcnt interval timer mode: clear counter when overflowed clear counter when overflowed wdt mode: clear counter after reset operation counting up with pck start counting up set flag time time wdtcnt value h'0003 ffff h'0000 0000 tme wovf, iovf wdtbcnt value reset (internal) interval timer mode wdt mode figure 16.2 wdt counting up operation 16.4.4 time for wdt overflow wdtbcnt is a 18-bit up-counter operated on the peripheral clock (pck). wdtbcnt is cleared when h'55 is set to the bits 31 to 24 in wdtbst. if the peripheral clock frequency is 50 mhz, the wdtbcnt overflow time is approximately 5.243 ms (= 2^18 [bit] 1/50 [mhz]). wdtcnt is a 12-bit counter, starts count up operation when overflow occurs in wdtbcnt. the time until wdtcnt overflows becomes the maxi mum value when h'000 are set to wdtst. where the peripheral clock frequency is 50 mhz, the maximum overflow time is approximately 21.475 s (= 2^12 [bit] 5.243 [ms]).
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 636 of 1286 rej09b0158-0100 and the time until wdtcnt overflows becomes the minimum value when h'001 is set to wdtst. the minimum overflow time is approximately 5.243 ms (= 2^1 [bit] 5.243 [ms]). 16.4.5 clearing wdt counter writing h'55 to wdtbst with longword access clears wdtbcnt and writing the overflow setting value to wdtst clears wdtcnt. 16.5 status pin change timing during reset 16.5.1 power-on reset by preset a power-on reset is to initialize the on-chip pll circuit when this lsi goes to the power-on reset state by the perset pin low level input and then it is necessary to ensure the synchronization settling time of the pll circuit. therefore, do not input high level to the preset pin during the synchronization settling time of the pll. the pll synchronization settling time is the total value of the pll1 synchronization settling time and the pll2 synchronization settling time. after the preset pin input level is changed from low level to high level, the reset state is continued during the reset holding time in the lsi. the reset holding time is 20 clock cycles of the xtal clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (pck). the status [1:0] pins output timing that indicat es the reset state is asynchronous, and that indicates a normal operation is synchronous with the peripheral clock (pck) and asynchronous with both the xtal clock and the clkout pin output clock. turning on power supply when turning on the power supply, the preset pin input level should be low level. and the trst pin input level should be low level to initialize the h-udi.
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 637 of 1286 rej09b0158-0100 vdd trst input preset input clkout output status[1:0] output hh (reset) ll (normal) xtal (oscillator) stabilization time pll synchronization settling time reset holding time xtal (oscillator) figure 16.3 status output during power-on preset input during normal operation it is necessary to ensure the pll synchronization settling time when the preset input during normal operation. clkout output status[1:0] output hh (reset) ll (normal) ll (normal) pll synchronization settling time reset holding time xtal (oscillator) preset input figure 16.4 status output by reset input during normal operation
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 638 of 1286 rej09b0158-0100 preset input during sleep mode it is necessary to ensure the pll oscillation time when power-on reset generates by the preset pin low revel input during sleep mode. clkout output status[1:0] output hh (reset) ll (normal) hl (sleep) pll synchronization settling time reset holding time xtal (oscillator) preset input figure 16.5 status output by reset input during sleep mode 16.5.2 power-on reset by watchdog timer overflow the transition time from the watchdog timer overflowed to the power-on reset state (watchdog timer reset setup time) is 1 clock cycle of the xt al clock and thereafter equal to or more than 5 clock cycles of the peripheral clock (pck). the power-on reset time (w atchdog timer reset holding time) by the watchdog timer overflowed is 3774 clock cycles of the xtal clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (pck). the status [1:0] pins output timing that indicat es the reset state or a normal operation is asynchronous with both the xtal clock and the clkout pin output clock because the status [1:0] pins output timing is synchronous with the peripheral clock (pck).
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 639 of 1286 rej09b0158-0100 power-on reset by watchdog timer overflowed in normal operation clkout output wdt overflow signal status[1:0] output hh (reset) ll (normal) ll (normal) wdt reset setup time wdt reset holding time xtal (oscillator) figure 16.6 status output by wa tchdog timer overflow power-on reset during normal operation power-on reset by watchdog tim er overflowed in sleep mode clkout output status[1:0] output wdt overflow signal hh (reset) hl (sleep) ll (normal) xtal (oscillator) wdt reset setup time wdt reset holding time figure 16.7 status output by wa tchdog timer overflow power-on reset during sleep mode
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 640 of 1286 rej09b0158-0100 16.5.3 manual reset by watchdog timer overflow the transition time from watchdog timer overflow ed to manual reset state (watchdog timer reset setup time) is 1 clock cycle of the xtal clock and thereafter equal to or more than 5 clock cycles of the peripheral clock (pck). the manual reset time (watchdog timer manual reset holding time) by the watchdog timer overflowed is equal to or more than 3774 clock cycles of the xtal clock. the status [1:0] pins output timing that indicat es the reset state or a normal operation is asynchronous with both the xtal clock and the clkout pin output clock because the status [1:0] pins output timing is synchronous with the peripheral clock (pck). manual reset by watchdog timer overflowed in normal operation clkout output wdt overflow signal status[1:0] output hh (reset) ll (normal) ll (normal) xtal (oscillator) wdt reset setup time manual reset holding time mresetout output figure 16.8 status output by wa tchdog timer overflow manual reset during normal operation
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 641 of 1286 rej09b0158-0100 manual reset by watchdog tim er overflowed in sleep mode clkout output wdt overflow signal status[1:0] output hh (reset) hl (sleep) ll (normal) xtal (oscillator) wdt reset setup time wdt reset holding time mresetout output figure 16.9 status output by wa tchdog timer overflow manual reset during sleep mode
section 16 watchdog timer and reset rev.1.00 dec. 13, 2005 page 642 of 1286 rej09b0158-0100
section 17 power-down mode rev.1.00 dec. 13, 2005 page 643 of 1286 rej09b0158-0100 section 17 power-down mode in power-down modes, some of the on-chip peripheral modules and the cpu functions are halted, enabling power consumption to be reduced. 17.1 features the sh7780 power-down mode has the following features. ? supports sleep mode and module standby mode ? supports rtc power supply backup mode where the power supply for only the rtc is held and other power supp lies are turned off ? supports ddr-sdram power supply backup mode where the power supply for only the 2.5- v power supplied modules are held and other power supplies are turned off 17.1.1 types of power-down modes the types and functions of power-down modes are as shown below. ? sleep mode ? module standby state ? rtc power supply backup mode ? ddr-sdram power supply backup mode table 17.1 lists the conditions needed to make a transition from the program execution state to a power-down mode, states of the cpu and on-chip peripheral modules in each mode, and methods to leave each power-down mode.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 644 of 1286 rej09b0158-0100 table 17.1 pow er-down modes state on-chip module power- down mode transition condition cpg cpu on-chip memory dmac rtc others pin ddr-sdram cancellation sleep sleep instruction executed operated halted (register contents retained) retained operated operated operated retained auto-refresh or self- refresh * 3 - interrupt - power-on reset - manual reset module standby corresponding bit in mstpcr set to 1 (see section 17.3.1) operated operated retained selected modules halted operated selected modules halted retained auto-refresh or self-refresh clear corresponding bit in mstpcr to 0 (see section 17.3.1) ddr- sdram power supply backup * 1 * 3 * 4 see section 17.6 halted halted halted halted halted halted all modules except for the 2.5-v interfaces are in high- impedance states self refresh power-on reset rtc power supply backup * 2 * 3 * 4 see section 17.7 halted halted retained halted operated halted all modules except for the rtc interface are in the high- impedance states undefined (refresh is not performed) power-on reset notes: 1. because power supplies (1.25 v and 3.3 v) other than the 2.5v power supply are stopped in this mode, only the i/os of the ddrif continue to operate. modules including the ddrif stop operating and do not hold register information. 2. because power supplies (1.25 v, 2.5 v, and 3.3 v) other than the rtc power supply are stopped in this mode, modules other th an the rtc stop operating and do not hold register information. 3. satisfy both transition conditions wh en both backups by the rtc and ddr-sdram power supplies are necessary. 4. do not input signals to i/o pins wh ile the i/o power supply (vddq) is stopped.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 645 of 1286 rej09b0158-0100 17.2 input/output pins table 17.2 shows the pin configuration of the power-down modes. table 17.2 pin configuration pin name function i/o description status1 processing state 1 indicate the processor's operating status status0 processing state 2 output status1 high high low status0 high low low operating status reset sleep mode normal operation note: these pins are multiplexed with the cmt pins. 17.3 register descriptions table 17.3 shows the register configuration for power-down mode. table 17.4 shows the register states in each processing mode. table 17.3 register configuration register name abbreviation r/w p4 address area 7 address access size sync clock standby control register mstpcr r/w h'ffc8 0030 h'1fc8 0030 32 pck table 17.4 register states in each processing mode register name abbreviation power-on reset by preset pin power-on reset by wdt/h-udi manual reset by wdt/ multiple exception sleep by sleep instruction standby control register mstpcr h' 0000 0000 retained retained retained
section 17 power-down mode rev.1.00 dec. 13, 2005 page 646 of 1286 rej09b0158-0100 17.3.1 standby control register (mstpcr) mstpcr is a 32-bit readable/writable register th at can individually start or stop the module assigned to each bit. mstpcr can be accessed only in longwords. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ?? r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w rr bit: initial value: r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? mstp21 ? ?? ? mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 ? ? ? ? ? ? ? ? ?? r r r r r r/w r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 mstp21 0 r/w module stop bit 21 to make a transition to the dmac module standby mode, confirm that the dme bits in dma operation registers (dmaor0 and dmaor1) are cleared to 0 or all te bits in dma channel control registers (chcrn, n = 0 to 11) are set to 1. 0: supplies the clock to the dmac module 1: stops the clock supply to the dmac module 20 to 14 ? all 0 r reserved these bits are is always re ad as 0. the write value should always be 0.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 647 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 to 8 mstp[13:8] all 0 r/w module stop bit [13:8] 0: supplies the clock to the corresponding module 1: stops the clock supply to the corresponding module [13]: mmcif, [12]: flctl, [11]: rtc, [10]: tmu channels 0 to 2, [9]: tmu channels 3 to 5, [8]: cmt 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 to 0 mstp[5:0] all 0 r/w module stop bit [5:0] 0: supplies the clock to the corresponding module 1: stops the clock supply to the corresponding module [5]: scif channel 0, [4]: scif channel 1, [3]: siof, [2]: hspi, [1]: ssi, [0]: hac note: if the sleep instruction is issued or the operating frequency is changed, note the below (1) and (2), when the dmac module proceed to its module standby mode. (1) set to 1 dmac bit in mstpcr bit 21 a fter confirm the dma transfer has finished. (2) perform two dummy read operations for mstpr before the sleep instruction is issued or the operating frequency is changed.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 648 of 1286 rej09b0158-0100 17.4 sleep mode 17.4.1 transition to sleep mode a transition to the sleep mode is made by ex ecuting the sleep instru ction in the program execution state. although the cpu stops operating after execution of the sleep instruction, the contents of the cpu registers are held. on-chip peripheral modules other than the cpu continue to operate and the clock continues to be output on the clkout pin. in sleep mode, a high-level signal is output at the status1 pin, and a low-level signal at the status0 pin. 17.4.2 cancellation of sleep mode the sleep mode is canceled by an interrupt (nmi, irq/ irl[7:0] , or on-chip modules) and a reset. since an interrupt is accepted in slee p mode even if the bl bit in sr is set to 1, save the contents of spc and ssr to the stack before execu ting the sleep instruct ion when necessary. cancellation by interrupt: the sleep mode can be canceled with an nmi, irq/ irl[7:0] , or on- chip module interrupt, and the interrupt exception handling then starts. a corresponding code to the interrupt is stored in intvent. cancellation by reset: the sleep mode is canceled with a power-on reset by the preset pin, a power-on reset by a watchdog timer overflow, or a manual reset.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 649 of 1286 rej09b0158-0100 17.5 module standby state this lsi supports the module standby state, where the clock supplied to on-chip modules is stopped. 17.5.1 transition to module standby mode setting a corresponding bit in the standby control register (mstpcr) to 1 will stop the clock supply. modules in module standby state k eep the state immediately before the transition to the module standby state. the registers keep the contents before halted, and the external pins keep the functions before halted. at waking up from the module standby state, operation is restarted from the condition immediately before the registers and external pins have halted. note: make sure to set the mstp bit to 1 while the modules have completed the operation and are in an idle state, with no interrupt sources from the external pins or other modules. 17.5.2 cancellation of modul e standby mode and resume the module standby mode can be canceled by cl earing a corresponding bit in the standby control register (mstpcr) to 0.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 650 of 1286 rej09b0158-0100 17.6 ddr-sdram power supply backup 17.6.1 self-refresh and initialization to preserve the contents of the ddr-sdram with battery backup, make sure that the ddr- sdram is in the self-refresh mode before turnin g off the system power su pply. when the system power supply is turned on, whether initialization of the ddr-sdram and cancellation of the self- refresh mode is needed will depend on whether the ddr-sdram has been in self-refresh mode or has not been initialized. both a transition to and a cancellation of the self-refresh mode are done for the ddr-sdram by a command. rmode bit: bit 33 in mim. the initial value is 0. setting this bit to 1 after setting the dre bit in mim to 1 causes the ddrif to start the sequence for a transition to the self-refresh mode. for details, see section 12.5.5 (1), self-refresh mode. sms bits: bits 2 to 0 in scr. sms = b'011. these bits are used to assert the cke signal (high) and to cancel the self-refresh mode with the desl command. bkprst signal: to prevent the cke signal from being unstable when turning on or off the lsi power supply, the bkprst signal must be driven to low in synchronization with turning the lsi power supply on or off. the bkprst signal must be kept low while the system power supply is turned off. transition to self-refresh mode completed system power supply turned off system power supply turned on power-on reset canceled cke asserted by sms bits in scr delay time of lsi internal reset preset ddrif reset vdd, vddq (1.25 v, 3.3 v) cke min 1 ms bkprst min 0 ms min 0 ms figure 17.1 ddr-sdram interface operation when turning system power supply on/off
section 17 power-down mode rev.1.00 dec. 13, 2005 page 651 of 1286 rej09b0158-0100 17.6.2 ddr-sdram backup sequence when turning off system power supply the sequence when the system power s upply is turned off is shown below. figure 17.1 shows the sequence of a transition to the self-refresh mode to turn off the system power supply. (a) confirm that all transactions of the ddrif by on-chip peripheral modules are completed. (b) issue the all bank precharge command (preall) with bits sms2 to sms0 in scr by software. activated banks will be closed. afte r that, issue the auto-refresh command (refa) with bits sms in scr to pe rform refresh on all rows. (c) specify the dre and rmode bits in mim of the ddrif to put the sdram into the self- refresh mode. at this time, keep the dce bit set to 1. the self-refresh command will be automatically issued and the cke signal will be driven to low by the ddrif. after that, the ddr-sdram will automatically enter the power-down mode. (d) the selfs bit in mim is set to 1. (e) drive the bkprst signal from high to low. immediatel y after the system power supply is turned off, the cke output may be unstable. before turning off the system power supply, use the external bkprst signal to keep the cke signal input of the ddr-sdram low until canceling the power-on reset as shown in figure 17.1. (f) turn off the system power supply (1.25 v and 3.3 v). note that in the transition from auto-refresh stat e to self-refresh state, the current auto-refresh state should have been finished or been disabled before the transition. after the system power supply is turned on, the cke output may remain unstable until the clock is supplied after the lsi power supply has become stable. use the external bkprst signal to keep the cke signal input of the ddr-sdram low until canceling the power-on reset as shown in figure 17.1.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 652 of 1286 rej09b0158-0100 (a) confirm that traffic to ddrif by on-chip peripheral modules is completed (b) (c) (d) (e) (f) set scr to issue preall and refa commands set mim to issue self-refresh command set mim: selfs = 1 drive bkprst high to low turn off system power supply time processing command (refa/nop) preall refa refs low high cke sdram state performs auto-refresh at regular intervals enters idle state after refreshing once performs self-refresh figure 17.2 sequence for turning off sy stem power supply in self-refresh mode
section 17 power-down mode rev.1.00 dec. 13, 2005 page 653 of 1286 rej09b0158-0100 17.7 rtc power supply backup 17.7.1 transition to rtc power supply backup to turn on the rtc battery backup with the system power supply turned off, assert the xrtcstbi signal before the voltage of the vdd (1.25v) power supply starts to drop. this function can be used to reduce the vdd curr ent. when the rtc clock is supplied to the rtc crystal oscillator, each counter of the rtc is still being counted up while the vdd power supply is not being supplied. 17.7.2 cancellation of rtc power supply backup the rtc power supply backup mode is cancelled by a power-on reset. even if an interrupt occurs during the rtc power supply backup mode, it is invalid because of th e power-on reset. the cancellation procedure is as follows. 1. the preset signal is low before the vdd power supply starts. 2. negate the xrtcstbi signal after the vdd becomes stable and ensure the power-on oscillation settling time to prevent the lsi from being damaged by the transient current caused of the vdd-rtc (3.3v) being supplied. 3. keep the preset low until the rtc has been reset, and then negate the preset signal. table 17.5 shows the pin configuration related to power-down modes. table 17.5 pin configuration pin name function i/o description xrtcstbi rtc standby input when this pin becom es low, the rtc goes to the rtc power supply backup mode.
section 17 power-down mode rev.1.00 dec. 13, 2005 page 654 of 1286 rej09b0158-0100 vdd-rtc vdd x rtcstbi preset (1) (1) power-on oscillation settling time (2) internal reset delay time to the rtc (2) system power supply turned off system power supply turned on rtc power supply backup canceled power-on reset canceled min 1 ms min 1 ms figure 17.3 sequence for turn ing system power supply on/off
section 17 power-down mode rev.1.00 dec. 13, 2005 page 655 of 1286 rej09b0158-0100 17.8 mode transitions figure 17.4 shows the mode transitions. power-off state multiplication ratio change sleep normal operation (1) power-on oscillation settling time module standby ddr-sdram power supply backup rtc power supply backup (1) (1) figure 17.4 mode transition diagram
section 17 power-down mode rev.1.00 dec. 13, 2005 page 656 of 1286 rej09b0158-0100 17.9 status pin change timing 17.9.1 in reset refer to section 16.5, status pin change timing during reset. 17.9.2 in sleep figure 17.5 shows the state of output pins in sleep mode. interrupt request ll (normal) hl (sleep) ll (normal) clkout irqout status[1:0] figure 17.5 status pins ou tput from sleep to interrupt
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 657 of 1286 rej09b0158-0100 section 18 timer unit (tmu) this lsi includes an on-chip 32-bit timer unit (tmu), which has six channels (channels 0 to 5). 18.1 features the tmu has the following features. ? ? ? ? ? ? ?
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 658 of 1286 rej09b0158-0100 figure 18.1 shows a block diagram of the tmu. tclk [legend] prescaler to each channel clock controller bus interface rtcclk peripheral bus tuni0 tuni1 tuni2 icpi2 tuni3 tuni4 tuni5 pck tcr tstr0 tcor tcr tcor tcor tcpr tstr1 tcnt: tcor: tcpr: tcr: tocr: tstr0, tstr1: timer counter timer constant register input capture register 2 (only in channel 2) timer control register timer output control register timer start register tocr tcr tcnt tcnt tcnt channel 0, 1 channel 2 channel 3, 4, 5 tclk controller clock controller interrupt controller clock controller interrupt controller clock controller interrupt controller figure 18.1 block diagram of tmu
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 659 of 1286 rej09b0158-0100 18.2 input/output pins table 18.1 shows the tmu pin configuration. table 18.1 pin configuration pin name function i/o description tclk * clock input/output i/o c hannel 0, 1 and 2 ex ternal clock input pin/channel 2 input capture control input pin/rtc output pin (shared with rtc) note: this pin is multiplexed with the lbsc and gpio pins.
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 660 of 1286 rej09b0158-0100 18.3 register descriptions table 18.2 shows the tmu register configuration. table 18.3 show s the register states in each processing mode. table 18.2 register configuration channel register name abbrev. r/w p4 address area 7 address size sync clock timer output control register tocr r/w h'ffd8 0000 h'1fd8 0000 8 p ck 0, 1, 2 common timer start register 0 tstr0 r/w h'ffd8 0004 h'1fd8 0004 8 p ck timer constant register 0 tcor0 r/w h'ffd8 0008 h'1fd8 0008 32 p ck timer counter 0 tcnt0 r/w h'ffd8 000c h'1fd8 000c 32 p ck 0 timer control register 0 tcr0 r/w h'ffd8 0010 h'1fd8 0010 16 p ck timer constant register 1 tcor1 r/w h'ffd8 0014 h'1fd8 0014 32 p ck timer counter 1 tcnt1 r/w h'ffd8 0018 h'1fd8 0018 32 p ck 1 timer control register 1 tcr1 r/w h'ffd8 001c h'1fd8 001c 16 p ck timer constant register 2 tcor2 r/w h'ffd8 0020 h'1fd8 0020 32 p ck timer counter 2 tcnt2 r/w h'ffd8 0024 h'1fd8 0024 32 p ck timer control register 2 tcr2 r/w h'ffd8 0028 h'1fd8 0028 16 p ck 2 input capture register 2 tcpr2 r h'ffd8 002c h'1fd8 002c 32 p ck 3, 4, 5 common timer start register 1 tstr1 r/w h'ffdc 0004 h'1fdc 0004 8 p ck timer constant register 3 tcor3 r/w h'ffdc 0008 h'1fdc 0008 32 p ck timer counter 3 tcnt3 r/w h'ffdc 000c h'1fdc 000c 32 p ck 3 timer control register 3 tcr3 r/w h'ffdc 0010 h'1fdc 0010 16 p ck timer constant register 4 tcor4 r/w h'ffdc 0014 h'1fdc 0014 32 p ck timer counter 4 tcnt4 r/w h'ffdc 0018 h'1fdc 0018 32 p ck 4 timer control register 4 tcr4 r/w h'ffdc 001c h'1fdc 001c 16 p ck timer constant register 5 tcor5 r/w h'ffdc 0020 h'1fdc 0020 32 p ck timer counter 5 tcnt5 r/w h'ffdc 0024 h'1fdc 0024 32 p ck 5 timer control register 5 tcr5 r/w h'ffdc 0028 h'1fdc 0028 16 p ck
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 661 of 1286 rej09b0158-0100 table 18.3 register states in each processing mode channel register name abbrev. power-on reset by preset pin/ wdt/h-udi manual reset by wdt/ multiple exception sleep by sleep instruction module standby timer output control register tocr h'00 h'00 retained retained 0, 1, 2 common timer start register 0 tstr 0 h'00 h'00 retained retained timer constant register 0 tcor0 h'ff ff ffff h'ffff ffff retained retained timer counter 0 tcnt0 h'ffff ffff h'ffff ffff retained retained 0 timer control register 0 tcr0 h'0000 h'0000 retained retained timer constant register 1 tcor1 h'ff ff ffff h'ffff ffff retained retained timer counter 1 tcnt1 h'ffff ffff h'ffff ffff retained retained 1 timer control register 1 tcr1 h'0000 h'0000 retained retained timer constant register 2 tcor2 h'ff ff ffff h'ffff ffff retained retained timer counter 2 tcnt2 h'ffff ffff h'ffff ffff retained retained timer control register 2 tcr2 h'0000 h'0000 retained retained 2 input capture register 2 tcpr2 retained retained retained retained 3, 4, 5 common timer start register 1 tstr 1 h'00 h'00 retained retained timer constant register3 tcor3 h'ff ff ffff h'ffff ffff retained retained timer counter 3 tcnt3 h'ffff ffff h'ffff ffff retained retained 3 timer control register 3 tcr3 h'0000 h'0000 retained retained timer constant register 4 tcor4 h'ff ff ffff h'ffff ffff retained retained timer counter 4 tcnt4 h'ffff ffff h'ffff ffff retained retained 4 timer control register 4 tcr4 h'0000 h'0000 retained retained timer constant register 5 tcor5 h'ff ff ffff h'ffff ffff retained retained timer counter 5 tcnt5 h'ffff ffff h'ffff ffff retained retained 5 timer control register 5 tcr5 h'0000 h'0000 retained retained
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 662 of 1286 rej09b0158-0100 18.3.1 timer output co ntrol register (tocr) tocr is an 8-bit readable/writable register that specifies whether external pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 tcoe ? ? ? ? ? ? ? r/w r r r r r r r bit: initial value: r/w: bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tcoe 0 r/w timer clock pin control specifies whether timer clock pin tclk is used as the external clock or input capture control input pin, or as the on-chip rtc output clock output pin. 0: timer clock pin (tclk) is used as external clock input or input capture control input pin 1: timer clock pin (tclk) is used as on-chip rtc output clock output pin
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 663 of 1286 rej09b0158-0100 18.3.2 timer start register (tstr0, tstr1) tstr is an 8-bit readable/writable register th at specifies whether tcnt in each channel is operated or stopped. ? 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 str0 str1 str2 ? ? ? ? ? r/w r/w r/w r r r r r bit: initial value: r/w: bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 str2 0 r/w counter start 2 specifies whether tcnt2 is operated or stopped. 0: tcnt2 count operation is stopped 1: tcnt2 performs count operation 1 str1 0 r/w counter start 1 specifies whether tcnt1 is operated or stopped. 0: tcnt1 count operation is stopped 1: tcnt1 performs count operation 0 str0 0 r/w counter start 0 specifies whether tcnt0 is operated or stopped. 0: tcnt0 count operation is stopped 1: tcnt0 performs count operation
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 664 of 1286 rej09b0158-0100 ? 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 str3 str4 str5 ? ? ? ? ? r/w r/w r/w r r r r r bit: initial value: r/w: bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 str5 0 r/w counter start 5 specifies whether tcnt5 is operated or stopped. 0: tcnt5 count operation is stopped 1: tcnt5 performs count operation 1 str4 0 r/w counter start 4 specifies whether tcnt4 is operated or stopped. 0: tcnt4 count operation is stopped 1: tcnt4 performs count operation 0 str3 0 r/w counter start 3 specifies whether tcnt3 is operated or stopped. 0: tcnt3 count operation is stopped 1: tcnt3 performs count operation
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 665 of 1286 rej09b0158-0100 18.3.3 timer constant register (tcorn) (n = 0 to 5) the tcor registers are 32-bit readable/writable registers. when a tcnt counter underflows while counting down, the tcor value is set in that tcnt, which continues counting down from the set value. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: r/w: 18.3.4 timer counter (tcntn) (n = 0 to 5) the tcnt registers are 32-bit r eadable/writable registers. each tcnt counts down on the input clock selected by the tpsc2 to tpsc0 bits in tcr. when a tcnt counter underflows while counting down, the unf flag is set in tcr of the corresponding channel. at the same time, the tcor value is set in tcnt, and the count-down operation continues from the set value. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: r/w:
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 666 of 1286 rej09b0158-0100 18.3.5 timer control regist ers (tcrn) (n = 0 to 5) the tcr registers are 16-bit read able/writable registers. each tcr selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating tcnt underflow is set to 1. tcr2 is also used for input capture control and control of interrupt generation in the event of input capture. ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 tpsc0 tpsc1 tpsc2 ckeg0 ckeg1 unie ? ? unf ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r r r/w r r r r r rr bit: initial value: r/w: ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 tpsc0 tpsc1 tpsc2 ckeg0 ckeg1 unie icpe0 icpe1 unf icpf ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 icpf * 1 0 r/w input capture interrupt flag status flag, provided in channel 2 only, which indicates the occurrence of input capture. 0: input capture has not occurred [clearing condition] when 0 is written to icpf 1: input capture has occurred [setting condition] when input capture occurs * 2 8 unf 0 r/w underflow flag status flag that indicate s the occurrence of tcnt underflow. 0: tcnt has not underflowed [clearing condition] when 0 is written to unf 1: tcnt has underflowed [setting condition] when tcnt underflows * 2
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 667 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 6 icpe1 * 1 icpe0 * 1 0 0 r/w r/w input capture control these bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. the ckeg bits specify whether the rising edge or falling edge of the tclk pin is used to set the tcnt2 value in tcpr2. the tcnt2 value is set in tcpr2 only when the icpf bit in tcr2 is 0. when the icpf bit is 1, tcpr2 is not set in the event of input capture. 00: input capture function is not used. 01: setting prohibited 10: input capture function is used, but interrupt due to input capture (ticpi2) is not enabled. data transfer request is sent to the dmac in the event of input capture. 11: input capture function is used, and interrupt due to input capture (ticpi2) is enabled. 5 unie 0 r/w underflow interrupt control controls enabling or disabling of interrupt generation when the unf status flag is set to 1, indicating tcnt underflow. 0: interrupt due to underflow (tuni) is disabled 1: interrupt due to underflow (tuni) is enabled 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 these bits select the external clock input edge when an external clock is selected or the input capture function is used. 00: count/input capture register set on rising edge 01: count/input capture register set on falling edge 1x: count/input capture register set on both rising and falling edges
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 668 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler 2 to 0 these bits select the tcnt count clock. 000: counts on pck/4 001: counts on pck/16 010: counts on pck/64 011: counts on pck/256 100: counts on pck/1024 101: setting prohibited 110: counts on on-chip rtc output clock (rctclk) 111: counts on external clock (tclk) * 3 notes: x: don't care 1. reserved bit in channel 0 or 1 (initial value is 0, and can only be read). 2. writing 1 does not change the val ue; the previous value is retained. 3. do not set in channels 3, 4, and 5. 18.3.6 input captur e register 2 (tcpr2) tcpr2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. the input capture function is controlled by means of the icpe and ckeg bits in tcr2. when input capture occurs, the tcnt2 value is copied into tcpr2. the value is set in tcpr2 only when the icpf bit in tcr2 is 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: r/w: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 669 of 1286 rej09b0158-0100 18.4 operation each channel has a 32-bit timer counter (tcnt) and a 32-bit timer constant register (tcor). each tcnt performs count-down operation. the channels have an auto -reload function that allows cyclic count operations, and can also perf orm external event counting. channel 2 also has an input capture function. 18.4.1 counter operation when one of bits str0 to str2 in tstr is set to 1, the tcnt for the corresponding channel starts counting. when tcnt underflows, the unf fl ag in tcr is set. if the unie bit in tcr is set to 1 at this time, an interrupt request is sent to the cpu. at the same time, the value is copied from tcor into tcnt, and the count-down continues (auto-reload function). (1) example of count operation setting procedure figure 18.2 shows an example of the count operation setting procedure.
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 670 of 1286 rej09b0158-0100 select operation select count clock underflow interrupt generation setting input capture interrupt generation setting when using input capture of channel 2 timer constant register setting set initial timer counter value start count (1) (1) (2) (3) (4) (5) (6) (2) (3) (4) (5) (6) note: when an interrupt is generated, clear the source flag in the interrupt handler. if the interrupt enabled state is set without clearing the flag, another interrupt will be generated. select the count clock with the tpsc2 to tpsc0 bits in tcr. when the external clock (tclk) is selected, specify the external clock edge with the ckeg1 and ckeg0 bits in tcr. specify whether an interrupt is to be generated on tcnt underflow with the unie bit in tcr. when the input capture function is used, set the icpe bits in tcr, including specification of whether the interrupt function is to be used. set a value in tcor. set the initial value intcnt. set the str bit to 1 in tstr to start the count. figure 18.2 example of coun t operation setting procedure
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 671 of 1286 rej09b0158-0100 (2) auto-reload count operation figure 18.3 shows the tcnt auto-reload operation. tcnt value tcor h'0000 0000 str0 to str5 unf tcor value set in tcnt on underflow time figure 18.3 tcnt auto-reload operation (3) tcnt count timing ? internal clock pck tcnt n + 1 n n ? 1 figure 18.4 count timing when operating on internal clock
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 672 of 1286 rej09b0158-0100 ? external clock input pin pck tcnt n + 1 n n ? 1 figure 18.5 count timing when operating on external clock ? rtc output clock tcnt n n + 1 n - 1 figure 18.6 count timing when op erating on on-chip rtc output clock
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 673 of 1286 rej09b0158-0100 18.4.2 input ca pture function channel 2 has an input capture function. the procedure for using the input capture function is as follows: 1. use bits tpsc2 to tpsc0 in tcr to set an internal clock as the timer operating clock. 2. use bits ipce1 and ipce0 in tcr to specify use of the input capture function, and whether interrupts are to be generated when this function is used. 3. use bits ckeg1 and ckeg0 in tcr to specify whether the rising or falling edge of the tclk pin is to be used to set the tcnt value in tcpr2. when input capture occurs, the tcnt2 value is set in tcpr2 only when the icpf bit in tcr2 is 0. a new dmac transfer request is not generated until processing of the previous request is finished. figure 18.7 shows the operation timing when the input capture function is used (with tclk rising edge detection). tcor h'0000 0000 tclk tcpr2 ticpi2 tcnt value tcor value set in tcnt on underflow tcnt value set time figure 18.7 operation timing wh en using input capture function
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 674 of 1286 rej09b0158-0100 18.5 interrupts there are seven tmu interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used . underflow interrupts are generate d on each of the channels, and input capture interrupts on channel 2 only. an underflow interrupt request is generated (for each channel) when both the unf bit and the interrupt enable bit (unie) for that channel are set to 1. when the input capture function is used and an input capture request is generated, an interrupt is requested if the icpf bit in tcr2 is 1 and the input capture control bits (icpe1 and icpe0) in tcr2 are both set to 11. the tmu interrupt sources ar e summarized in table 18.4. table 18.4 tmu interrupt sources channel interrupt source description 0 tuni0 underflow interrupt 0 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 ticpi2 input capture interrupt 2 3 tuni3 underflow interrupt 3 4 tuni4 underflow interrupt 4 5 tuni5 underflow interrupt 5
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 675 of 1286 rej09b0158-0100 18.6 usage notes 18.6.1 register writes when writing to a tmu register, timer count operation must be stopped by clearing the start bit (str5 to str0) for the relevant channel in tstr. note that tstr can be written to, and the unf and icpf bits in tcr can be cleared while the count is in progress. when the flags (unf and icpf) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 18.6.2 reading from tcnt reading from tcnt is performed synchronously with the timer count operation. note that when the timer count operation is performed simult aneously with reading from a register, the synchronous processing causes the tcnt value befo re the count-down operati on to be read as the tcnt value. 18.6.3 reset rtc frequency divider circuit when selecting the output clock of the on-chip rtc for the count clock, reset the rtc frequency divider circuit. 18.6.4 external clock frequency ensure that the external cloc k (tclk) input frequency for chan nels 0, 1 and 2 does not exceed pck/4.
section 18 timer unit (tmu) rev.1.00 dec. 13, 2005 page 676 of 1286 rej09b0158-0100
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 677 of 1286 rej09b0158-0100 section 19 compare match timer (cmt) this lsi includes the 32-bit compare match timer, which has four channels (channel 0 to 3). there are two mode of operation: one is four channels 32-bit free running timer mode that has common 32-bit free running time base and the other is four channels 16-bit timer/counter mode that operates as four channels timer or counter individually. 19.1 features ? ? ? ? ? ?
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 678 of 1286 rej09b0158-0100 figure 19.1 shows a block diagram of the cmt. cmt_ctr0 cmt_ctr1 cmtctl: cmtfrt: cmtirqs: configuration register free-running timer interrupt status register cmtcfg: cmtchnc: cmtchnst: cmtchnt: control register channeln timer/counter (n = 3 to 0) channeln stop time register (n = 1, 0) channeln time register (n = 3 to 0) cmtcfg cmtctl cmtfrt cmtirqs cmtchn cmtchn cmti bus interface cmtchn cmtchn [legend] cmtchn channel 0, 1 mode controller clock controller clock controller clock controller pin controller interrupt detection interrupt detection interrupt controller channel 2, 3 32-bit timer prescaler peripheral bus 32-bit timer to each channel figure 19.1 block diagram of cmt
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 679 of 1286 rej09b0158-0100 19.2 input/output pins table 19.1 shows the cmt pin configuration. table 19.1 pin configuration pin name function i/o description cmt_ctr0 * channel 0 timer/counter input/output i/o cmt_ctr1 * channel 1 timer/counter input/output i/o 32-bit free-running timer or 16-bit timer/counter input capture input, output compare output or external trigger input. note: these pins are multiplexed with the status0 and status1 pins. 19.3 register descriptions table 19.2 shows the cmt register configuration. table 19.3 show s the register states in each processing mode. table 19.2 register configuration ch. register name abbreviation r/w p4 address area 7 address access size sync clock configuration register cmtcfg r/w h'ffe3 0000 h'1fe3 0000 32 pck free-running timer cmtfrt r h'ffe3 0004 h'1fe3 0004 32 pck control register cmtctl r/w h'ffe3 0008 h'1fe3 0008 32 pck common interrupt status register cmtirqs r/w h'ffe3 000c h'1fe3 000c 32 pck channel 0 time register cmtch0t r/w h'ffe3 0010 h'1fe3 0010 32 pck channel 0 stop time register cmtch0st r/w h'ffe3 0020 h'1fe3 0020 32 pck 0 channel 0 timer/counter cmtch0c r/w h'ffe3 0030 h'1fe3 0030 32 pck channel 1 time register cmtch1t r/w h'ffe3 0014 h'1fe3 0014 32 pck channel 1 stop time register cmtch1st r/w h'ffe3 0024 h'1fe3 0024 32 pck 1 channel 1 timer/counter cmtch1c r/w h'ffe3 0034 h'1fe3 0034 32 pck channel 2 time register cmtch2t r/w h'ffe3 0018 h'1fe3 0018 32 pck 2 channel 2 timer/counter cmtch2c r/w h'ffe3 0038 h'1fe3 0038 32 pck channel 3 time register cmtch3t r/w h'ffe3 001c h'1fe3 001c 32 pck 3 channel 3 timer/counter cmtch3c r/w h'ffe3 003c h'1fe3 003c 32 pck
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 680 of 1286 rej09b0158-0100 table 19.3 register states of cmt in each processing mode ch. register name abbreviation power-on reset by preset pin/wdt/ h-udi manual reset by wdt/ multiple exception sleep by sleep instruction module standby configuration register cmtcfg h'0000 0000 h'0000 0000 retained retained free-running timer cmtfrt h'0000 0000 h'0000 0000 retained retained control register cmtctl h'0000 0000 h'0000 0000 retained retained common interrupt status register cmtirqs h'0000 0000 h'0000 0000 retained retained channel 0 time register cmtch0t h'0000 0000 h'0000 0000 retained retained channel 0 stop time register cmtch0st h'0000 0000 h'0000 0000 retained retained 0 channel 0 timer/counter cmtch0c h'0000 0000 h'0000 0000 retained retained channel 1 time register cmtch1t h'0000 0000 h'0000 0000 retained retained channel 1 stop time register cmtch1st h'0000 0000 h'0000 0000 retained retained 1 channel 1 timer/counter cmtch1c h'0000 0000 h'0000 0000 retained retained channel 2 time register cmtch2t h'0000 0000 h'0000 0000 retained retained 2 channel 2 timer/counter cmtch2c h'0000 0000 h'0000 0000 retained retained channel 3 time register cmtch3t h'0000 0000 h'0000 0000 retained retained 3 channel 3 timer/counter cmtch3c h'0000 0000 h'0000 0000 retained retained
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 681 of 1286 rej09b0158-0100 19.3.1 configuration register (cmtcfg) cmtcfg is a 32-bit readable/writable register . the possible operations for a pin are timer compare, timer input capture, up or down count, and capture input, where one pin is used for capture while the second is used to enable the count. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rot0 ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r/w r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 t01 ? ? ? frtm ? ? ed0 ed1 ? ? ?? r/w r/w r r r r/w r r r/w r/w r/w r/w r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 17 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 16 rot0 0 r/w channel 0,1 rotation enable [updown-counter mode (t01 = 11)] 0: counting up by cmt_ctr0 signal, counting down by cmt_ctr1 signal 1: rotary mode operation by cmt_ctr[1:0] signal (then the settings of ed0 and ed1 are invalid) [other than updown-counter mode] clear this bit to 0. 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 682 of 1286 rej09b0158-0100 bit bit name initial value r/w description 11, 10 ed1 all 0 r/w channel 1 pin active control [input capture mode] 00: setting prohibited * 01: edge detection on rising edge of cmt_ctr1 pin input 10: edge detection on falling edge of cmt_ctr1 pin input 11: edge detection on either edge of cmt_ctr1 pin input [output compare mode] 00: setting prohibited * 01: high level is output from cmt_ctr1 pin during active period 10: low level is output from cmt_ctr1 pin during active period 11: setting prohibited * 9, 8 ed0 all 0 r/w channel 0 pin active control [input capture mode] 00: setting prohibited * 01: edge detection on rising edge of cmt_ctr0 pin input 10: edge detection on falling edge of cmt_ctr0 pin input 11: edge detection on either edge of cmt_ctr0 pin input [output compare mode] 00: setting prohibited * 01: high level is output from cmt_ctr0 pin during active period 10: low level is output from cmt_ctr0 pin during active period 11: setting prohibited *
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 683 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 frtm 0 r/w free-running timer mode determines whether the timer works as a common 32- bit free-running timer or four independent 16-bit timers/counters. 0: 16-bit timer/counter mode (channel 0, 1) 16-bit timer mode (channel 2, 3) 1: 32-bit free-running timer (frt) mode when setting to 1, clear the t01 bit to 00. 4 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1, 0 t01 all 0 r/w ti mer 0,1 configuration specifies the channel 0 and channel 1 operation mode. clear to 00 in 32-bit fr ee-running timer mode (frtm = 1). 00: timers 0 and 1 01: up-counter 0 and timer 1 10: up-counters 0 and 1 11: updown-counter 0 note: * when these channels be used, be sure to set up values other than setting prohibited.
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 684 of 1286 rej09b0158-0100 19.3.2 free-running timer (cmtfrt) cmtfrt is a 32-bit read only register that is the common time base of the capture/compare register (channel 0, 1) and compare register (channel 2, 3) in 32-bit free-running timer (frt) mode. sh r/w: sh r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r r r r r r r r r r r r r r r r frt r r r r r r r r r r r r r r r r frt 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 bit bit name initial value r/w description 31 to 0 frt all 0 r free-running timer these bits indicate the current value of the free-running timer (frt). 19.3.3 control register (cmtctl) cmtctl is a 32-bit readable/writable register that controls interrupts, makes settings for the clocks, and selects the operating mode. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 iee0 iee1 ? ? ice0 ice1 ice2 ice3 ioe0 ioe1 ioe2 ioe3 te0 te1 te3 te2 r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 op0 op1 op2 op3 sl0 sl1 ? ? cc0 cc1 cc2 cc3 r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 685 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 30 29 28 te3 te2 te1 te0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 timer enable enables the counting of each of the 16-bit counters. if these bits are inactive when operating in timer mode or in counter mode, the counters are reset to 0. in updown-counter mode, channel 1 needs to be disabled (te1 = 0). 0: counting disabled; counter will be reset to h'0000 1: counter is incremented n = 3 to 0 27 26 25 24 ioe3 ioe2 ioe1 ioe0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 interrupt overflow enable these bits enable an interrupt to be generated when the relevant ion bit is set in cmtirqs register. 0: interrupt generation disabled 1: interrupt generation enabled n = 3 to 0 23 22 21 20 ice3 ice2 ice1 ice0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 interrupt compare enable these bits enable an interrupt to be generated when the relevant icn bit is set in the cmtirqs register. 0: interrupt generation disabled 1: interrupt generation enabled n = 3 to 0 19 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 iee1 iee0 0 0 r/w r/w channel 1 to 0 interrupt edge enable these bits enable an interrupt to be generated when the relevant ien bit is set in cmtirqs register. 0: interrupt generation disabled 1: interrupt generation enabled when a channel is in output compare mode, the corresponding ieen has to be set to 0. n = 1, 0
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 686 of 1286 rej09b0158-0100 bit bit name initial value r/w description 15, 14 cc3 all 0 r/w timer clock control channel 3 these bits specify the clock input for the 16-bit timer in channel 3. * 00: clock for timer 3 is 1/32 of peripheral clock (pck) 01: clock for timer 3 is 1/128 of peripheral clock (pck) 10: clock for timer 3 is 1/512 of peripheral clock (pck) 11: clock for timer 3 is 1/1024 of peripheral clock (pck) the clock which divided from the peripheral clock (pck) is the timer/counter resolution. 13, 12 cc2 all 0 r/w timer clock control channel 2 these bits specify the clock input for the 16-bit timer in channel 2. * 00: clock for timer 2 is 1/32 of peripheral clock (pck) 01: clock for timer 2 is 1/128 of peripheral clock (pck) 10: clock for timer 2 is 1/512 of peripheral clock (pck) 11: clock for timer 2 is 1/1024 of peripheral clock (pck) the clock which divided from the peripheral clock (pck) is the timer/counter resolution. 11, 10 cc1 all 0 r/w timer clock control channel 1 these bits specify the clock input for the 16-bit timer/counter in channel 1. * 00: clock for timer 1 is 1/32 of peripheral clock (pck) 01: clock for timer 1 is 1/128 of peripheral clock (pck) 10: clock for timer 1 is 1/512 of peripheral clock (pck) 11: clock for timer 1 is 1/1024 of peripheral clock (pck) set the same value as the cc0 bit when using 16-bit input capture mode. set the same value as the cc0 bit when using 16-bit input capture mode. the clock which divided from the peripheral clock (pck) is the timer/counter resolution.
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 687 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9, 8 cc0 all 0 r/w free-running timer clock control this clock is used for the 32-bit free-running timer (frt) and also for the 16-bit timer/counter in channel 0. * 00: clock for frt and timer 0 is 1/32 of peripheral clock (pck) 01: clock for frt and timer 0 is 1/128 of peripheral clock (pck) 10: clock for frt and timer 0 is 1/512 of peripheral clock (pck) 11: clock for frt and timer 0 is 1/1024 of peripheral clock (pck) the clock which divided from the peripheral clock (pck) is the timer/counter resolution. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 si1 si0 0 0 r/w r/w channel 1 to 0 stop ignore for the channel n, these bits determine whether in output compare mode with 32-bit free-running timer mode, the output remains active for half the maximum time or until the stop value is reached. 0: output remains active until the channel n stop time value is reached 1: output remains active for ha lf the total time of the frt n = 0, 1 3 2 1 0 op3 op2 op1 op0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 operation for the channel n, if in timer mode, these bits determine whether the timer is used in output compare or input capture mode. set 1 to the corresponding bit when using channel 2 or 3 as the timer. 0: input capture mode (can be set in channel 0, 1) 1: output compare mode when a channel is in output compare mode, the corresponding ieen bits has to be set to 0. n = 3 to 0 note: * the source clock is the peripheral clock (pck ). the clock which divided from the source clock is the timer/counter resolution of the channel.
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 688 of 1286 rej09b0158-0100 19.3.4 interrupt stat us register (cmtirqs) cmtirqs, once set, can only be cleared by a write . writing 0 to these bi ts clears the interrupt status bits. these conditions only create an interrupt if the relevant interrupt enable bit is set. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ie0 ie1 ? ? ic0 ic1 ic2 ic3 io0 io1 io2 io3 ? ? ?? r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 io3 io2 io1 io0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 interrupt overflow a bit for each channel indicates if the up-counters or updown-counters have wrapped i.e. overflowed from h'ffff to h'0000 or underflowed from h'0000 to h'ffff. 0: the counter is not overflowed or underflowed 1: the counter is overflowed or underflowed 7 6 5 4 ic3 ic2 ic1 ic0 0 0 0 0 r/w r/w r/w r/w channel 3 to 0 interrupt compare a bit for each channel indicates whether in timer mode, the free-running timer has become equal to the channel times. 0: timer has not become equal to the channel time value 1: timer has become equal to the channel time value 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 ie1 ie0 0 0 r/w r/w channel 1 to 0 interrupt edge a bit for each channel indicates whether an edge that will cause an action (active edge) has been defected. 0: channel 1 to 0 has not received an active edge 1: channel 1 to 0 has received an active edge
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 689 of 1286 rej09b0158-0100 19.3.5 channels 0 to 3 time registers (cmtch0t to cmtch3t) in output compare mode, these re gisters specify the value to be compared with the free-running timer. in input capture mode, this register stores the free-running timer values or the 16-bit timer values on the active edge of the input. every time an edge is det ected, these registers are updated and the new captured value will be saved. sh r/w: sh r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w channel n time r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: n = 3 to 0 r/w channel n time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 19.3.6 channels 0 to 1 stop time registers (cmtch0st to cmtch1st) in output compare mode, these re gisters specify the value to be compared with the free-running timer. when clearing the stcn bit in cmtctl, th e output state that specifies by cmtcfg is inverted when cmtfrt value is reached to the setting value of cmtchnt. sh r/w: sh r/w: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 bit: initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w channel n stop time r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: n = 1 to 0 r/w channel n stop time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 bit: initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 690 of 1286 rej09b0158-0100 19.3.7 channels 0 to 3 counters (cmtch0c to cmtch3c) each channel register indicates the current value of the timer/counter. writing to this register, it can be set the timer counter. when reading this register, the timer/counter value is not affected. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 channel n counter 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 691 of 1286 rej09b0158-0100 19.4 operation the cmt has two operation modes: one is four cha nnels free-running timer th at operates with the common time base of 32-bit free-running timer operating between approximately 1.5mhz (pck/32 selected at pck = 50mhz) to 30khz (pck/1024 se lected at pck = 33mhz). the other is 16-bit timer/counter that operating as two channels 16-bit timer/counter and two channels 16-bit timer. when operating as the timer, it can be selectable input capture or output compare. they differ from the free-running timer mode that they ar e initialized to h'0000 when capture input or compare match occurs on that channel. 19.4.1 edge detection the timers and counters are based on edge detec tion on the input pins. an active edge can be selectable by setting cmtcfg to be a rising edge, falling edge, or both edges. in addition, the edge detection logic can operate in rotary switch operation where the combination of two inputs indicates whether the switch has been turned righ t or left and the updown counter is incremented or decremented. the edge detection input can either work independently for the timers or the up- counters or can work as pairs to indicate up and down to the updown-counters. in order for an edge to be detected, the input pulse to the cmt_ctr pin must last for at least two cycles of the clock divided from the peripheral clock (pck) for that channel, as shown in figure 19.2. pck input pulse edge detection the clock divided from pck figure 19.2 edge detection (example of rising edge)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 692 of 1286 rej09b0158-0100 19.4.2 32-bit tim er: input capture when rising edge or falling edge is detected wh ile the timer cmtfrt is operating, the value of cmtfrt is captured in the corresponding cmtchn t (n = 1, 0). then the ien flag in cmtirqs is set to 1 and the interrupt is generated when the ieen bit in cmtctl is set to 1. cmt_ctrn cmti peripheral bus common between channels edge detection edge control channel time register 32-bit free-running timer clock generation multiplexer figure 19.3 32-bit timer mode: in put capture (channel 1 and channel 0) pck frt operation clock cmtfrt cmt_ctrn input cmtchnt ien flag n n n ? 1 n + 1 figure 19.4 32-bit timer mode: input capture operation timing
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 693 of 1286 rej09b0158-0100 table 19.4 32-bit timer mode: ex ample of input capture setting register bit settings cmtcfg 31 t o 12 all 0 11 to 8 arbitrary value (pin setting of each channel) 7, 6 all 0 5 1 (32-bit free-running timer) 4 to 0 all 0 cmtctl 31 to 18 all 0 17, 16 arbitrary value (edge interrupt setting of each channel) 15 t o 10 all 0 9, 8 arbitrary value (clock setting of frt) 7 to 2 all 0 1, 0 all 0 (input capture mode setting of all channels) 19.4.3 32-bit timer: output compare when the value of the cmtfrt matches value of cmtchnt plus 1 while the timer cmtfrt is operating, the cmt_ctr output state becomes equal to the setting of the ed1 and ed0 bits in cmtcfg. then the icn flag in cmtirqs is set to 1 and the interrupt is generated when the icen bit in cmtctlis set to 1. the cmt_ctr output is being asserted until the value of cmtfrt matches cmtchnt plus 1 or cmtchnt plus h'8000 0001 while the timer cmtfrt is operating. the cmt_ctr pin can be set to not active state by setting the stcn bit in cmtctl. note that channels 2 and 3 do not have the output pin, use as the interval timer to generate an interrupt with regular period.
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 694 of 1286 rej09b0158-0100 cmtchnst cmtchnt h'ffff ffff cmtfrt value time cmtchnst + h'8000 0000 h'0000 0000 start count-up frtm bit cmt_ctrn output icn flag stcn bit output remains active until the channel n stop time value is reached output remains active for half the total time of the frt figure 19.5 cmt_ctrn assert timing (channel 0 and 1) cmt_ctrn 32-bit frt = channel time cmti common between channels 32-bit free-running timer clock generation channel time register figure 19.6 32-bit timer mode: outp ut compare (channel 1 and channel 0)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 695 of 1286 rej09b0158-0100 pck frt operation clock cmtfrt cmt_ctrn output cmtchnt cmtchnst icn flag nn + 1 n + 1 n + 2 n figure 19.7 32-bit timer mode: output compare operation timing (example of high output in active and not active by cmtchnst) pck cmtfrt cmtchnt n frt operation clock cmt_ctrn output n + h'8000 0000 n + h'8000 0001 figure 19.8 32-bit timer mode: output compare operation timing (example of high output in active and not active by cmtfrt)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 696 of 1286 rej09b0158-0100 table 19.5 32-bit timer mode: example of output compare setting register bit settings cmtcfg 31 t o 12 all 0 11 to 8 arbitrary value (pin setting of each channel) 7, 6 all 0 5 1 (32-bit free-running timer) 4 to 0 all 0 cmtctl 31 to 24 all 0 23 to 20 arbitrary value (compare interrupt setting of each channel) 19 t o 10 all 0 9, 8 arbitrary value (clock setting of frt) 7, 6 all 0 5, 4 arbitrary value (activ e state setting of each channel) 3 to 0 all 1 (out put compare mode setting of all channels)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 697 of 1286 rej09b0158-0100 19.4.4 16-bit tim er: input capture when rising edge or falling edge is detected while the timer cmtch0c is operating, the value of cmtchnc (n = 0, 1) is captured in the correspo nding cmtchnt (n = 1, 0). then the ien flag in cmtirqs is set to 1 and the interrupt is generated when the ieen bit in cmtctl is set to 1. each channel timer overflowed after the timer is counting up at h'ffff that is the value of cmtchnc (n = 1, 0). then the ion flag in cmtirqs is set to 1 and the interrupt is generated when the ioen bit in cmtctl is set to 1. the 16-bit timer cmtchnc (n = 1, 0) is initialized to h'0000 when the ten (n = 1, 0) bit in cmtcl is cleared to 0 or an input capture occurs. cmt_ctrn cmti common between channels edge detection edge control channel time register 16-bit counter clock generation figure 19.9 16-bit timer mode: in put capture (channel 1 and channel 0)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 698 of 1286 rej09b0158-0100 pck cmtchnt h'0000 n n cmtch0t operation clock cmtchnc cmt_ctrn input ien flag n + 1 n ? 1 figure19.10 16-bit timer mode : input capture operation timing table 19.6 16-bit timer mode: ex ample of input capture setting register bit settings cmtcfg 31 t o 12 all 0 11 to 8 arbitrary value (pin setting of each channel) 7, 6 all 0 5 0 (16-bit timer/counter) 4 to 0 all 0 (16-bit timer mode setting of all channels) cmtctl 31, 30 all 0 29, 28 all 1 (counter enable of all channels) 27, 26 all 0 25, 24 arbitrary value (overflow interrupt setting of each channel) 23 to 18 all 0 17, 16 arbitrary value (edge interrupt setting of each channel) 15 t o 10 same clock setting with channel 0 9, 8 arbitrary value (clock setting of channel 0) 7 to 2 all 0 1, 0 all 0 (input capture mode setting of all channels)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 699 of 1286 rej09b0158-0100 19.4.5 16-bit timer: output compare when the value of cmtchnc (n = 1, 0) matches the lower 16-bit of cmtchnt while the timer cmtch0c is operating, the output is inverted. then the icn flag in cmtirqs is set to 1 and the interrupt is generated when the icen bit in cmtctl is set to 1. however, when the lower 16-bit of time register cmtchnt is h'0000, the compare match does not occur. each channel timer overflowed after the timer is counting up at h'ffff that is the value of cmtchnc (n = 3 to 0). then the ion flag in cmtirqs is set to 1 and the interrupt is generated when the ioen bit in cmtctl is set to 1. the 16-bit timer cmtchnc (n = 3 to 0) is initialized to h'0000 when the ten (n = 1, 0) bit in cmtcl is cleared to 0 or a compare match occurs. note that channels 2 and 3 do not have the output pin, use as the interval timer to generate an interrupt with regular period. cmti cmt_ctrn 16-bit counter = channel time clock generation 16-bit counter channel time register figure 19.11 16-bit ti mer mode: output compare (cmt_ctr pins are available for channel 1 and channel 0)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 700 of 1286 rej09b0158-0100 pck cmtchnc cmtchnt h'0000 n n cmtchnc operation clock cmt_ctrn output icn flag n ? 1n + 1 figure19.12 16-bit timer mode: output compare op eration timing table 19.7 16-bit timer mode: example of output compare setting register bit settings cmtcfg 31 t o 16 all 0 15 to 8 all 0 7, 6 all 0 5 0 (16-bit timer/counter) 4 to 0 all 0 (16-bit timer mode setting of all channels) cmtctl 31 to 28 all 1 (counter enable of all channels) 27 to 24 arbitrary value (overflow interrupt setting of each channel) 23 to 20 arbitrary value (compare interrupt setting of each channel) 19 to 16 all 0 15 to 8 arbitrary value (clock setting of each channel) 7 to 4 all 0 3 to 0 all 1 (out put compare mode setting of all channels)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 701 of 1286 rej09b0158-0100 19.4.6 counter: up-counter when rising edge or falling edge of the cmt_ctr input signal is detected at the rising edge of each channel operation clock, the channel co unter cmtchnc value is captured in the corresponding cmtchnt (n = 1, 0) and that counter is counted up. then the ien flag in cmtirqs is set to 1 and the interrupt is generated when the ieen bit in cmtctl is set to 1. and each channel counter overflowed, the ion flag in cmtirqs is set to 1 and the interrupt is generated when the ioen bit in cmtctl is set to 1. the counter cmtchnc (n = 1, 0) is initialized to h'0000 when the ten (n = 1, 0) bit in cmtcl is cleared to 0 or an input capture occurs. cmti cmt_ctrn edge detection up-counter figure 19.13 up-counter mode (channel 1 and channel 0) pck cmtchnc cmtchnt n n cmtchnt operation clock cmt_ctrn input ien flag n + 1 figure 19.14 up-counter mode operation timing
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 702 of 1286 rej09b0158-0100 table 19.8 setting example of up-counter mode register bit settings cmtcfg 31 t o 12 all 0 11 to 8 arbitrary value (pin setting of each channel) 7, 6 all 0 5 0 (16-bit timer/counter) 4 to 2 all 0 1, 0 10 (up-counter mode setting of all channels) cmtctl 31, 30 all 0 29, 28 all 1 (counter enable of all channels) 27, 26 all 0 25, 24 arbitrary value (overflow interrupt setting of each channel) 23 t o 18 all 0 17, 16 arbitrary value (edge interrupt setting of each channel) 15 to 12 all 0 11 to 8 arbitrary value (clock setting of each channel) 7 to 0 all 0
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 703 of 1286 rej09b0158-0100 19.4.7 counter: updown-counter channel 0 can be used as an updown-counter. however, the cmt_crt1 pin is to connect to the channel 0, the channel 1 timer/counter needs to be disabled. when rising edge or falling edge of the cmt_ctr input signal is detected at the rising edge of the channel 0 operation clock, the channel count er cmtch0c is counted up or down. then the ien flag in cmtirqs is set to 1 and the interrupt is generated when the ieen bit in cmtctl is set to 1. if both the count up pin (cmt_ctr0) and count down pin (cmt_ctr1) detect rising edge or falling edge, the counter value is not updated but the ien bit in cmtirqs is set to 1. and the counter cmtch0c overflowed or underflowed, the io0 flag in cmtirqs is set to 1 and the interrupt is generated when the ioe0 bit in cmtctl is set to 1. the counter cmtch0c is initialized to h?0000 when the te0 bit in cmtcl is cleared to 0. cmti cmti edge detection updown-counter up down edge detection cmt_ctr0 cmt_ctr1 figure 19.15 updown-count er mode (only channel 0) pck cmtch0c n cmtch0t operation clock cmt_ctr1 input cmt_ctr0 input edge interrupt flag n ? 1 figure 19.16 updown-count er mode: countdown operation timing (only channel 0)
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 704 of 1286 rej09b0158-0100 table 19.9 setting exampl e of updown-counter mode register bit settings cmtcfg 31 t o 12 all 0 11 to 8 arbitrary value (pin setting of each channel) 7, 6 all 0 5 0 (16-bit timer/counter) 4 to 2 all 0 1, 0 11 (updown-counter mode setting of channel 0) cmtctl 31 to 29 all 0 28 1 (counter enable of channel 0) 27 to 25 all 0 24 arbitrary value (overflow interrupt setting of channel 0) 23 t o 18 all 0 17, 16 arbitrary value (edge interrupt setting of each channel) 15 to 10 all 0 9, 8 arbitrary value (clock setting of channel 0) 7 to 0 all 0
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 705 of 1286 rej09b0158-0100 19.4.8 counter: rotary switch operation of updown-counter the updown-counter can oper ate as a rotary switch. when the falling edge of the control pin is detected and then the data pin input level is low, the counter is counted up, or the data pin input level is high, the counter is counted down. then the timer is counted up, the ie0 flag in cmtirqs is set to 1, or the timer is counted down, the ie1 flag in cmtirqs is set to 1 and the interrupt is generated when the ieen bit in cmtctl is set to 1. if both the count up and count down are detected, both the ie0 and the ie1 flags are set to 1 and the counter cmtc h0c is updated by the most recently detected edge. pck cmtch0c n cmtch0t operation clock cmt_ctr1 input cmt_ctr0 input channel 0 edge interrupt flag n + 1 figure 19.17 rotary switch operation count-up timing pck cmtch0c n cmtch0t operation clock cmt_ctr1 input cmt_ctr0 input channel 1 edge interrupt flag n ? 1 figure 19.18 rotary switch operation count-down timing
section 19 compare match timer (cmt) rev.1.00 dec. 13, 2005 page 706 of 1286 rej09b0158-0100 table 19.10 setting example of updown-counter mode register bit settings cmtcfg 31 t o 17 all 0 16 all 1 (rotary switch operation setting of channel 0) 15 to 6 all 0 5 0 (16-bit timer/counter) 4 to 2 all 0 1, 0 11 (updown-counter mode setting of channel 0) cmtctl 31 to 29 all 0 28 1 (counter enable of channel 0) 27 to 25 all 0 24 arbitrary value (overflow interrupt setting of channel 0) 23 t o 18 all 0 17, 16 arbitrary value (edge interrupt setting of each channel) 15 to 10 all 0 9, 8 arbitrary value (clock setting of channel 0) 7 to 0 all 0 19.4.9 interrupts the cmt has three interrupt sources: the ove rflow, compare and edge. however, only one interrupt request is assigned for the cmt, it cannot be identified by the request. table 19.11 cmt interrupt setting interrupt source operation mode overflow compare edge 32-bit timer input capture not available not available available output compare not available available not available 16-bit timer input capture available not available available output compare available available not available counter up-counter available not available available updown-counter available not available available
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 707 of 1286 rej09b0158-0100 section 20 realtime clock (rtc) the sh7780 includes an on-chip realtime clock (rtc ) and a 32.768 khz crystal oscillator for use by the rtc. 20.1 features the rtc has the following features. ? ? ? ? ? ? ? ?
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 708 of 1286 rej09b0158-0100 20.1.1 block diagram figure 20.1 shows a block diagram of the rtc. r64cnt 16.384 khz 32.768 khz 128 hz at extal2 xtal2 i pri cui rcr1 rcr2 rcr3 ryrcnt ryrar rmoncnt rwkcnt rdaycnt rhrcnt rmincnt rseccnt rsecar rminar rhrar rdayar rwkar rmonar prescaler rtc crystal oscillator rtc operation control unit counter unit interrupt control unit to registers bus interface peripheral bus rtcclk figure 20.1 block diagram of rtc
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 709 of 1286 rej09b0158-0100 20.2 input/output pins table 20.1 shows the rtc pins. table 20.1 rtc pins pin name function i/o description extal2 rtc oscillator cryst al pin input connects crystal to rtc oscillator xtal2 rtc oscillator crystal pin output connects crystal to rtc oscillator tclk * 1 tmu clock input/rtc clock output i/o tmu external clock input pin/input capture control input pin/rt c output pin (shared with tmu) vdd-rtc dedicated rtc power supply ? rtc oscillator power supply pin * 2 vss-rtc dedicated rtc gnd pin ? rtc oscillator gnd pin * 2 notes: 1. this pin is multiplexed with the lbsc and gpio pins. 2. power must be supplied to the rtc power supply pins even when the rtc is not used.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 710 of 1286 rej09b0158-0100 20.3 register descriptions table 20.2 shows the rtc registers. table 20.3 shows the register states in each processing mode. table 20.2 rtc registers register name abbreviation r/w p4 address area 7 address access size sync clock 64 hz counter r64cnt r h'ffe80000 h'1fe80000 8 pck second counter rseccnt r/w h'ffe80004 h'1fe80004 8 pck minute counter rmincnt r/w h'ffe80008 h'1fe80008 8 pck hour counter rhrcnt r/w h'ffe8000c h'1fe8000c 8 pck day-of-week counter rwkcnt r/w h'ffe80010 h'1fe80010 8 pck day counter rdaycnt r/w h'ffe80014 h'1fe80014 8 pck month counter rmoncnt r/w h'ffe80018 h'1fe80018 8 pck year counter ryrcnt r/w h'ffe8001c h'1fe8001c 16 pck second alarm register rsecar r/w h'ffe80020 h'1fe80020 8 pck minute alarm register rmin ar r/w h'ffe80024 h'1fe80024 8 pck hour alarm register rhra r r/w h'ffe80028 h'1fe80028 8 pck day-of-week alarm register rw kar r/w h'ffe8002c h'1fe8002c 8 pck day alarm register rdayar r/w h'ffe80030 h'1fe80030 8 pck month alarm register rmon ar r/w h'ffe80034 h'1fe80034 8 pck rtc control register 1 rcr1 r/w h'ffe80038 h'1fe80038 8 pck rtc control register 2 rcr2 r/w h'ffe8003c h'1fe8003c 8 pck rtc control register 3 rcr3 r/w h'ffe80050 h'1fe80050 8 pck year alarm register ryra r r/w h'ffe80054 h'1fe80054 16 pck
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 711 of 1286 rej09b0158-0100 table 20.3 register states of rtc in each processing mode register name abbreviation initial value power-on reset manual reset sleep 64 hz counter r64cnt undefined counts counts counts second counter rseccnt undefined counts counts counts minute counter rmincnt undef ined counts counts counts hour counter rhrcnt undefin ed counts counts counts day-of-week counter rwkcnt undefined counts counts counts day counter rdaycnt undefined counts counts counts month counter rmoncnt undef ined counts counts counts year counter ryrcnt undefined counts counts counts second alarm register rsecar undefined * 1 initialized * 1 retained retained minute alarm register rminar undefined * 1 initialized * 1 retained retained hour alarm register rhrar undefined * 1 initialized * 1 retained retained day-of-week alarm register rwkar undefined * 1 initialized * 1 retained retained day alarm register rdayar undefined * 1 initialized * 1 retained retained month alarm register rmonar undefined * 1 initialized * 1 retained retained rtc control register 1 rcr1 h'00 * 3 initialized initialized retained rtc control register 2 rcr2 h'09 * 4 initialized initialized * 2 retained rtc control register 3 rcr3 h' 00 initialized retained retained year alarm register ryrar undefined retained retained retained notes: 1. the enb bit in eac h register is initialized. 2. bits other than the rtcen bit and start bit are initialized. 3. the value of the cf bit and af bit is undefined. 4. the value of t he pef bit is undefined.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 712 of 1286 rej09b0158-0100 20.3.1 64 hz counter (r64cnt) r64cnt is an 8-bit read-only register that indi cates a state of 64 hz to 1 hz within the rtc frequency divider. if this register is read when a carry is generated from the 128 hz frequency division stage, bit 7 (cf) in rtc control register 1 (rcr1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 hz counter read. in this case, the read value is not valid, and so r64cnt must be read again after first writing 0 to the cf bit in rcr1 to clear it. when the reset bit or adj bit in rtc control re gister 2 (rcr2) is set to 1, the rtc frequency divider is initialized and r64cnt is initialized to h'00. r64cnt is not initialized by a power-on or manual reset. bit 7 is always read as 0 and cannot be modified. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? 0 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz ? r r r r r r r r bit: initial value: r/w: 20.3.2 second counter (rseccnt) rseccnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded second value in the rtc. it counts on the carry (transition of the r64cnt.1hz bit from 1 to 0) generated once per second by the 64 hz counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rseccnt is not initialized by a power-on or manual reset. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? 0 1-second units 10-second units ? r/w r/w r/w r/w r/w r/w r/w r bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 713 of 1286 rej09b0158-0100 20.3.3 minute counter (rmincnt) rmincnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded minute value in the rtc. it counts on the carry generated once per minute by the second counter. the setting range is decimal 00 to 59. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmincnt is not initialized by a power-on or manual reset. bit 7 is always read as 0. a write to this bit is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? 0 1-minute units 10-minute units ? r/w r/w r/w r/w r/w r/w r/w r bit: initial value: r/w: 20.3.4 hour counter (rhrcnt) rhrcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded hour value in the rtc. it counts on the carry generated once per hour by the minute counter. the setting range is decimal 00 to 23. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rhrcnt is not initialized by a power-on or manual reset. bits 7 and 6 are always read as 0. a write to thes e bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? 0 ? 0 1-hour units 10-hour units ? r/w r/w r/w r/w r/w r/w r r bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 714 of 1286 rej09b0158-0100 20.3.5 day-of-week counter (rwkcnt) rwkcnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day-of-week value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 0 to 6. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rwkcnt is not initialized by a power-on or manual reset. bits 7 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? 0 0 0 0 0 day-of-week code ? ? ? ? ? r/w r/w r/w r r r r r bit: initial value: r/w: day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 715 of 1286 rej09b0158-0100 20.3.6 day counter (rdaycnt) rdaycnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded day value in the rtc. it counts on the carry generated once per day by the hour counter. the setting range is decimal 01 to 31. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rdaycnt is not initialized by a power-on or manual reset. the setting range for rdaycnt depends on the month and whether the year is a leap year, so care is required when making th e setting. taking the year counter (ryrcnt) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. bits 7 and 6 are always read as 0. a write to these bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? 0 0 1-day units 10-day units ? ? r/w r/w r/w r/w r/w r/w r r bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 716 of 1286 rej09b0158-0100 20.3.7 month counter (rmoncnt) rmoncnt is an 8-bit readable/writable register used as a counter for setting and counting the bcd-coded month value in the rtc. it counts on the carry generated once per month by the day counter. the setting range is decimal 01 to 12. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. rmoncnt is not initialized by a power-on or manual reset. bits 7 to 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? 0 10-month unit ? 0 0 1-month units ? ? r/w r/w r/w r/w r/w r r r bit: initial value: r/w: 20.3.8 year counter (ryrcnt) ryrcnt is a 16-bit readable/writable register us ed as a counter for setting and counting the bcd-coded year value in the rtc. it counts on the carry generated once per year by the month counter. the setting range is decimal 0000 to 9999. the rtc will not operate normally if any other value is set. write processing should be performed after stopping the count with the start bit in rcr2, or by using the carry flag. ryrcnt is not initialized by a power-on or manual reset. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? 1-year units 10-year units 100-year units 1000-year units r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 717 of 1286 rej09b0158-0100 20.3.9 second alarm register (rsecar) rsecar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded second value counter, rseccnt. when the enb b it is set to 1, the rsecar value is compared with the rseccnt value. comparison between th e counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operat e normally if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the other fields in rsecar are not initialized by a power-on or manual reset. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? 0 1-second units 10-second units enb r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 20.3.10 minute alarm register (rminar) rminar is an 8-bit readable/writable register us ed as an alarm register for the rtc's bcd-coded minute value counter, rmincnt. when the enb bit is set to 1, the rminar value is compared with the rmincnt value. comparison between th e counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the respective values all match. the setting range is decimal 00 to 59 + enb bit. the rtc will not operat e normally if any other value is set. the enb bit in rminar is initialized by a power-on reset. the other fields in rminar are not initialized by a power-on or manual reset. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? 0 1-minute units 10-minute units enb r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 718 of 1286 rej09b0158-0100 20.3.11 hour alarm register (rhrar) rhrar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded hour value counter, rhrcnt. when the enb bit is set to 1, the rhrar value is compared with the rhrcnt value. comparison between the coun ter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm fl ag is set when the resp ective values all match. the setting range is decimal 00 to 23 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rhrar is initialized by a power-on reset. the other fields in rhrar are not initialized by a power-on or manual reset. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? 0 ? 0 1-hour units 10-hour units enb r/w r/w r/w r/w r/w r/w r r/w bit: initial value: r/w: 20.3.12 day-of-week alarm register (rwkar) rwkar is an 8-bit readable/writable register used as an alarm register for the rtc's bcd-coded day-of-week value counter, rwkcnt. when the enb bit is set to 1, the rwkar value is compared with the rwkcnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 0 to 6 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the other fields in rwkar are not initialized by a power-on or manual reset.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 719 of 1286 rej09b0158-0100 bits 6 to 3 are always read as 0. a write to these bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? 0 0 0 0 0 day-of-week code ? ? ? ? enb r/w r/w r/w r r r r r/w bit: initial value: r/w: day-of-week code 0 1 2 3 4 5 6 day of week sun mon tue wed thu fri sat 20.3.13 day alarm register (rdayar) rdayar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded day value counter, rdaycnt. when the enb bit is set to 1, the rdayar value is compared with the rday cnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 31 + enb bit. the rtc will not operat e normally if any other value is set. the setting range for rdayar depend s on the month and whether the year is a leap year, so care is required when making the setting. the enb bit in rdayar is initialized by a power-on reset. the other fields in rdayar are not initialized by a power-on or manual reset. bit 6 is always read as 0. a write to this bit is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? 0 0 1-day units 10-day units ? enb r/w r/w r/w r/w r/w r/w r r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 720 of 1286 rej09b0158-0100 20.3.14 month alarm register (rmonar) rmonar is an 8-bit readable/writable register used as an alarm regi ster for the rtc's bcd- coded month value counter, rmoncnt. when the enb bit is set to 1, the rmonar value is compared with the rmon cnt value. comparison between the counter and the alarm register is performed for those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1, and the rcr1 alarm flag is set when the respective values all match. the setting range is decimal 01 to 12 + enb bit. the rtc will not operate normally if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the other fields in rmonar are not initialized by a power-on or manual reset. bits 6 and 5 are always read as 0. a write to these bits is invalid, but the write value should always be 0. 0 1 2 3 4 5 6 7 ? ? ? ? ? 0 10-month unit ? 0 0 1-month units ? enb r/w r/w r/w r/w r/w r r r/w bit: initial value: r/w: 20.3.15 year-alarm register (ryrar) ryrar is the alarm register for the rtc's bcd -coded year-value counter ryrcnt. when the yenb bit of rcr3 is set to 1, the ryrcnt value is compared with the ryrar value. comparison between the counter an d the alarm register only take s place with the alarm registers (rsecar, rminar, rhrar, rwkar, rdaya r and rmonar) in which the enb and yenb bits are set to 1. the alarm flag of rcr1 is only set to 1 when the respective values all match. the setting range of ryrar is decimal 0000 to 999 9, and normal operation is not obtained if a value beyond this range is set here. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? 1 year 10 years 100 years 1000 years r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 721 of 1286 rej09b0158-0100 20.3.16 rtc control register 1 (rcr1) rcr1 is an 8-bit readable/writable register contai ning a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. the cie and aie bits are initialized to 0 by a power-on or manual reset; the value of bits other than cie and aie is undefined. 0 1 2 3 4 5 6 7 ? ? ? 0 0 ? ? ? af crf ? aie cie ? ? cf r/w r r r/w r/w r r r/w bit: initial value: r/w: bit bit name initial value r/w description 7 cf undefined r/w carry flag this flag is set to 1 on generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read. the count register value read at this time is not guaranteed, and so the count register must be read again. 0: no second counter carry, or 64 hz counter carry when 64 hz counter is read [clearing condition] when 0 is written to cf 1: second counter carry, or 64 hz counter carry when 64 hz counter is read [setting conditions] generation of a second counter carry, or a 64 hz counter carry when the 64 hz counter is read when 1 is written to cf 6 to 5 ? undefined r reserved the initial value of these bi ts is undefined. a write to these bits is invalid, but the write value should always be 0.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 722 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 cie 0 r/w carry interrupt enable flag enables or disables interrupt generation when the carry flag (cf) is set to 1. 0: carry interrupt is not generated when cf flag is set to 1 1: carry interrupt is generated when cf flag is set to 1 3 aie 0 r/w alarm interrupt enable flag enables or disables interrupt generation when the alarm flag (af) is set to 1. 0: alarm interrupt is not generated when af flag is set to 1 1: alarm interrupt is generated when af flag is set to 1 2 ? undefined r reserved the initial value of these bi ts is undefined. a write to these bits is invalid, but the write value should always be 0. 1 crf undefined r carry ready flag indicates whether or not rseccnt (second counter) is in the state of the carry ready period. this flag is set to 1 when the second counter value is to be incremented after the 1 hz bit in r64cnt (64 hz counter) has changed from 1 to 0. however, writing to this bit is invalid, the write value should always be 0. 0: not carry ready period [clearing condition] when rseccnt is not in carry ready period 1: carry ready period [setting condition] when rseccnt is in carry ready period
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 723 of 1286 rej09b0158-0100 bit bit name initial value r/w description 0 af undefined r/w alarm flag set to 1 when the alarm time set in those registers among rsecar, rminar, rhrar, rwkar, rdayar, and rmonar in which the enb bit is set to 1 matches the respective counter values 0: alarm registers and counter values do not match (initial value) [clearing condition] when 0 is written to af 1: alarm registers and counter values match * [setting condition] when alarm registers in which the enb bit is set to 1 and counter values match * note: * writing 1 does not change the value. 20.3.17 rtc control register 2 (rcr2) rcr2 is an 8-bit readable/writable register us ed for periodic interrupt control, 30-second adjustment, and frequency divider reset and rtc count control. rcr2 is basically initialized to h'09 by a power-on reset, except that the value of the pef bit is undefined. in a manual reset, bits other than rtcen and start are initialized, while the value of the pef bit is undefined. in standby mode rcr2 is not initialized, and retains its current value. 0 1 2 3 4 5 6 7 1 0 0 1 0 0 0 ? start reset adj rtcen pes[2:0] pef r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 724 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 pef undefined r/w periodic interrupt flag indicates interrupt generation at the interval specified by bits pes2?pes0. when this flag is set to 1, a periodic interrupt is generated. 0: interrupt is not generated at interval specified by bits pes2?pes0 [clearing condition] when 0 is written to pef 1: interrupt is generated at interval specified by bits pes2?pes0 [setting conditions] generation of interrupt at in terval specified by bits pes2?pes0 when 1 is written to pef 6 to 4 pes[2:0] all 0 r/w periodic interrupt enable these bits specify the perio d for periodic interrupts. 000: no periodic interrupt generation 001: periodic interrupt generated at 1/256-second intervals 010: periodic interrupt generated at 1/64-second intervals 011: periodic interrupt generated at 1/16-second intervals 100: periodic interrupt generated at 1/4-second intervals 101: periodic interrupt generated at 1/2-second intervals 110: periodic interrupt generated at 1-second intervals 111: periodic interrupt generated at 2-second intervals 3 rtcen 1 r/w oscillator enable controls the operation of t he rtc's crystal oscillator. 0: rtc crystal oscillator is halted 1: rtc crystal oscillator is operated
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 725 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 adj 0 r/w 30-second adjustment used for 30-second adjustment. when 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. the frequency divider circuits (rtc prescaler and r64cnt) are also reset at this time. this bit always returns 0 if read. 0: normal clock operation 1: 30-second adjustment performed 1 reset 0 r/w reset the frequency divider circuits are initialized by writing 1 to this bit. when 1 is written to the reset bit, the frequency divider circuits (rtc prescaler and r64cnt) are reset and the reset bit is automatically cleared to 0 (i.e. does not need to be written with 0). 0: normal clock operation 1: frequency divider circuits are reset 0 start 1 r/w start bit stops and restarts counter (clock) operation. 0: second, minute, hour, day, day-of-week, month, and year counters are stopped * 1: second, minute, hour, day, day-of-week, month, and year counters operate normally * note: * the 64 hz counter continues to operate unless stopped by means of the rtcen bit.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 726 of 1286 rej09b0158-0100 20.3.18 rtc control register (rcr3) rcr3 is readable/writable register that specifies enable or disabl e the alarm function of ryrcnt that is the rtc's bcd-coded year-value counter. when the yenb bit of rcr3 is set to 1, the ryrcnt value is compared with the ryrar value. rcr3 is initialized by a power-on reset. bits 6 to 0 of rcr3 are always read as 0. a write to these bits is invalid. if a value is written to these bits, it should always be 0. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? yenb r r r r r r r r/w bit: initial value: r/w:
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 727 of 1286 rej09b0158-0100 20.4 operation examples of the use of the rtc are shown below. 20.4.1 time setting procedures figure 20.2 shows examples of the time setting procedures. stop clock reset frequency divider set second/minute/hour/day/ day-of-week/month/year start clock operation (a) setting time after stopping clock (b) setting time while clock is running set rcr2.reset to 1. clear rcr2.start to 0. in any order. set rcr2.start to 1. clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm flag is not cleared). set ryrcnt first and rseccnt last. read rcr1 register and check cf bit. clear carry flag write to counter register carry flag = 1? no yes figure 20.2 examples of time setting procedures the procedure for setting the time after stopping the clock is shown in figure 20.2 (a). the programming for this method is simple, and it is useful for setting all the counters, from second to year. the procedure for setting the time while the clock is running is shown in figure 20.2 (b). this method is useful for modifying only certain counter values (for example, only the second data or hour data). if a carry occurs during the write ope ration, the write data is automatically updated and there will be an error in the set data. the carry flag should therefore be used to check the write status. if the carry flag ( rcr1.cf) is set to 1, the write must be repeated. the interrupt function can also be used to determine the carry flag status.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 728 of 1286 rej09b0158-0100 20.4.2 time reading procedures figure 20.3 shows examples of the time reading procedures. no no yes yes no no yes yes (a) reading time without using interrupts (b) reading time using interrupts clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm flag is not cleared). clear rcr1.cie to 0. clear rcr1.cf to 0 (write 1 to rcr1.af so that alarm flag is not cleared). set rcr1.cie to 1. clear rcr1.cie to 0. note: * when h'59 is read out from the second counter register, that should be changed to h'00 and the read out value of the minute counter register should be added to 1 as a carry processing. the hour counter, day-of-week, day, month, and year counters may be necessary to do carry processing. read rcr1 register and check cf bit. clear carry flag read counter register disable carry interrupts clear carry flag enable carry interrupts interrupt generated? clear carry flag disable carry interrupts read counter register crf = 1? crf = 1? add 1 (second) to the second counter register value that is read out * add 1 (second) to the second counter register value that is read out * cf = 1? figure 20.3 examples of time reading procedures
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 729 of 1286 rej09b0158-0100 if a carry occurs or being the carry ready period (rcr1.crf = 1) while the time is being read, the correct time will not be obtained and the read mu st be repeated. the procedure for reading the time without using interrupts is shown in figure 20 .3 (a), and the procedur e using carry interrupts in figure 20.3 (b). the method without using interrupts is normally used to keep the program simple. 20.4.3 alarm function the use of the alarm function is illustrated in figure 20.4. monitor alarm time (wait for interrupt or check alarm flag) clock running disable alarm interrupts set alarm time clear alarm flag enable alarm interrupts clear rcr1.aie to prevent erroneous interrupts. be sure to reset the flag as it may have been set during alarm time setting. set rcr1.aie to 1. figure 20.4 example of use of alarm function an alarm can be generated by the second, minute, hour, day-of-week, day, month, or year value, or a combination of thes e. write 1 to the enb bit in the al arm registers involved in the alarm setting, and set the alarm time in the lower bits. write 0 to the enb bit in registers not involved in the alarm setting. when the counter and the alarm time match, rcr1.af is set to 1. alarm detection can be confirmed by reading this bit, but normally an interrupt is used. if 1 has been written to rcr1.aie, an alarm interrupt is generated in th e event of alarm, enabling the alarm to be detected.
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 730 of 1286 rej09b0158-0100 20.5 interrupts there are three kinds of rtc interrupt: alarm interr upts, periodic interrupts, and carry interrupts. an alarm interrupt request (ati) is generated when the alarm flag (af) in rcr1 is set to 1 while the alarm interrupt enable bit (aie) is also set to 1. a periodic interrupt request (pri) is generated when the periodic interrupt enable bits (pes2? pes0) in rcr2 are set to a value other than 000 and the periodic interrupt flag (pef) is set to 1. a carry interrupt request (cui) is generated when th e carry flag (cf) in rcr1 is set to 1 while the carry interrupt enable bit (cie) is also set to 1. 20.6 usage notes 20.6.1 register initialization after powering on and making the rcr1 register settings, reset the frequency divider (by setting rcr2.reset to 1) and make initial se ttings for all the other registers. 20.6.2 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 20.4, and the rtc crystal oscillator circuit in figure 20.5. table 20.4 crystal oscillator circu it constants (rec ommended values) f osc c in c out 32.768 khz 10?22 pf 10?22 pf
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 731 of 1286 rej09b0158-0100 extal2 xtal2 xtal c in c out r f r d noise filter notes: 1. select either the c in or c out side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. built-in resistance value r f (typ. value) = 10 m ? , r d (typ. value) = 400 k ? 3. c in and c out values include floating capacitance due to the wiring. take care when using a solidearth board. 4. the crystal oscillation stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2 and xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. 7. insert a noise filter in the rtc power supply. c rtc r rtc 3.3 v vdd-rtc vss-rtc sh7780 figure 20.5 example of crys tal oscillator ci rcuit connection
section 20 realtime clock (rtc) rev.1.00 dec. 13, 2005 page 732 of 1286 rej09b0158-0100 20.6.3 interrupt source and request generating order if it occurs complex interrupt sour ce of alarm interrupts (ati), periodic interrupts (pfi), and carry interrupts (cui) at the same time, the rtc generates interrupt request as shown in figure 20.6. pck (50mhz) extal2 (32.768khz) tclk (16.384khz) rseccnt[7:0] second counter register r64cnt[7:0] 64hz counter register rcr2.pef periodical interrupt flag (interrupt request signal) rcr1.cf carry flag (interrupt request signal) rcr1.af alarm flag (interrupt request signal) n+1 h'7f n carry, periodical, and alarm interrupt extal2 4 clock cycles carry ready period h'00 pck 2 clock cycles pck 4 to 6 clock cycles pck 6 to 8 clock cycles figure 20.6 interrupt request signal ge neration timing of complex sources
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 733 of 1286 rej09b0158-0100 section 21 serial communi cation interface with fifo (scif) this lsi is equipped with a 2-ch annel serial communication inte rface with built-in fifo buffers (serial communication interface with fifo: scif). the scif can perform both asynchronous and clocked synchronous serial communications. 64-stage fifo buffers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. channels 0 has modem control functions ( rts , cts ). 21.1 features the scif has the following features. ? asynchronous serial communication mode serial data communication is executed us ing an asynchronous system in which synchronization is achieved character by charact er. serial data commun ication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchrono us communication interface adapter (acia). there is a choice of 8 serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? receive error detection: parity , framing, and overrun errors ? break detection: a break is detected when a framing error lasts for more than 1 frame length at space 0 (low level). when a framing er ror occurs, a break can also be detected by reading the scifn_rxd (n = 0, 1) pin level directly from the serial port register (scsptr). ? clocked synchronous serial communication mode serial data communication is synchronized with a clock. serial data communication can be carried out with other lsis that have a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? receive error detecti on: overrun errors
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 734 of 1286 rej09b0158-0100 ? full-duplex communication capability the transmitter and receiver are independent units , enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 64-stage fifo buffer structure, enabling continuous serial data transmission and reception. ? lsb first for data transmission/reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from scif0_sck or scif1_sck pin. ? four interrupt sources there are four interrupt sour ces?transmit-fifo-dat a-empty, break, receive-fifo-data-full, and receive-error?that can issu e requests independently. ? the dma controller (dmac) can be activated to execute a data transfer by issuing a dma transfer request in the event of a transmit-fifo-data-empty or receive-fifo-data-full interrupt. ? when not in use, the scif can be stopped by halting its clock supply to reduce power consumption. ? in asynchronous mode, modem control functions ( rts and cts ) are provided.(only in channel 0) ? the amount of data in the transm it/receive fifo registers, and the number of receive errors in the receive data in the receive fi fo register, can be ascertained. ? in asynchronous mode, a timeout error (dr) can be detected during reception. figure 21.1 shows a block diagram of the scif. figures 21.2 to 21.6 show block diagrams of the i/o ports in scif. there are two channels in this lsi (channel n = 0, 1).
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 735 of 1286 rej09b0158-0100 module data bus scfrdrn 64-stage scftdrn 64-stage bus interface parity generation parity check external clock clock transmit/receive control baud rate generator peripheral bus scifn [legend] scrsrn: scfrdrn: sctsrn: scftdrn: scsmrn: scscrn: scfsrn: receive shift register receive fifo data register transmit shift register transmit fifo data register serial mode register serial control register serial status register scbrrn: scsptrn: scfcrn: sctfdrn: scrfdrn: sclsrn: scrern: bit rate register serial port register fifo control register transmit fifo data count register receive fifo data count register line status register serial error register scrsrn sctsrn scsmrn sclsrn sctfdrn scrfdrn scfcrn scfsrn scscrn scsptrn scrern scbrrn txin rxin erin brin scif0_rts (channel 0 only) scif0_cts (channel 0 only) scifn_sck scifn_txd scifn_rxd pck pck/64 pck/4 pck/16 note: n = 0, 1 figure 21.1 block diagram of scif
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 736 of 1286 rej09b0158-0100 figures 21.2 to 21.6 show block diagrams of the i/o ports in scif. reset peripheral bus sptrw d7 d6 r q d rtsio c reset sptrr sptrw r q d rtsdt c sptrw: scif0_rts scif_rts signal write to scsptr sptrr: read from scsptr note: * the scif0_rts pin function is designated as modem control by the mce bit in scfcr. modem control enable signal * figure 21.2 scif0_rts pin (only in channel 0) reset peripheral bus sptrw d5 d4 r q d ctsio c reset sptrr sptrw r q d ctsdt c sptrw: scif0_cts scif_cts signal write to scsptr sptrr: read from scsptr note: * the scif0_cts pin function is designated as modem control by the mce bit in scfcr. modem control enable signal * figure 21.3 scif0_cts pin (only in channel 0)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 737 of 1286 rej09b0158-0100 reset peripheral bus sptrw: write to scsptr sptrr: read from scsptr sptrw r q d d3 d2 sckio c reset sptrw r q d sckdt c scifn_clk clock output enable signal * serial clock output signal * serial clock input signal * serial input enable signal * note: * the scifn_clk pin function is designated as internal clock output or external clock input by the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. sptrr figure 21.4 scifn_sck pin (n = 0, 1) reset peripheral bus sptrw r q d d1 d0 spb2io c reset sptrw r q d spb2dt c scifn_txd sptrw: write to scsptr transmit enable signal serial transmit data figure 21.5 scifn_txd pin (n = 0, 1)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 738 of 1286 rej09b0158-0100 peripheral bus scifn_rxd sptrr serial receive data sptrr: read from scsptr figure 21.6 scifn_rxd pin (n = 0, 1)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 739 of 1286 rej09b0158-0100 21.2 input/output pins table 21.1 shows the scif pin configuration. table 21.1 pin configuration pin name function i/o description scif0_sck channel 0 serial clock pin i/o clock input/output scif0_rxd channel 0 receive dat a pin input receive data input scif0_txd channel 0 transmit dat a pin output transmit data output scif0_cts channel 0 modem control pin i/o transmission enabled scif0_rts channel 0 modem control pin i/o transmission request scif1_sck channel 1 serial clock pin i/o clock input/output scif1_rxd channel 1 receive data pin input receive data input scif1_txd channel 1 transmit data pin output transmit data output notes: these pins are made to function as serial pins by performing scif operation settings with the c/ a bit in scsmr, the te, re, cke1, and cke0 bits in scscr, and the mce bit in scfcr. break state transmission and detec tion can be set in scsptr of the scif. channel 0 pins are multiplexed with the pcic, hspi, flctl, gpio and mode control pins, and channel 1 pins are multiplexed with the mmcif, gpio and mode control pins.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 740 of 1286 rej09b0158-0100 21.3 register descriptions table 21.2 shows the register configuration. table 21.3 show s the register states in each processing mode. table 21.2 register configuration ch. register name abbrev. r/ w p4 address area 7 address size sync clock 0 serial mode register 0 scsmr0 r/w h'ffe0 0000 h'1fe0 0000 16 pck bit rate register 0 scbrr0 r/w h'ffe0 0004 h'1fe0 0004 8 pck serial control register 0 scscr0 r/w h'ffe0 0008 h'1fe0 0008 16 pck transmit fifo data register 0 sc ftdr0 w h'ffe0 000c h'1fe0 000c 8 pck serial status register 0 scfsr0 r/w * 1 h'ffe0 0010 h'1fe0 0010 16 pck receive fifo data register 0 scfrdr0 r h'ffe0 0014 h'1fe0 0014 8 pck fifo control register 0 scf cr0 r/w h'ffe0 0018 h'1fe0 0018 16 pck transmit fifo data count register 0 sctfdr0 r h'ffe0 001c h'1fe0 001c 16 pck receive fifo data count register 0 scrfdr0 r h'ffe0 0020 h'1fe0 0020 16 pck serial port register 0 scsptr0 r/w h'ffe0 0024 h'1fe0 0024 16 pck line status register 0 sclsr0 r/w * 2 h'ffe0 0028 h'1fe0 0028 16 pck serial error register 0 screr0 r h'ffe0 002c h'1fe0 002c 16 pck 1 serial mode register 1 scsmr1 r/w h'ffe1 0000 h'1fe1 0000 16 pck bit rate register 1 scbrr1 r/w h'ffe1 0004 h'1fe1 0004 8 pck serial control register 1 scscr1 r/w h'ffe1 0008 h'1fe1 0008 16 pck transmit fifo data register 1 sc ftdr1 w h'ffe1 000c h'1fe1 000c 8 pck serial status register 1 scfsr1 r/w * 1 h'ffe1 0010 h'1fe1 0010 16 pck receive fifo data register 1 scfrdr1 r h'ffe1 0014 h'1fe1 0014 8 pck fifo control register 1 scf cr1 r/w h'ffe1 0018 h'1fe1 0018 16 pck transmit fifo data count register 1 sctfdr1 r h'ffe1 001c h'1fe1 001c 16 pck receive fifo data count register 1 scrfdr1 r h'ffe1 0020 h'1fe1 0020 16 pck serial port register 1 scsptr1 r/w h'ffe1 0024 h'1fe1 0024 16 pck line status register 1 sclsr1 r/w * 2 h'ffe1 0028 h'1fe1 0028 16 pck serial error register 1 screr1 r h'ffe1 002c h'1fe1 002c 16 pck notes: 1. to clear the flags, 0s can onl y be written to bits 7 to 4, 1, and 0. 2. to clear the flag, 0 can only be written to bit 0.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 741 of 1286 rej09b0158-0100 table 21.3 register states of sc if in each processing mode ch. register name abbrev. power-on reset by preset pin/ wdt/h-udi manual reset by wdt/multiple exception sleep by sleep instruction module standby 0 serial mode register 0 scsmr0 h'0000 h'0000 retained retained bit rate register 0 scbrr0 h'ff h'ff retained retained serial control register 0 scscr0 h'0000 h'0000 retained retained transmit fifo data register 0 scft dr0 undefined undefined retained retained serial status register 0 scfsr0 h'0060 h'0060 retained retained receive fifo data register 0 scfrdr0 undefined undefined retained retained fifo control register 0 scfcr0 h'0000 h'0000 retained retained transmit fifo data count register 0 sctfdr0 h'0000 h'0000 retained retained receive fifo data count register 0 scrfdr0 h'0000 h'0000 retained retained serial port register 0 scsptr0 h'0000 * 1 h'0000 * 1 retained retained line status register 0 sclsr0 h'0000 h'0000 retained retained serial error register 0 screr0 h'0000 h'0000 retained retained 1 serial mode register 1 scsmr1 h'0000 h'0000 retained retained bit rate register 1 scbrr1 h'ff h'ff retained retained serial control register 1 scscr1 h'0000 h'0000 retained retained transmit fifo data register 1 scft dr1 undefined undefined retained retained serial status register 1 scfsr1 h'0060 h'0060 retained retained receive fifo data register 1 scfrdr1 undefined undefined retained retained fifo control register 1 scfcr1 h'0000 h'0000 retained retained transmit fifo data count register 1 sctfdr1 h'0000 h'0000 retained retained receive fifo data count register 1 scrfdr1 h'0000 h'0000 retained retained serial port register 1 scsptr1 h'0000 * 2 h'0000 * 2 retained retained line status register 1 sclsr1 h'0000 h'0000 retained retained serial error register 1 screr1 h'0000 h'0000 retained retained notes: 1. bits 2 and 0 are undefined. 2. bits 6, 4, 2, and 0 are undefined.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 742 of 1286 rej09b0158-0100 since the register functions, pin functions, and interrupt requests are the same in each channel except for the modem control, the channel number n (n = 0, 1) is omitted in the description below. 21.3.1 receive shift register (scrsr) scrsr is the register used to receive serial data. the scif sets serial data input from the scif_rxd pin in scrsr in the order received, starting with the lsb (bit 0), and converts it to parallel da ta. when one byte of data has been received, it is transferred to scfr dr, automatically. scrsr cannot be directly read from and written to by the cpu. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit: initial value: r/w: 21.3.2 receive fifo da ta register (scfrdr) scfrdr is an 8-bit fifo register of 64 stages that stores received serial data. when the scif has received one byte of serial da ta, it transfers the receive d data from scrsr to scfrdr where it is stored, and completes the r eceive operation. scrsr is then enabled for reception, and consecutive receive operations can be performed un til scfrdr is full (64 data bytes). scfrdr is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in scfrdr, an u ndefined value will be returned. when scfrdr is full of receive data, subsequent seri al data is lost. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit: initial value: r/w:
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 743 of 1286 rej09b0158-0100 21.3.3 transmit shift register (sctsr) sctsr is the register used to transmit serial data. to perform serial data transmission, the scif first transfers transmit data from scftdr to sctsr, then sends the data to the scif_txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr to sctsr, and transmission started, automatically. sctsr cannot be directly read from and written to by the cpu. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit: initial value: r/w: 21.3.4 transmit fifo data register (scftdr) scftdr is an 8-bit fifo regist er of 64 stages that stores data for serial transmission. if sctsr is empty when transmit data has been written to scftdr, the scif transfers the transmit data written in scftdr to sctsr and starts serial transmission. scftdr is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr is filled with 64 bytes of transmit data. data written in this case is ignored. 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? w w w w w w w w bit: initial value: r/w:
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 744 of 1286 rej09b0158-0100 21.3.5 serial mode register (scsmr) scsmr is a 16-bit register used to set the scif's serial transfer format and select the baud rate generator clock source. scsmr can always be read from and written to by the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 cks0 cks1 ? stop o/ e pe chr c/ a ? ? ? ? ? ? ?? r/w r/w r r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 c/ a 0 r/w communication mode selects asynchronous mode or clocked synchronous mode as the scif operating mode. 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length selects 7 or 8 bits as the asynchronous mode data length. in clocked synchronous mode, the data length is fixed at 8 bits regardless of the chr bit setting. when 7-bit data is selected, the m sb (bit 7) of scftdr is not transmitted. 0: 8-bit data 1: 7-bit data
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 745 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 pe 0 r/w parity enable in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. in clocked synchronous mode, parity bit addition and checking is disabled regardless of the pe bit setting. 0: parity bit addition and checking disabled 1: parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. 4 o/ e 0 r/w parity mode selects either even or odd parity for use in parity addition and checking. in asynchronous mode, the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking. in clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode, the o/ e bit setting is invalid. 0: even parity 1: odd parity when even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 746 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 stop 0 r/w stop bit length in asynchronous mode, selects 1 or 2 bits as the stop bit length. the stop bit se tting is valid only in asynchronous mode. since the stop bit is not added in clocked synchronous mode, the stop bit setting is invalid. 0: 1 stop bit * 1 1: 2 stop bits * 2 in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bi t; if it is 0, it is treated as the start bit of the next transmit character. note: 1. in transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock source for the on-chip baud rate generator. the clock source can be selected from pck, pck/4, pck/16, and p ck/64, according to the setting of bits cks1 and cks0. for details of the relationship between clock sources, bit rate register settings, and baud rate, see section21.3.8, bit rate register n (scbrr). 00: pck clock 01: pck/4 clock 10: pck/16 clock 11: pck/64 clock note: pck = peripheral clock
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 747 of 1286 rej09b0158-0100 21.3.6 serial control register (scscr) scscr is a register used to enable/disable transmission/reception by scif, serial clock output, interrupt requests, and to select transm ission/reception clock source for the scif. scscr can always be read from and written to by the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 cke0 cke1 ? reie re te rie tie ? ? ? ? ? ? ?? r/w r/w r r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 tie 0 r/w transmit interrupt enable enables or disables transm it-fifo-data-empty interrupt (txi) request generation when serial transmit data is transferred from scftdr to sctsr, the number of data bytes in scftdr falls to or below the transmit trigger set number, and the tdfe flag in scfsr is set to 1. txi interrupt requests can be cleared using the following methods: either by reading 1 from the tdfe flag in scfsr, writing transmit data exceeding the transmit trigger set number to scftdr and then clearing the tdfe flag in scfsr to 0, or by clearing the tie bit to 0. 0: transmit-fifo-data-empt y interrupt (txi) request disabled 1: transmit-fifo-data-empt y interrupt (txi) request enabled
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 748 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 rie 0 r/w receive interrupt enable enables or disables generation of a receive-data-full interrupt (rxi) request when the rdf flag or dr flag in scfsr is set to 1, a receive-error interrupt (eri) request when the er flag in scfsr is set to 1, and a break interrupt (bri) request when the brk flag in scfsr or the orer flag in sclsr is set to 1. 0: receive-data-full interrupt (rxi) request, receive- error interrupt (eri) request, and break interrupt (bri) request disabled 1: receive-data-full interrupt (rxi) request, receive- error interrupt (eri) request, and break interrupt (bri) request enabled note: an rxi interrupt request can be cleared by reading 1 from the rdf or dr flag in scfsr, then clearing the flag to 0, or by clearing the rie bit to 0. eri and bri interrupt requests can be cleared by reading 1 from the er, brk, or orer flag in scfsr, then clearing the flag to 0, or by clearing the rie and reie bits to 0. 5 te 0 r/w transmit enable enables or disables the start of serial transmission by the scif. serial transmission is started when transmit data is written to scftdr while the te bit is set to 1. 0: transmission disabled 1: transmission enabled * note: scsmr and scfcr settings must be made, the transmission format decided, and the transmit fifo reset, before the te bit is set to 1.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 749 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 re 0 r/w receive enable enables or disables the start of serial reception by the scif. serial reception is started wh en a start bit is detected in this state in asynchronous mode or a synchronization clock is input while the re bit is set to 1. it should be noted that clearing the re bit to 0 does not affect the dr, er, brk, rdf, fer, per flags in scfsr, and orer flag in sclsr, which retain their states. serial reception begins once the start bit is detected in these states. 0: reception disabled 1: reception enabled * note: * scsmr and scfcr settings must be made, the reception format decided, and the receive fifo reset, before the re bit is set to 1. 3 reie 0 r/w receive error interrupt enable enables or disables generation of receive-error interrupt (eri) and break interrupt (bri) requests. the reie bit setting is valid only when the rie bit is 0. receive-error interrupt (eri) and break interrupt (bri) requests can be cleared by reading 1 from the er, brk in scfsr, or orer fl ag in sclsr, then clearing the flag to 0, or by clearing the rie and reie bits to 0. when reie is set to 1, eri and bri interrupt requests will be generated even if rie is cleared to 0. in dma transfer, this setting is made if the interrupt controller is to be notified of eri and bri interrupt requests. 0: receive-error interrupt (eri) and break interrupt (bri) requests disabled 1: receive-error interrupt (eri) and break interrupt (bri) requests enabled 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 750 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 these bits select the scif clock source and whether to enable or disable the clock output from the scif_sck pin. the cke1 and cke0 bits are used together to specify whether the scif_sck pin functions as a serial clock output pin or a serial clock input pin. note however that the cke0 bit setting is valid only when an internal clock is selected as the scif clock source (cke1 = 0). when an external clock is selected (cke1 = 1), the cke0 bit setting is invalid. the cke1 and cke0 bits must be set before determining the scif's operating mode with scsmr. ? asynchronous mode 00: internal clock/scif_sck pin functions as port by setting scsptr register 01: internal clock/scif_sck pin functions as clock output * 1 1x: external clock/scif_sck pin functions as clock input * 2 ? clocked synchronous mode 0x: internal clock/scif_sck pin functions as synchronization clock output 1x: external clock/scif_sck pin functions as synchronization clock input notes: x: don't care 1. outputs a clock with a frequency 16 times the bit rate. 2. inputs a clock with a frequency 16 times the bit rate.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 751 of 1286 rej09b0158-0100 21.3.7 serial status register n (scfsr) scfsr is a 16-bit register that consists of stat us flags that indicate th e operating status of the scif. scfsr can be read from or written to by the cp u at all times. however, 1 cannot be written to flags er, tend, tdfe, brk, rdf, and dr. also note that in order to clear these flags they must be read as 1 beforehand. the fer flag and per flag are read-only flags and cannot be modified. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 1 0 0 0 0 0 0 0 00 dr rdf per fer brk tdfe tend er ? ? ? ? ? ? ?? r/w * r/w * r r r/w * r/w * r/w * r/w * r r r r r r rr bit: initial value: r/w: note: * only 0 can be written, to clear the flag. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 752 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 er 0 r/w * receive error indicates that a framing error or parity error occurred during reception. the er flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr, and reception continues. the fer and per bits in scfsr can be used to determine whether there is a receive error in the readout data from scfrdr. 0: no framing error or parity error occurred during reception [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1: a framing error or parity error occurred during reception [setting conditions] ? when the scif checks whet her the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * ? when, in reception, the number of 1-bits in the receive data plus the parit y bit does not match the parity setting (even or odd) specified by the o/ e bit in scsmr note: in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. 6 tend 1 r/w * transmit end indicates that transmission has been ended without valid data in scftdr after transmission of the last bit of the transmit character. 0: transmission is in progress [clearing conditions] ? when transmit data is written to scftdr, and 0 is written to tend after reading tend = 1 ? when data is written to scftdr by the dmac 1: transmission has been ended [setting conditions] ? power-on reset or manual reset ? when the te bit in scscr is 0 ? when there is no transmit data in scftdr after transmission of the last bit of a 1-byte serial transmit character
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 753 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 tdfe 1 r/w * transmit fifo data empty indicates that data has been transferred from scftdr to sctsr, the number of data bytes in scftdr has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in scfcr, and new transmit data can be written to scftdr. 0: a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr [clearing conditions] ? when transmit data exceeding the transmit trigger set number is written to scftdr after reading tdfe = 1, and 0 is written to tdfe ? when transmit data exceeding the transmit trigger set number is written to scftdr by the dmac 1: the number of transmit data bytes in scftdr does not exceed the transmit trigger set number (initial value) [setting conditions] ? power-on reset or manual reset ? when the number of scftdr transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * note: as scftdr is a 64-byte fifo register, the maximum number of bytes that can be written when tdfe = 1 is 64 - (transmit trigger set number). data written in excess of this will be ignored. sctfdr indicates the number of data bytes transmitted to scftdr.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 754 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 brk 0 r/w * break detect indicates that a receive data break signal has been detected. 0: a break signal has not been received [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1: a break signal has been received * [setting condition] ? when data with a framing error is received, followed by the space "0" level (low level ) for at least one frame length note: when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr. when the break ends and the receive signal returns to mark "1", receive data transfer is resumed. 3 fer 0 r framing error in asynchronous mode, indicates whether or not a framing error has been found in the data that is to be read next from scfrdr. 0: there is no framing error that is to be read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in the data that is to be read next from scfrdr 1: there is a framing error that is to be read from scfrdr [setting condition] ? when there is a framing error in the data that is to be read next from scfrdr
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 755 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 per 0 r parity error in asynchronous mode, indicates whether or not a parity error has been found in the data that is to be read next from scfrdr. 0: there is no parity error that is to be read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in the data that is to be read next from scfrdr 1: there is a parity error in the receive data that is to be read from scfrdr [setting condition] ? when there is a parity error in the data that is to be read next from scfrdr
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 756 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 rdf 0 r/w * receive fifo data full indicates that the received data has been transferred from scrsr to scfrdr, and the number of receive data bytes in scfrdr is equa l to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in scfcr. 0: the number of receive data bytes in scfrdr is less than the receive trigger set number [clearing conditions] ? power-on reset or manual reset ? when scfrdr is read until the number of receive data bytes in scfrdr falls below the receive trigger set number after reading rdf = 1, and 0 is written to rdf ? when scfrdr is read by the dmac until the number of receive data bytes in scfrdr falls below the receive trigger set number 1: the number of receive data bytes in scfrdr is equal to or greater than the receive trigger set number [setting condition] ? when scfrdr contains at least the receive trigger set number of receive data bytes * note: scfrdr is a 64-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if all the data in scfrdr is read and another read is performed, the data value will be un defined. the number of receive data bytes in scfrdr is indicated by scrfdr.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 757 of 1286 rej09b0158-0100 bit bit name initial value r/w description 0 dr 0 r/w * receive data ready in asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in scfrdr, and no further data has arrived for at least 15 etu after the stop bit of the last data received. this is not set when using clocked synchronous mode. 0: reception is in progress or has ended normally and there is no receive data left in scfrdr [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr has been read after reading dr = 1, and 0 is written to dr ? when all the receive data in scfrdr has been read by the dmac 1: no further receive data has arrived [setting condition] ? when scfrdr contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * [legend] etu: elementary time unit (time for transfer of 1 bit) note: equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. note: * only 0 can be written, to clear the flag.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 758 of 1286 rej09b0158-0100 21.3.8 bit rate register n (scbrr) scbrr is an 8-bit register that set the serial tran smission/reception bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr. scbrr can always be read from and written to by the cpu. the scbrr setting is found from the following equation. asynchronous mode: n = 10 6 - 1 pck 64 2 2n - 1 b clocked synchronous mode: n = 10 6 - 1 pck 8 2 2n - 1 b where b: bit rate (bit/s) n: scbrr setting for baud rate generator (0 n 255) pck: peripheral module operating frequency (mhz) n: 0 to 3 (see table 21.4 for the relation between n and the clock.) table 21.4 scsmr settings scsmr setting n baud rate generator input clock cks1 cks0 0 pck 0 0 1 pck/4 0 1 2 pck/16 1 0 3 pck/64 1 1 the bit rate error in asynchronous mode is found from the following equation: error (%) = - 1 100 pck 10 6 (n + 1) b 64 2 2n - 1
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 759 of 1286 rej09b0158-0100 21.3.9 fifo control register n (scfcr) scfcr performs data count resetting and trigger data number setting for transmit and receive fifo registers, and also contai ns a loopback test enable bit. scfcr can always be read from and written to by the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 loop rfcl tfcl mce * note: * reserved bit in channel 1. ttrg0 ttrg1 rtrg0 rtrg1 rst rg2 * rst rg1 * rst rg0 * ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 rstrg2 * rstrg1 * rstrg0 * 0 0 0 r/w r/w r/w scif0_rts output active trigger the scif0_rts signal becomes high when the number of receive data stor ed in scfrdr exceeds the trigger number shown below. 000:63 001:1 010:8 011:16 100:32 101:48 110:54 111:60
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 760 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 6 rtrg1 rtrg0 0 0 r/w r/w receive fifo data number trigger these bits are used to set the number of receive data bytes that sets the rdf flag in scfsr. the rdf flag is set when the number of receive data bytes in scfrdr is equal to or greater than the trigger set number shown below. 00:1 01:16 10:32 11:48 5 4 ttrg1 ttrg0 0 0 r/w r/w transmit fifo data number trigger these bits are used to set the number of remaining transmit data bytes that sets the tdfe flag in scfsr. the tdfe flag is set when the number of transmit data bytes in scftdr is equal to or less than the trigger set number shown below. 00: 32 (32) 01:16 (48) 10: 2 (62) 11: 0 (64) note: figures in parentheses are the number of empty bytes in scftdr when the flag is set. 3 mce * 0 r/w modem control enable enables the scif0_cts and scif0_rts modem control signals. always set th e mce bit to 0 in clocked synchronous mode. 0: modem signals disabled 1: modem signals enabled note: when the mce bit is 0, scif0_cts is fixed at active-0 regardless of the input value, and scif0_rts output is also fixed at 0.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 761 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 tfcl 0 r/w transmit fifo data count register clear clears the transmit fifo dat a count register to 0. 0: clear operation disabled 1: clear operation enabled note: a reset operation is performed in the event of a power-on reset or manual reset. 1 rfcl 0 r/w receive fifo data count register clear clears the transmit fifo dat a count register to 0. 0: clear operation disabled 1: clear operation enabled note: a reset operation is performed in the event of a power-on reset or manual reset. 0 loop 0 r/w loopback test internally connects the transmit output pin (scif_txd) and receive input pin (scif_rxd), and the scif0_rts pin and scif0_cts pin (for channel 0), enabling loopback testing. 0: loopback test disabled 1: loopback test enabled note: * only channel 0. reserved bit in channel 1.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 762 of 1286 rej09b0158-0100 21.3.10 transmit fifo data count register n (sctfdr) sctfdr is a 16-bit register that indicates the nu mber of transmit data bytes stored in scftdr. sctfdr can always be read from the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 t0 t1 t2 t3 t4 t5 t6 ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 to 0 t6 to t0 all 0 r these bits show the number of untransmitted data bytes in scftdr. a value of h'00 indicates that there is no transmit data, and a value of h'40 indicates that scftdr is full of transmit data.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 763 of 1286 rej09b0158-0100 21.3.11 receive fifo data count register n (scrfdr) scrfdr is a 16-bit register that indicates the number of receive data bytes stored in scfrdr. scrfdr can always be read from the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 r0 r1 r2 r3 r4 r5 r6 ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 to 0 r6 to r0 all 0 r these bits show the number of receive data bytes in scfrdr. a value of h'00 i ndicates that there is no receive data, and a value of h'40 indicates that scfrdr is full of receive data.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 764 of 1286 rej09b0158-0100 21.3.12 serial port register n (scsptr) scsptr is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial commu nication interface (scif) pins at all times. input data can be read from the scif_rxd pin, output data writte n to the scif_txd pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. all scsptr bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. scsptr is not initialized in the module standby state. note that when reading data via a serial port pi n in the scif, the peripheral clock value from 2 cycles before is read. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? 0 ? 0 ? 0 ? 0 0 0 0 0 0 0 00 spb2 dt spb2 io sck dt sck io cts dt * cts io * rts dt * rts io * ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: note: * reserved bit in channel 1. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 rtsio * 0 r/w serial port scif0_rts port input/output specifies the serial port scif0_rts pin input/output condition. when actually setting the scif0_rts pin as a port output pin to output the value set by the rtsdt bit, the mce bit in scfcr should be cleared to 0. 0: rtsdt bit value is not output to scif0_rts pin 1: rtsdt bit value is output to scif0_rts pin
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 765 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 rtsdt * ? r/w serial port scif0_rts port data specifies the serial port scif0_rts pin input/output data. input or output is s pecified by the rtsio bit. in output mode, the rtsdt bit value is output to the scif0_rts pin. the scif0_rts pin value is read from the rtsdt bit regardless of the value of the rtsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. 0: input/output dat a is low-level 1: input/output dat a is high-level 5 ctsio * 0 r/w serial port scif0_cts port input/output specifies the serial port scif0_cts pin input/output condition. when actually setting the scif0_cts pin as a port output pin to output the value set by the ctsdt bit, the mce bit in scfcr should be cleared to 0. 0: ctsdt bit value is not output to scif0_cts pin 1: ctsdt bit value is output to scif0_cts pin 4 ctsdt * ? r/w serial port scif0_cts port data specifies the serial port scif0_cts pin input/output data. input or output is s pecified by the ctsio bit. in output mode, the ctsdt bit value is output to the scif0_cts pin. the scif0_cts pin value is read from the ctsdt bit regardless of the value of the ctsio bit. the initial value of this bit after a power-on reset or manual reset is undefined. 0: input/output dat a is low-level 1: input/output dat a is high-level 3 sckio 0 r/w serial port clock port input/output specifies the serial port scif_sck pin input/output condition. when actually setting the scif_sck pin as a port output pin to output the value set by the sckdt bit, the cke1 and cke0 bits in scscr should be cleared to 0. 0: sckdt bit value is not output to scif_sck pin 1: sckdt bit value is output to scif_sck pin
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 766 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 sckdt ? r/w serial port clock port data specifies the serial port scif_sck pin input/output data. input or output is s pecified by the sckio bit. in output mode, the sckdt bit value is output to the scif_sck pin. the scif_sck pin value is read from the sckdt bit regardless of the value of the sckio bit. the initial value of this bit after a power-on reset or manual reset is undefined. 0: input/output dat a is low-level 1: input/output dat a is high-level 1 spb2io 0 r/w serial port break input/output specifies the serial port sc if_txd pin output condition. when actually setting the scif_txd pin as a port output pin to output the va lue set by the spb2dt bit, the te bit in scscr should be cleared to 0. 0: spb2dt bit value is not output to the scif_txd pin 1: spb2dt bit value is out put to the scif_txd pin 0 spb2dt ? r/w serial port break data specifies the serial port scif_rxd pin input data and scif_txd pin output data. the scif_txd pin output condition is specified by the spb2io bit. when the scif_txd pin is designated as an output, the value of the spb2dt bit is output to the scif_txd pin. the scif_rxd pin value is read from the spb2dt bit regardless of the value of the spb2io bit. the initial value of this bit after a power-on reset or manual reset is undefined. 0: input/output dat a is low-level 1: input/output dat a is high-level note: * only channel 0. reserved bit in channel 1.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 767 of 1286 rej09b0158-0100 21.3.13 line status register n (sclsr) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 orer ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r/w * r r r r r r r r r r r r r rr bit: initial value: r/w: note: * only 0 can be written, to clear the flag. bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 orer 0 r/w * overrun error indicates that an overrun error occurred during reception, causing abnormal termination. 0: reception in progress, or reception has ended normally [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. 1: an overrun error occurred during reception [setting condition] ? when the next serial reception is completed while scfrdr receives 64-byte data (scfrdr is full) the receive data prior to the overrun error is retained in scfrdr, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. note: * only 0 can be written, to clear the flag.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 768 of 1286 rej09b0158-0100 21.3.14 serial error register n (screr) screr is a 16-bit register that indicates the numb er of receive errors in the data in scfrdr. screr can always be read from the cpu. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 fer0 fer1 fer2 fer3 fer4 fer5 ? ? per0 per1 per2 per3 per4 per5 ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 11 10 9 8 per5 per4 per3 per2 per1 per0 0 0 0 0 0 0 r r r r r r number of parity errors these bits indicate the number of data bytes in which a parity error occurred in the receive data stored in scfrdr. after the er bit in scfsr is set, the value indicated by bits per5 to per0 is the number of data bytes in which a parity error occurred. if all 64 bytes of receive data in scfrdr have parity errors, the value indicated by bits per5 to per0 will be 0. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 3 2 1 0 fer5 fer4 fer3 fer2 fer1 fer0 0 0 0 0 0 0 r r r r r r number of framing errors these bits indicate the number of data bytes in which a framing error occurred in the receive data stored in scfrdr. after the er bit in scfsr is set, the value indicated by bits fer5 to fer0 is the number of data bytes in which a framing error occurred. if all 64 bytes of receive data in scfrdr have framing errors, the value indicated by bits fer5 to fer0 will be 0.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 769 of 1286 rej09b0158-0100 21.4 operation 21.4.1 overview the scif can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character and in synchronous mode, in which synchronization is achieved with clock pulses. for details on asynchronous mode, see section 21.4.2, operation in asynchronous mode. 64-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead, and enabling fast and continuous communication to be performed. scif0_rts and scif0_cts signals are also provided as modem control signals (channel 0 only). the serial transfer format is selected using scsmr, as shown in table 21.4. the scif clock source is determined by the combination of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr, as shown in table 21.5. note: since the operations are the same in each channel except for the modem control, the channel number n (n = 0, 1) is omitted in the description below. asynchronous mode: ? data length: choice of 7 or 8 bits ? lsb first for data transmission/reception ? choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer fo rmat and character length) ? detection of framing errors, parity errors, receiv e-fifo-data-full state, overrun errors, receive- data-ready state, and breaks, during reception ? indication of the number of data bytes stored in the transmit and receive fifo registers ? choice of internal (peripheral clock: pck) or external clock (scif_sck input clock) as scif clock source when internal clock is selected: the scif oper ates on the baud rate generator clock and can output a clock with frequency of 16 times the bit rate from scif_sck pin. when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 770 of 1286 rej09b0158-0100 clocked synchronous mode: ? data length: fixed at 8 bits ? lsb first for data transmission/reception ? detection of overrun errors during reception ? choice of internal or external clock input from scif_sck pin as scif clock source when internal clock (peripheral clock: pck) is selected: the scif operates on the baud rate genera tor clock and a serial clock is output to external devices. when external clock (scif_sck input clock) is selected: the on-chip baud rate generator is not used and the scif operates on the input serial clock. table 21.5 scsmr settings for s erial transfer format selection scsmr settings scif transfer format bit 7: c/ a bit 6: chr bit 5: pe bit 3: stop mode data length parity bit stop bit length 0 1 bit 0 1 no 2 bits 0 1 bit 0 1 1 8-bit data yes 2 bits 0 0 1 bit 1 no 2 bits 0 1 bit 0 1 1 1 asynchronous mode 7-bit data yes 2 bits 1 x x x clocked synchronous mode 8-bit data no no note: x: don't care
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 771 of 1286 rej09b0158-0100 table 21.6 scsmr and scscr settings for scif clock source selection scsmr scscr settings bit 7: c/ a bit 1: cke1 bit 0: cke0 mode clock source sck pin function 0 scif does not use scif_sck pin 0 1 internal outputs clock with frequency of 16 times the bit rate 0 inputs clock with frequency of 16 0 1 1 asynchronous mode external times the bit rate 0 outputs synchronization clock 0 1 internal 0 inputs synchronization clock 1 1 1 clocked synchronous mode external
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 772 of 1286 rej09b0158-0100 21.4.2 operation in asynchronous mode in asynchronous mode, a character that consists of data with a start bi t indicating the start of communication and a stop bit indicating the end of communication is transm itted or received. in this mode, serial communication is performe d with synchronization achieved character by character. inside the scif, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and receiver ha ve a 64-stage fifo buff er structure, so that data can be read or written during transmissi on or reception, enabling continuous data transmission and reception. figure 21.7 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the scif monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and star ts serial communication. one character in serial communication consists of a start bit (low level), followed by transmit/receive data (lsb-first; from the lowest b it), a parity bit (high or low level), and finally stop bits (high level). in reception in asyn chronous mode, the scif s ynchronizes with the fall of the start bit. receive data can be latched at the middle of each bit b ecause the scif samples data at the eighth clock which has a frequency of 16 times the bit rate. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 21.7 data format in asynchronous communication (example with 8-bit data, parity, and two stop bits)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 773 of 1286 rej09b0158-0100 (1) data transfer format table 21.7 shows the data transfer formats that can be used. any of 8 tr ansfer formats can be selected according to the scsmr settings. table 21.7 serial transfer formats (asynchronous mode) scsmr settings serial transfer format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 s 8-bit data stop 0 0 1 s 8-bit data stop stop 0 1 0 s 8-bit data p stop 0 1 1 s 8-bit data p stop stop 1 0 0 s 7-bit data stop 1 0 1 s 7-bit data stop stop 1 1 0 s 7-bit data p stop 1 1 1 s 7-bit data p stop stop [legend] s : start bit stop : stop bit p : parity bit
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 774 of 1286 rej09b0158-0100 (2) clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the scif_sck pin can be selected as the scif's serial clock, according to the settings of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. for details of scif clock source selection, see table 21.5. when an external clock is input at the scif_sck pin, the clock frequency should be 16 times the bit rate used. when the scif is operated on an internal clock, a clock whose frequency is 16 times the bit rate is output from the scif_sck pin. (3) scif initialization (asynchronous mode) before transmitting and receiving data, it is necessa ry to clear the te and re bits in scscr to 0, then initialize the scif as described below. when the operating mode or transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. 1. when the te bit is cleared to 0, sctsr is initialized. note that clearing the te and re bits to 0 does not change the contents of scfsr, scftdr, or scfrdr. 2. the te bit should be cleared to 0 after all transmit data has been sent and the tend flag in scfsr has been set. tend can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after th e clearance. before setting te again to start transmission, the tfrst bit in scfcr should first be set to 1 to reset scftdr. 3. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 775 of 1286 rej09b0158-0100 figure 21.8 shows a sample scif initialization flowchart. start of initialization clear te and re bits in scscr to 0 set tfcl and rfcl bits in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te, re, tie, and rie bits cleared to 0) set data transfer format in scsmr set value in scbrr 1-bit interval elapsed? set rtrg1-0, ttrg1-0 bits, and mce in scfcr, and clear tfcl and rfcl bits to 0 set te and re bits in scscr to 1, and set tie, rie, and reie bits end of initialization wait no yes set the clock selection in scscr. be sure to clear bits tie, rie, te, and re to 0. set the data transfer format in scsmr. write a value corresponding to the bit rate into scbrr. (not necessary if an external clock is used.) wait at least one bit interval, then set the te bit or re bit in scscr to 1. also set the rie, reie, and tie bits. setting the te and re bits enables the scif_txd and scif_rxd pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. [1] [1] [2] [3] [4] [2] [3] [4] figure 21.8 sample scif initialization flowchart
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 776 of 1286 rej09b0158-0100 (4) serial data transmission (asynchronous mode): figure 21.9 shows a sample flow chart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. start of transmission read tdfe flag in scfsr tdfe = 1? write transmit data in scftdr, and clear tdfe flag and tend flag in scfsr to 0 all data transmitted? read tend flag in scfsr tend = 1? break output? clear spb2dt to 0 and set spb2io to 1 clear te bit in scscr to 0 end of transmission no yes no yes no yes no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr, and clear the tdfe and tend flags to 0. the number of transmit data bytes that can be written is 64 - (transmit trigger set number). write: [2] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe flag to 0. [3] break output at the end of serial transmission: to output a break in serial transmission, clear the spb2dt bit to 0 and set the spb2io bit to 1 in scsptr, then clear the te bit in scscr to 0. in [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by sctfdr. [1] [2] [3] figure 21.9 sample serial transmission flowchart
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 777 of 1286 rej09b0158-0100 in serial transmission, the scif operates as described below. 1. when data is written into scftdr, the scif transfers the data from scftdr to sctsr and starts transmitting. confirm that the tdfe flag in scfsr is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is at least 64 ? (transmit trigger setting). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls to or below the transmit trigger number set in scfcr, the tdfe flag is set. if the tie bit in scscr is set to 1 at this time, a transmit-fifo- data-empty interrupt (txi) request is generated. the serial transmit data is sent from the scif_txd pin in the following order. (a) start bit: one 0-bit is output. (b) transmit data: 8-bit or 7-bit data is output in lsb-first order. (c) parity bit: one parity bit (even or odd parity) is output. a format in which a parity bit is not output can also be selected. (d) stop bit(s): one or two 1-bits (stop bits) are output. (e) mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at th e timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data after the stop bit is sent, the tend flag in scfsr is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output from the scif_txd pin.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 778 of 1286 rej09b0158-0100 figure 21.10 shows an example of the operation for transmission in asynchronous mode. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to scftdr and tdfe flag read as 1 then cleared to 0 by txi interrupt handler one frame txi interrupt request figure 21.10 sample scif transmission operation (example with 8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and rest arted in accordance with the scif0_cts input value. when scif0_cts is set to 1 during transmission , the line goes to the mark state after transmission of one frame. when scif0_cts is set to 0, the next transmit data is output starting from the start bit. figure 21.11 shows an example of the operation when modem control is used. serial data scif0_txd scif0_cts 0 d0 d1 d7 0/1 0 d0 d1 d7 0/1 drive high before stop bit start bit parity bit stop bit start bit figure 21.11 sample operation using modem control ( scif0_cts ) (only in channel 0)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 779 of 1286 rej09b0158-0100 (5) serial data reception (asynchronous mode) figure 21.12 shows a sample flowchart fo r serial reception. use the following procedure for serial data r eception after enab ling the scif for reception. start of reception read er, dr, brk flags in scfsr and orer flag in sclsr er, dr, brk or orer = 1? read rdf flag in scfsr rdf = 1? read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? clear re bit in scscr to 0 end of reception yes no yes yes no no error handling [1] receive error handling and break detection: read the dr, er, and brk flags in scfsr, and the orer flag in sclsr, to identify any error, perform the appropriate error handling, then clear the dr, er, brk, and orer flags to 0. in the case of a framing error, a break can also be detected by reading the value of the scif_rxd pin. [2] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [3] serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading from scrfdr. [1] [2] [3] figure 21.12 sample serial reception flowchart (1)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 780 of 1286 rej09b0158-0100 error handling receive error handling er = 1? brk = 1? break handling dr = 1? read receive data in scfrdr clear dr, er, brk flags in scfsr, and orer flag in sclsr, to 0 end yes yes yes no overrun error handling orer = 1? yes no no no [1] whether a framing error or parity error has occurred in the receive data that is to be read from scfrdr can be ascertained from the fer and per bits in scfsr. [2] when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00, and the break data in which a framing error occurred is stored. figure 21.12 sample serial reception flowchart (2)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 781 of 1286 rej09b0158-0100 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0-start bit is det ected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. (a) stop bit check: the scif checks whether the stop bit is 1. if there are two stop bits, only the first is checked. (b) the scif checks whether receive data can be transferred from scrsr to scfrdr.* (c) overrun error check: the scif checks that th e orer flag is 0, indi cating that no overrun error has occurred.* (d) break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set.* if (b), (c), and (d) checks are passed, the receive data is stored in scfrdr. note: * reception continues even when a parity error or framing error occurs. 4. if the rie bit in scscr is set to 1 when th e rdf or dr flag change s to 1, a receive-fifo- data-full interrupt (rxi) request is generated. if the rie bit or reie bit in scs cr is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit or reie bit in scscr is set to 1 when the brk or orer flag changes to 1, a break reception interrupt (br i) request is generated. figure 21.13 shows an example of the operation for reception in asynchronous mode.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 782 of 1286 rej09b0158-0100 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdf fer detect flaming error serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler eri interrupt request generated by receive error figure 21.13 sample sc if receive operation (example with 8-bit data, parity, one stop bit) 5. when modem control is enabled, the scif0_rts signal is output when scfrdr is empty. when scif0_rts is 0, reception is possible. when scif0_rts is 1, this indicates that scfrdr contains bytes of data equal to or more than the scif0_rts output active trigger number. the scif0_rts output active trigger value is specified by bits 10 to 8 in the fifo control register (scfcr). for details, see section 21.3.9, fifo control register n (scfcr). in addition, scif0_rts is also 1 when the re bit in scscr is cleared to 0. figure 21.14 shows an example of the operation when modem control is used. d0 d1 d2 d7 0/1 1 0 0 serial data scif_rxd scif0_rts start bit parity bit stop bit start bit figure 21.14 sample operation using modem control ( scif0_rts ) (only in channel 0)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 783 of 1286 rej09b0158-0100 21.4.3 operation in cl ocked synchronous mode clocked synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. since the transmitter and receiver are independent units in the scif, full-duplex communication can be achieved by sharing the clock. both th e transmitter and receiver have a 64-stage fifo buffer structure, so that data can be read or written during transmission or reception, enabling continuous data tran sfer and reception. figure 21.15 shows the general format for clocked synchronous communication. don't care don't care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 21.15 data format in clocked synchronous communication in clocked synchronous serial communication, data on the communication line is output from one fall of the synchronization clock to the next fall. data is guaranteed to be accurate at the start of the synchronization clock. in serial communication, each char acter is output starting with th e lsb and ending with the msb. after the msb is output, the communication line remains in the state of the last data. in clocked synchronous mode, the scif receives data in synchronization with the rise of the synchronization clock. (1) data transfer format a fixed 8-bit data format is used. no parity bit can be added.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 784 of 1286 rej09b0158-0100 (2) clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the scif_sck pin can be selected as the scif's serial clock, according to the settings of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. for details of scif clock source selection, see table 17.5. when the scif is operated on an internal clock, the synchronization clock is output from the scif_sck pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when an internal clock is selected in a receive operation only, as long as the re bit in scscr is set to 1, clock pulses are output until the number of receive data bytes in the receive fifo data register r eaches the receive trigger number. (3) scif initialization (clocked synchronous mode): before transmitting and receiving data, it is necessa ry to clear the te and re bits in scscr to 0, then initialize the scif as described below. when changing the operating mode or transfer form at, etc., the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, sctsr is initialized. note that clearing the re bit to 0 does not initialize the rdf, per, fer, or orer flag state or change the contents of scfrdr. figure 21.16 shows a sample scif initialization flowchart.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 785 of 1286 rej09b0158-0100 start of initialization clear te and re bits in scscr to 0 set tfcl and rfcl bits in scfcr to 1 to clear the fifo buffer after reading brk, dr, and er flags in scfsr, write 0 to clear them set cke1 and cke0 bits in scscr (leaving te, re, tie, and rie bits cleared to 0) set data transfer format in scsmr set value in scbrr 1-bit interval elapsed? set rtrg1-0 and ttrg1-0 bits in scfcr, and clear tfcl and rfcl bits to 0 set te and re bits in scscr to 1, and set tie, rie, and reie bits set external pins to be used (scif_sck, scif_txd, and scif_rxd) end of initialization wait no yes leave the te and re bits cleared to 0 until the initialization almost ends. be sure to clear the tie, rie, te, and re bits to 0. set the cke1 and cke0 bits. set the data transfer format in scsmr. write a value corresponding to the bit rate into scbrr. this is not necessary if an external clock is used. wait at least one bit interval after this write before moving to the next step. set the external pins to be used. set scif_rxd input for reception and scif_txd output for transmission. the input/output of the scif_sck pin must match the setting of the cke1 and cke0 bits. set the te or re bit in scscr to 1. also set the tie, rie, and reie bits to enable the scif_txd, scif_rxd, and scif_sck pins to be used. when transmitting, the scif_txd pin will go to the mark state. when receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the scif_sck pin at this point. [1] [1] [2] [3] [4] [5] [6] [2] [3] [4] [5] [6] figure 21.16 sample scif initialization flowchart
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 786 of 1286 rej09b0158-0100 (4) serial data transmission (clocked synchronous mode) figure 21.17 shows a sample flowchart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. start of transmission read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr and clear tdfe flag and tend flag in scfsr to 0 all data transmitted? read tend flag in scfsr tend = 1? clear te bit in scscr to 0 end of transmission no yes no yes no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr, and clear the tdfe flag to 0. the transition of the tdfe flag from 0 to 1 can also be identified by a txi interrupt. [2] serial transmission continuation procedeure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, them write data to scftdr, and then clear the tdfe flag to 0. [2] [1] figure 21.17 sample serial transmission flowchart in serial transmission, the scif operates as described below. 1. when data is written into scftdr, the scif transfers the data from scftdr to sctsr and starts transmitting. confirm that the tdfe flag in scfsr is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is at least 64 (transmit trigger setting).
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 787 of 1286 rej09b0158-0100 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls to or below the transmit trigger number set in scfcr, the tdfe flag is set. if the tie bit in scscr is set to 1 at this time, a transmit-fifo- data-empty interrupt (txi) request is generated. if clock output mode is selected, the scif outputs eight synchronization clock pulses for each data. when the external clock is selected, data is output in synchronization with the input clock. the serial transmit data is sent from the scif_txd pin in the lsb-first order. 3. the scif checks the scftdr transmit data at th e timing for sending the last bit. if data is present, the data is transferre d from scftdr to sctsr, and th en serial transmission of the next frame is started. if there is no transmit da ta, the tend flag in scfsr is set to 1 after the last bit is sent, and the transmit data pin (scif_tx d pin) retains the output state of the last bit. 4. after serial transmission ends, the scif_sck pin is fixed high when the cke1 bit in scscr is 0. figure 21.18 shows an example of the operation for transmission in clocked synchronous mode. synchronization clock serial data tdfe tend data written to scftdr and tdfe flag cleared to 0 by txi interrupt handler one frame bit 0 lsb txi interrupt request msb bit 1 bit 6 bit 7 bit 7 bit 0 bit 1 txi interrupt request figure 21.18 sample scif transmission operation in clocked synchronous mode
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 788 of 1286 rej09b0158-0100 (5) serial data reception (clocked synchronous mode) figure 21.19 shows a sample flowchart fo r serial reception. use the following procedure for serial data r eception after enab ling the scif for reception. when switching the operating mode from asynchronous mode to clocked synchronous mode without initializing the scif, make sure that the orer, per7 to per0, and fer7 to fer0 flags are cleared to 0. start of reception read orer flag in sclsr orer = 1? read rdf flag in scfsr rdf = 1? read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? clear re bit in scscr to 0 end of reception ye s no ye s ye s no no error handling [1] receive error handling: read the orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the orer flag to 0. transmission/reception cannot be resumed while the orer flag is set to 1. [2] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, and clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [3] serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading scfrdr. [1] [3] [2] figure 21.19 sample serial reception flowchart (1)
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 789 of 1286 rej09b0158-0100 error handling clear orer flag in sclsr to 0 end overrun error handling orer = 1? yes no figure 21.19 sample serial reception flowchart (2) in serial reception, the scif operates as described below. 1. the scif is initialized internally in synchronization with the input or output of the synchronization clock. 2. the received data is stored in scrsr in lsb-to-msb order. after receiving the data, the scif checks whethe r the receive data can be transferred from scrsr to scfrdr. if this check is passed, th e receive data is stored in scfrdr. if an overrun error is detected in the error check, reception cannot continue. 3. if the rie bit in scscr is set to 1 when the rdf flag changes to 1, a receive-fi fo-data-full interrupt (rxi) request is generated. if the rie bit in scscr is set to 1 when the or er flag changes to 1, a break interrupt (bri) request is generated. figure 21.20 shows an exampl e of the operation for reception in clocked synchronous mode.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 790 of 1286 rej09b0158-0100 synchronization clock serial data rdf orer data read from scfrdr and rdf flag cleared to 0 by rxi interrupt handler one fr ame bit 7 lsb rxi interrupt request msb bit 0 bit 6 bit 7 bit 7 bit 0 bit 1 rxi interr upt bri interrupt request by overrun error figure 21.20 sample scif reception operation in clocke d synchronous mode
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 791 of 1286 rej09b0158-0100 (6) simultaneous serial data transmission and reception (clock ed synchronous mode) figure 21.21 shows a sample flowchart for simulta neous serial data transmission and reception. use the following procedure for si multaneous serial transmission and reception after enabling the scif for both transm ission and reception. start of transmission and reception read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr, and clear tdfe flag in scfsr to 0 read orer flag in sclsr orer = 1? read rdf flag in scfsr rdf = 1? clear te and re bits in scscr to 0 end of transmission and reception read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? no no yes no no yes yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr, and clear the tdfe flag to 0. the transition of the tdfe flag from 0 to 1 can also be identified by a txi interrupt. [2] receive error handling: read the orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the orer flag to 0. transmission/reception cannot be resumed while the orer flag is set to 1. [3] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, and clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [4] serial transmission and reception continuation procedure: to continue serial transmission and reception, read 1 from the rdf flag and the receive data in scfrdr, and clear the rdf flag to 0 before receiving the msb in the current frame. similarly, read 1 from the tdfe flag to confirm that writing is possible before transmitting the msb in the current frame. then write data to scftdr and clear the tdfe flag to 0. [2] [1] yes error handling [3] [4] when switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the te and re bits to 0, and then set them simultaneously to 1. note: figure 21.21 sample simultaneous seri al transmission and reception flowchart
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 792 of 1286 rej09b0158-0100 21.5 scif interrupt sources and the dmac the scif has four interrupt sources in each channel: transmit-fifo-data-empty interrupt (txi) request, receive-error interrupt (eri) request, receive-fifo-data-fu ll interrupt (rxi) request, and break interrupt (bri) request. table 21.7 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie, rie, and reie bits in scscr. a separate interrupt request is sent to the interrupt contro ller for each of these interrupt sources. if the tdfe flag in scfsr is set to 1 when a txi interrupt is enabled by the tie bit, a txi interrupt request and a transmit-fifo-data-empty request for dma transfer are generated. if the tdfe flag is set to 1 when a txi interrupt is di sabled by the tie bit, only a transmit-fifo-data- empty request for dma transfer is generated. a transmit-fifo-data-empt y request can activate the dmac to perform data transfer. if the rdf or dr flag in scfsr is set to 1 when an rxi interrupt is enabled by the rie bit, an rxi interrupt request and a receive-fifo-data-full request for dma transfer are generated. if the rdf or dr flag is set to 1 when an rxi interrupt is disabled by the rie bit, only a receive-fifo- data-full request for dma transfer is generated. a receive-fifo-data-full request can activate the dmac to perform data transfer. note that genera tion of an rxi interrupt request or a receive- fifo-data-full request by setting the dr flag to 1 occurs only in asynchronous mode. when the brk flag in scfsr or the orer flag in sclsr is set to 1, a bri interrupt request is generated. if transmission/reception is carried out using the dmac, set and enable the dmac before making the scif settings. also make setti ngs to inhibit output of rxi and txi interrupt requests to the interrupt controller. if output of interrupt requests is enabled, these interrupt requests to the interrupt controller can be cleared by the dmac regardless of the interrupt handler. by setting the reie bit to 1 while the rie bit is cleared to 0 in scscr, it is possible to output eri interrupt requests, but not rxi interrupt requests.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 793 of 1286 rej09b0158-0100 table 21.8 scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) not possible high rxi interrupt initiated by receive fifo data full flag (rdf) or receive data ready flag (dr) * possible bri interrupt initiated by break flag (brk) or overrun error flag (orer) not possible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low note: * an rxi interrupt by setting of the dr flag is available only in asynchronous mode.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 794 of 1286 rej09b0158-0100 21.6 usage notes note the following when using the scif. (1) scftdr writing and the tdfe flag the tdfe flag in scfsr is set when the number of transmit data bytes written in scftdr has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in scfcr. after tdfe is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 agai n, even after being read as 1 and cleared to 0. tdfe clearing should therefore be carried out when scftdr contains more than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr can be found from sctfdr. (2) scfrdr reading and the rdf flag the rdf flag in scfsr is set when the number of receive data bytes in scfrdr has become equal to or greater than the receive trigger nu mber set by bits rtrg1 and rtrg0 in scfcr. after rdf is set, receive data equivalent to the trigger number can be read from scfrdr, allowing efficient co ntinuous reception. however, if the number of data bytes read in scfrdr is equal to or greater than the trigger number, the rdf flag will be set to 1 again even if it is cleared to 0. after the receive data is read, clear the rdf flag readout to 0 in order to reduce the number of data bytes in scfrdr to less than the trigger number. the number of receive da ta bytes in scfrdr can be found from scrfdr. (3) break detection and processing if a framing error (fer) is detected , break signals can also be det ected by reading the scif_rxd pin value directly. in the break state the input from the scif_rxd pin consists of all 0s, so the fer flag is set and the parity er ror flag (per) may also be set. although the scif stops tr ansferring receive data to scfrdr after receiving a break, the receive operation continues.
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 795 of 1286 rej09b0158-0100 (4) sending a break signal the input/output condition and level of the scif_txd pin are determined by bits spb2io and spb2dt in scsptr. this feature can be used to send a break signal. after the serial transmitter is initialized and until th e te bit is set to 1 (enabling transmission), the scif_txd pin function is not selected and the value of the spb2dt bit substitutes for the mark state. the spb2io and spb2dt bits should therefore be set to 1 (designating output and high level) in the beginning. to send a break signal during serial transmissi on, clear the spb2dt bit to 0 (designating low level), and then clear the te bit to 0 (halting tran smission). when the te bit is cleared to 0, the transmitter is initialized, regardless of the current transmission state, and 0 is output from the scif_txd pin. (5) receive data sampling timing and receive margin in asynchronous mode in asynchronous mode, the scif operates on a base clock with a frequency of 16 times the bit rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 21.22. 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (scif_rxd) start bit ?7.5 clocks +7.5 clocks synchronization sampling timing data sampling timing figure 21.22 receive data sampling timing in asynchronous mode
section 21 serial communication interface with fifo (scif) rev.1.00 dec. 13, 2005 page 796 of 1286 rej09b0158-0100 thus, the reception margin in asynchrono us mode is given by formula (1). 1 | d - 0.5 | m= (0.5 - 2n ) - (l - 0.5) f - n (1 + f) 100 % .................. (1) m: receive margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation from equation (1), if f = 0 and d = 0.5, the receptio n margin is 46.875%, as given by formula (2). when d = 0.5 and f = 0: m = (0.5 ? 1 / (2 16) ) 100% = 46.875% ............................................... (2) however, this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. (6) when using dmac to update scft dr in external clock synchronizing when using an external clock as the synchronization clock, after scftdr is updated by the dmac, an external clock should be input after at least five peripheral clock (pck) cycles. a malfunction may occur when the tran sfer clock is input within four cycles after updating scftdr (see figure 21.23). scif_sck tdfe flag scif_txd note: when the scif is operated on an external clock, set t to ensure 5 pck clock cycles or more. d0 d1 d2 d6 d7 d3 d4 d5 t figure 21.23 example of synchronization clock transfer by dmac
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 797 of 1286 rej09b0158-0100 section 22 serial i/o with fifo (siof) this lsi includes a clock-synchronized serial i/o module with fifo (siof). 22.1 features ? ? ? ?
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 798 of 1286 rej09b0158-0100 figure 22.1 shows a block diagram of the siof. p/s s/p pck 1/nmclk siof_mclk siof_sck siof_sync siof_txd siof_rxd timing control siof interrupt request (siofi) peripheral bus bus interface control registers transmit fifo (32 bits 16 stages) receive fifo (32 bits 16 stages) transmit control data receive control data baud rate generator dma transfer request figure 22.1 block diagram of siof
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 799 of 1286 rej09b0158-0100 22.2 input/output pins the pin configuration in this module is shown in table 22.1. table 22.1 pin configuration pin name function i/o description siof_mclk master clock input master clock input pin siof_sck serial clock i/o se rial clock pin (common to transmission/reception) siof_sync frame synchronous signal i/o frame synchronous signal (common to transmission/reception) siof_txd transmit data output transmit data pin siof_rxd receive data input receive data pin note: these pins are multiplexed with hac, ssi and gpio pins.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 800 of 1286 rej09b0158-0100 22.3 register descriptions table 22.2 shows the siof register configurati on. table 22.3 shows the register states in each processing mode. table 22.2 register co nfiguration of siof name abbreviation r/w p4 address area7 address access size sync clock mode register simdr r/w h 'ffe2 0000 h'1fe2 0000 16 pck clock select register siscr r/ w h'ffe2 0002 h'1fe2 0002 16 pck transmit data assign register sitdar r/w h'ffe2 0004 h'1fe2 0004 16 pck receive data assign regi ster sirdar r/w h'ffe2 0006 h'1fe2 0006 16 pck control data assign register sicda r r/w h'ffe2 0008 h'1fe2 0008 16 pck control register sictr r/w h'ffe2 000c h'1fe2 000c 16 pck fifo control register sifctr r/w h'ffe2 0010 h'1fe2 0010 16 pck status register sistr r/w h'ffe2 0014 h'1fe2 0014 16 pck interrupt enable register siier r/w h'ffe2 0016 h'1fe2 0016 16 pck transmit data register sitdr w h'ffe2 0020 h'1fe2 0020 32 pck receive data register sirdr r h'ffe2 0024 h'1fe2 0024 32 pck transmit control data register sit cr r/w h'ffe2 0028 h'1fe2 0028 32 pck receive control data register si rcr r/w h'ffe2 002c h'1fe2 002c 32 pck
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 801 of 1286 rej09b0158-0100 table 22.3 register states of si of in each processing mode name abbreviation power-on reset by preset pin/wdt/ h-udi manual reset by wdt/multiple exceptions sleep by sleep instruction module standby mode register simdr h'8000 h'8000 retained retained clock select register siscr h'c000 h'c000 retained retained transmit data assign register sitdar h'0000 h'0000 retained retained receive data assign register sirdar h'0000 h'0000 retained retained control data assign register sicdar h'0000 h'0000 retained retained control register sictr h'0000 h'0000 retained retained fifo control register sifctr h'1000 h'1000 retained retained status register sistr h'0000 h'0000 retained retained interrupt enable register siier h'0000 h'0000 retained retained transmit data register sitdr h'xxxx xxxx h'xxxx xxxx retained retained receive data register sirdr h'xxxx xxxx h'xxxx xxxx retained retained transmit control data register sitcr h'0000 0000 h'0000 0000 retained retained receive control data register sircr h'xxxx xxxx h'xxxx xxxx retained retained [legend] x: undefined
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 802 of 1286 rej09b0158-0100 22.3.1 mode re gister (simdr) simdr is a 16-bit readable/writable regist er that sets the siof operating mode. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ? ? ? ? syn cdl syn cac rcim txdiz fl[3:0] redg syn cat trmd[1:0] r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15, 14 trmd[1:0] 10 r/w transfer mode 1, 0 select transfer mode as shown in table 22.4. 00: slave mode 1 01: slave mode 2 10: master mode 1 11: master mode 2 13 syncat 0 r/w siof_sync pin valid timing indicates the position of the siof_sync signal to be output as a synchronization pulse. 0: at the start-bit data of frame 1: at the last-bit data of slot 12 redg 0 r/w receive data sampling edge 0: the siof_rxd signal is sampled at the falling edge of siof_sck 1: the siof_rxd signal is sampled at the rising edge of siof_sck note: the timing to transmit the siof_txd signal is at the opposite edge of the timing that samples the siof_rxd. this bit is valid only in master mode. 11 to 8 fl[3:0] 0000 r/w frame length 3 to 0 specify the flame length and transfer data format. for details, refer to table 22.7.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 803 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 txdiz 0 r/w siof_txd pin output when transmission is invalid * 0: high output (1 output) when invalid 1: high-impedance state when invalid note: invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 rcim 0 r/w receive control data interrupt mode 0: sets the rcrdy bit in sistr when the contents of sircr change. 1: sets the rcrdy bit in sistr each time when the sircr receives the control data. 5 syncac 0 r/w siof_sync pin polarity valid when the siof_sync signal is output as a synchronous pulse. 0: active-high 1: active-low 4 syncdl 0 r/w data pin bit delay for siof_sync pin valid when the siof_sync signal is output as synchronous pulse. only one-bit delay is valid for transmission in slave mode. 0: no bit delay 1: 1-bit delay 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 804 of 1286 rej09b0158-0100 table 22.4 shows the operatio n in each transfer mode. table 22.4 operation in each transfer mode transfer mode master/slave siof_ sync bit delay control data method * slave mode 1 slave synchronous pulse slot position slave mode 2 slave synchronous pulse secondary fs master mode 1 master synchronous pulse syncdl bit slot position master mode 2 master l/r no not supported note: * the control data method is valid only when t he fl bits are specified as b'1xxx. (x: don't care) 22.3.2 clock select register (siscr) siscr is a 16-bit readable/writable register that se ts the serial clock generation conditions for the master clock. siscr can be specified when the bits trmd[1:0] in simdr are specified as b'10 or b'11. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 brdv[2:0] ? ? ? ? ? brps[4:0] ? mssel msimm r/w r/w r/w r r r r r r/w r/w r/w r/w r/w r r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 mssel 1 r/w master clock source selection the master clock is the clock source input to the baud rate generator (prescaler). 0: uses the input clock signal of the siof_mclk pin as the master clock 1: uses peripheral clock (pck) as the master clock 14 msimm 1 r/w master clock direct selection 0: uses the output clock of the baud rate generator as the serial clock 1: uses the master clock itself as the serial clock 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 805 of 1286 rej09b0158-0100 bit bit name initial value r/w description 12 to 8 brps[4:0] 00000 r/w prescalar setting set the master clock division ratio according to the count value of the prescala r of the baud rate generator. the range of settings is from 00000 ( 1/1) to 11111 ( 1/32). 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 brdv[2:0] 000 r/w baud rate generator's division ratio setting set the frequency division ratio for the output stage of the baud rate generator. 000: prescalar output 1/2 001: prescalar output 1/4 010: prescalar output 1/8 011: prescalar output 1/16 100: prescalar output 1/32 101: setting prohibited 110: setting prohibited 111: prescalar output 1/1 ? setting 111 is valid only when the bits brps[4:0] are set to 00001. the frequency division ratio of the baud rate generator is finally determined by the value of brps by brdv (maximum 1/1024).
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 806 of 1286 rej09b0158-0100 22.3.3 control register (sictr) sictr is a 16-bit readable/writable register that sets the siof operating state. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rxrst txrst ? ? ? ? ? ? rxe txe ? ? ? ? scke fse r/w r/w r r r r r r r/w r/w r r r r r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 scke 0 r/w serial clock output enable this bit is valid in master mode. 0: disables the siof_sck output (outputs 0) 1: enables the siof_sck output if this bit is set to 1, the siof initializes the baud rate generator and initiates the op eration. at the same time, the siof outputs the clock ge nerated by the baud rate generator to the siof_sck pin. 14 fse 0 r/w frame synchrono us signal output enable this bit is valid in master mode. 0: disables the siof_sync output (outputs 0) 1: enables the siof_sync output if this bit is set to 1, the siof initializes the frame counter and initiates the operation. 13 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 807 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9 txe 0 r/w transmit enable 0: disables data transmission from the siof_txd pin 1: enables data transmission from the siof_txd pin ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siof_sync signal). ? when the 1 setting for this bit becomes valid, the siof issues a transmit transfer request according to the setting of the tfwm bit in sifctr. when transmit data is stored in the transmit fifo, transmission of data from the siof_txd pin begins. this bit is initialized upon a transmit reset. 8 rxe 0 r/w receive enable 0: disables data reception from siof_rxd 1: enables data reception from siof_rxd ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siof_sync signal). ? when the 1 setting for this bit becomes valid, the siof begins the recept ion of data from the siof_rxd pin. when receive data is stored in the receive fifo, the siof issues a reception transfer request according to the setting of the rfwm bit in sifctr. this bit is initialized upon receive reset. 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 808 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 txrst 0 r/w transmit reset 0: does not reset transmit operation 1: resets transmit operation ? this bit setting becomes valid immediately. for details of transmit reset, refer to table 22.13. ? siof automatically clears this bit upon the completion of reset. thus, this bit is always read as 0. 0 rxrst 0 r/w receive reset 0: does not reset receive operation 1: resets receive operation ? this bit setting becomes valid immediately. for details of receive reset, refer to table 22.13. ? siof automatically clears this bit upon the completion of reset. thus, this bit is always read as 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 809 of 1286 rej09b0158-0100 22.3.4 transmit data register (sitdr) sitdr is a 32-bit write-only register th at specifies the siof operating status. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sitdl[15:0] w w w w w w w w w w w w w w ww w w w w w w w w w w w w w w ww bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sitdr[15:0] bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 sitdl[15:0] undefined w left-channel transmit data specify data to be output fr om the siof_txd pin as left-channel data. the positio n of the left-channel data in the transmit frame is specified by the tdla bit in sitdar. ? these bits are valid only when the tdle bit in sitdar is set to 1. 15 to 0 sitdr[15:0] undefined w right-channel transmit data specify data to be output fr om the siof_txd pin as right-channel data. the pos ition of the right-channel data in the transmit frame is specified by the tdra bit in sitdar. ? these bits are valid only when the tdre bit and tlrep bit in sitdar are set to 1 and cleared to 0, respectively.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 810 of 1286 rej09b0158-0100 22.3.5 receive data register (sirdr) sirdr is a 32-bit read-only register that reads recei ve data of the siof. si rdr stores data in the receive fifo. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sirdl[15:0] r r r r r r r r r r r r r r rr r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sirdr[15:0] bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 sirdl[15:0] undefined r left-channel receive data store data received from the siof_rxd pin as left- channel data. the position of the left-channel data in the receive frame is specified by the rdla bit in sirdar. ? these bits are valid only when the rdle bit in sirdar is set to 1. 15 to 0 sirdr[15:0] undefined r right-channel receive data store data received from t he siof_rxd pin as right- channel data. the position of the right-channel data in the receive frame is specified by the rdra bit in sirdar. ? these bits are valid only when the rdre bit in sirdar is set to 1.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 811 of 1286 rej09b0158-0100 22.3.6 transmit control data register (sitcr) sitcr is a 32-bit readable/writable register that specifies transmit control data of the siof. sitcr can be specified only when the fl bits in simdr are specified as b'1xxx (x: don't care). sitcr is initialized by the conditions specified in table 22.3, register state of siof in each processing mode, or by a transmit rese t caused by the txrst bit in sictr. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sitc0[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sitc1[15:0] bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 sitc0[15:0] h'0000 r/w c ontrol channel 0 transmit data specify data to be output fr om the siof_txd pin as control channel 0 transmit data. the position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sitc1[15:0] h'0000 r/w c ontrol channel 1 transmit data specify data to be output fr om the siof_txd pin as control channel 1 transmit data. the position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 812 of 1286 rej09b0158-0100 22.3.7 receive control data register (sircr) sircr is a 32-bit readable/writable register that stores receive control data of the siof. sircr can be specified only when the fl bits in si mdr are specified as b' 1xxx (x: don't care). 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sirc0[15:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? sirc1[15:0] bit: initial value: r/w: bit bit name initial value r/w description 31 to 16 sirc0[15:0] undefined r/w control channel 0 receive data store data received from the siof_rxd pin as control channel 0 receive data. t he position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sirc1[15:0] undefined r/w control channel 1 receive data store data received from the siof_rxd pin as control channel 1 receive data. t he position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 813 of 1286 rej09b0158-0100 22.3.8 status register (sistr) sistr is a 16-bit readable/writable register that sh ows the siof state. each bit in this register becomes an siof interrupt source when the corresponding bit in siier is set to 1. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rfovf rfudf tfudf tfovf fserr saerr ? ? rdreq rfful rcrdy ? tdreq tfemp ? tcrdy r/w r/w r/w r/w r/w r/w r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 tcrdy 0 r transmit control data ready 0: indicates that a write to sitcr is disabled 1: indicates that a write to sitcr is enabled ? if sitcr is written when this bit is cleared to 0, sitcr is over-written and th e previous contents of sitcr are not output from the siof_txd pin. ? this bit is valid when the txe bit in sitcr is set to 1. ? this bit indicates a state of the siof. if sitcr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 13 tfemp 0 r transmit fifo empty 0: indicates that transmit fifo is not empty 1: indicates that transmit fifo is empty ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if sitdr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 814 of 1286 rej09b0158-0100 bit bit name initial value r/w description 12 tdreq 0 r transmit data transfer request 0: indicates that the size of empty space in the transmit fifo does not exceed the size specified by the tfwm bit in sifctr. 1: indicates that the size of empty space in the transmit fifo exceeds the size specified by the tfwm bit in sifctr. a transmit data transfer request is issued when the empty space in the transmit fifo exceeds the size specified by the tfwm bit in sifctr. when using transmit data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if the size of empty space in the transmit fifo is less than the size specified by the tfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 rcrdy 0 r receive control data ready 0: indicates that the sircr stores no valid data. 1: indicates that the sircr stores valid data. ? if sircr is written when this bit is set to 1, sircr is modified by the latest data. ? this bit is valid when the rxe bit in sictr is set to 1. ? this bit indicates a state of the siof. if sircr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 815 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9 rfful 0 r receive fifo full 0: receive fifo not full 1: receive fifo full ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if sirdr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 8 rdreq 0 r receive data transfer request 0: indicates that the size of valid space in the receive fifo does not exceed the size specified by the rfwm bit in sifctr. 1: indicates that the size of valid space in the receive fifo exceeds the size specified by the rfwm bit in sifctr. a receive data transfer request is issued when the valid data space in the receive fifo exceeds the size specified by the rfwm bit in sifctr. when using receive data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if the size of valid data space in the receive fifo is less than the size specified by the rfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 816 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 saerr 0 r/w slot assign error 0: indicates that no slot assign error occurs 1: indicates that a slot assign error occurs a slot assign error occurs when the specifications in sitdar, sirdar, and sicdar overlap. if a slot assign error occurs, the siof does not transmit data to the siof_txd pin and does not receive data from the siof_rxd pin. note that the siof does not clear the txe bit or rxe bit in sictr at a slot assign error. ? this bit is valid when the txe bit or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 4 fserr 0 r/w frame synchronization error 0: indicates that no frame synchronization error occurs 1: indicates that a frame synchronization error occurs a frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. if a frame synchronization error occurs, the siof performs transmission or reception for slots that can be transferred. ? this bit is valid when the txe or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 817 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 tfovf 0 r/w transmit fifo overflow 0: no transmit fifo overflow 1: transmit fifo overflow a transmit fifo overflow means that there has been an attempt to write to sitdr when the transmit fifo is full. when a transmit fifo overflow occurs, the siof indicates overflow, and writing is invalid. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 2 tfudf 0 r/w transmit fifo underflow 0: no transmit fifo underflow 1: transmit fifo underflow a transmit fifo underflow means that loading for transmission has occurred when the transmit fifo is empty. when a transmit fifo underflow occurs, the siof repeatedly sends the previous transmit data. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 818 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 rfudf 0 r/w receive fifo underflow 0: no receive fifo underflow 1: receive fifo underflow a receive fifo underflow means that reading of sirdr has occurred when the receive fifo is empty. when a receive fifo underflow occurs, the value of data read from sirdr is not guaranteed. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 0 rfovf 0 r/w receive fifo overflow 0: no receive fifo overflow 1: receive fifo overflow a receive fifo overflow means that writing has occurred when the receive fifo is full. when a receive fifo overflow occurs, the siof indicates overflow, and receive data is lost. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 819 of 1286 rej09b0158-0100 22.3.9 interrupt enab le register (siier) siier is a 16-bit readable/writable register that enables the issue of siof interrupts. when each interrupt enable bit in this register is set to 1 and the corresponding bit in sistr is set to 1, the siof issues an interrupt. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rf ovfe rf udfe tf udfe tf ovfe fs erre sa erre ? ? rd reqe rf fule rc rdye rd mae tdr eqe tfe mpe td mae tcr dye r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 tdmae 0 r/w transmit data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the tdreqe bit can be set as transmit interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac 14 tcrdye 0 r/w transmit control data ready enable 0: disables interrupts due to transmit control data ready 1: enables interrupts due to transmit control data ready 13 tfempe 0 r/w transmit fifo empty enable 0: disables interrupts due to transmit fifo empty 1: enables interrupts due to transmit fifo empty 12 tdreqe 0 r/w transmit data transfer request enable 0: disables interrupts due to transmit data transfer requests 1: enables interrupts due to transmit data transfer requests 11 rdmae 0 r/w receive data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the rdreqe bit can be set as receive interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 820 of 1286 rej09b0158-0100 bit bit name initial value r/w description 10 rcrdye 0 r/w receive control data ready enable 0: disables interrupts due to receive control data ready 1: enables interrupts due to receive control data ready 9 rffule 0 r/w receive fifo full enable 0: disables interrupts due to receive fifo full 1: enables interrupts due to receive fifo full 8 rdreqe 0 r/w receive data transfer request enable 0: disables interrupts due to receive data transfer requests 1: enables interrupts due to receive data transfer requests 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 saerre 0 r/w slot assign error enable 0: disables interrupts due to slot assign error 1: enables interrupts due to slot assign error 4 fserre 0 r/w frame synchronization error enable 0: disables interrupts due to frame synchronization error 1: enables interrupts due to frame synchronization error 3 tfovfe 0 r/w transmit fifo overflow enable 0: disables interrupts due to transmit fifo overflow 1: enables interrupts due to transmit fifo overflow 2 tfudfe 0 r/w transmit fifo underflow enable 0: disables interrupts due to transmit fifo underflow 1: enables interrupts due to transmit fifo underflow 1 rfudfe 0 r/w receive fifo underflow enable 0: disables interrupts due to receive fifo underflow 1: enables interrupts due to receive fifo underflow 0 rfovfe 0 r/w receive fifo overflow enable 0: disables interrupts due to receive fifo overflow 1: enables interrupts due to receive fifo overflow
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 821 of 1286 rej09b0158-0100 22.3.10 fifo control register (sifctr) sifctr is a 16-bit readable/writable register that indicates the area available for the transmit/receive fifo transfer. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00 rfua[4:0] rfwm[2:0] tfua[4:0] tfwm[2:0] r r r r r r/w r/w r/w r r r r r r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 to 13 tfwm[2:0] 000 r/w transmit fifo watermark 000: issue a transfer request when 16 stages of the transmit fifo are empty. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 12 or more stages of the transmit fifo are empty. 101: issue a transfer request when 8 or more stages of the transmit fifo are empty. 110: issue a transfer request when 4 or more stages of the transmit fifo are empty. 111: issue a transfer request when 1 or more stages of transmit fifo are empty. ? a transfer request to the transmit fifo is issued by the tdreqe bit in sistr. ? the transmit fifo is always used as 16 stages of the fifo regardless of these bit settings. 12 to 8 tfua[4:0] 10000 r transmit fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as 00000 (full) to 10000 (empty).
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 822 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 to 5 rfwm[2:0] 000 r/w receive fifo watermark 000: issue a transfer request when 1 stage or more of the receive fifo are valid. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 4 or more stages of the receive fifo are valid. 101: issue a transfer request when 8 or more stages of the receive fifo are valid. 110: issue a transfer request when 12 or more stages of the receive fifo are valid. 111: issue a transfer request when 16 stages of the receive fifo are valid. ? a transfer request to the receive fifo is issued by the rdreqe bit in sistr. ? the receive fifo is always used as 16 stages of the fifo regardless of these bit settings. 4 to 0 rfua[4:0] 00000 r receive fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as 00000 (empty) to 10000 (full).
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 823 of 1286 rej09b0158-0100 22.3.11 transmit data a ssign register (sitdar) sitdar is a 16-bit readable/writable register that specifies the position of the transmit data in a frame. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 tdra[3:0] ? ? tlrep tdre tdla[3:0] ? tdle ? r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r r r/w r bit: initial value: r/w: ? bit bit name initial value r/w description 15 tdle 0 r/w transmit left-channel data enable 0: disables left-channel data transmission 1: enables left-channel data transmission 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 8 tdla[3:0] 0000 r/w transmit left-channel data assigns 3 to 0 specify the position of left-channel data in a transmit frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? transmit data for the left channel is specified in the sitdl bit in sitdr. 7 tdre 0 r/w transmit right-channel data enable 0: disables right-channel data transmission 1: enables right-channel data transmission 6 tlrep 0 r/w transmit left-channel repeat 0: transmits data specified in the sitdr bit in sitdr as right-channel data 1: repeatedly transmits data specified in the sitdl bit in sitdr as right-channel data ? this bit setting is valid when the tdre bit is set to 1. ? when this bit is set to 1, the sitdr settings are ignored.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 824 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 to 0 tdra[3:0] 0000 r/w transmit right-channel data assigns 3 to 0 specify the position of right-channel data in a transmit frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? transmit data for the right channel is specified in the sitdr bit in sitdr. 22.3.12 receive data a ssign register (sirdar) sirdar is a 16-bit readable/writable register that specifies the position of the receive data in a frame. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 rdra[3:0] ? ? ? rdre rdla[3:0] ? rdle ? r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w r r r/w r bit: initial value: r/w: ? bit bit name initial value r/w description 15 rdle 0 r/w receive left-channel data enable 0: disables left-channel data reception 1: enables left-channel data reception 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 8 rdla[3:0] 0000 r/w receive left-channel data assigns 3 to 0 specify the position of left-channel data in a receive frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? receive data for the left channel is stored in the sirdl bit in sirdr.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 825 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 rdre 0 r/w receive right-channel data enable 0: disables right-channel data reception 1: enables right-channel data reception 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 to 0 rdra[3:0] 0000 r/w receive right-channel data assigns 3 to 0 specify the position of right-channel data in a receive frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? receive data for the right channel is stored in the sirdr bit in sirdr. 22.3.13 control data assign register (sicdar) sicdar is a 16-bit readable/writable register that specifies the position of the control data in a frame. sicdar can be specified only when the fl bits in si mdr are specified as b'1xxx (x: don't care). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 cd1 a[3:0] ? ? ? cd1e cd0 a[3:0] ? cd0e ? r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w r r r/w r bit: initial value: r/w: ? bit bit name initial value r/w description 15 cd0e 0 r/w control channel 0 data enable 0: disables transmission and reception of control channel 0 data 1: enables transmission and reception of control channel 0 data 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 826 of 1286 rej09b0158-0100 bit bit name initial value r/w description 11 to 8 cd0a[3:0] 0000 r/w control channel 0 data assigns 3 to 0 specify the position of control channel 0 data in a receive or transmit frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? transmit data for the control channel 0 data is specified in the sitd0 bit in sitcr. ? receive data for the control channel 0 data is stored in the sird0 bit in sircr. 7 cd1e 0 r/w control channel 1 data enable 0: disables transmission and reception of control channel 1 data 1: enables transmission and reception of control channel 1 data 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 to 0 cd1a[3:0] 0000 r/w control channel 1 data assigns 3 to 0 specify the position of control channel 1 data in a receive or transmit frame as 0000 (0) to 1110 (14). 1111: setting prohibited ? transmit data for the control channel 1 data is specified in the sitd1 bit in sitcr. ? receive data for the control channel 1 data is stored in the sird1 bit in sircr.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 827 of 1286 rej09b0158-0100 22.4 operation 22.4.1 serial clocks master/slave modes: the following modes are available as the siof clock mode. ? ? scke siof_sck siof_mclk pck divider pre- scalar baud rate generator 1/1 to 1/1024 master clock master clock timing control master figure 22.2 serial clock supply table 22.5 shows an example of serial clock frequency.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 828 of 1286 rej09b0158-0100 table 22.5 siof serial clock frequency sampling rate frame length 8 khz 44.1 khz 48 khz 32 bits 256 khz 1.4112 mhz 1.536 mhz 64 bits 512 khz 2.8224 mhz 3.072 mhz 128 bits 1.024 mhz 5.6448 mhz 6.144 mhz 256 bits 2.048 mhz 11.2896 mhz 12.288 mhz
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 829 of 1286 rej09b0158-0100 22.4.2 serial timing siof_sync : the siof_sync is a frame synchronous signal. depending on the transfer mode, it has the following two functions. ? ? siof_sck siof_rxd siof_txd siof_sync siof_sck siof_rxd siof_txd siof_sync (a) synchronous pulse (b) l/r 1 frame 1 frame start bit data 1-bit delay start bit of left channel data (1/2 frame length) start bit of right channel data (1/2 frame length) no dela y figure 22.3 serial data synchronization timing
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 830 of 1286 rej09b0158-0100 transmit/receive timing: the siof_txd transmit timing and siof_rxd r eceive timing relative to the siof_sck can be set as the sa mpling timing in the following two ways. the transmit/receive timing is set us ing the redg bit in simdr. ? ? siof_sck redg = 0 redg = 1 siof_sync siof_txd siof_rxd siof_sck siof_sync siof_txd siof_rxd (a) falling-edge sampling (a) rising-edge sampling receive timing transmit timing receive timing tr ansmit timing figure 22.4 siof transmit/receive timing 22.4.3 transfer data format the siof performs the following transfer. ? ? trmd[1:0] transfer mode siof _sync bit delay control data * 00 slave mode 1 synchronous pulse slot position 01 slave mode 2 synchronous pulse secondary fs 10 master mode 1 synchronous pulse syncdl bit slot position 11 master mode 2 l/r no not supported note: * the control data method is valid only when the fl bits are specified as b'1xxx (x: don't care).
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 831 of 1286 rej09b0158-0100 frame length: the length of the frame to be transferre d by the siof is specified by the bits fl[3:0] in simdr. table 22.7 shows the relationship between the bits fl[3:0] settings and frame length. table 22.7 frame length fl[3:0] slot length number of bits in a frame transfer data 00xx 8 8 8-bit monaural data 0100 8 16 8-bit monaural data 0101 8 32 8-bit monaural data 0110 8 64 8-bit monaural data 0111 8 128 8-bit monaural data 10xx 16 16 16-bit monaural data 1100 16 32 16-bit monaural stereo data 1101 16 64 16-bit monaural stereo data 1110 16 128 16-bit monaural stereo data 1111 16 256 16-bit monaural stereo data note: x: don't care. slot position: the siof can specify the pos ition of transmit data, receive data, and control data in a frame (common to transmission and reception) by sl ot numbers. the slot number of each data is specified by the following registers. ? ? ?
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 832 of 1286 rej09b0158-0100 22.4.4 register allocation of transfer data transmit/receive data: writing and reading of transmit/r eceive data is performed for the following registers. ? ? 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 l-channel data r-channel data (a) 16-bit stereo data data data data (b) 16-bit monaural data (c) 8-bit monaural data (d) 16-bit stereo data (left and right same audio output) data figure 22.5 transmit/receive data bit alignment note: in the figure, only the sh aded areas are transmitted or r eceived as valid data. therefore, access must be made in byte units for 8-bit data , and in word units for 16-bit data. data in unshaded areas is not tr ansmitted or received. monaural or stereo can be specified for transmit data by the tdle bit and tdre bit in sitdar. monaural or stereo can be specified for receive data by the rdle bit and rdre bit in sirdar. to achieve left and right same audio output while stereo is specified for tr ansmit data, specify the tlrep bit in sitdar. table 22.8 and table 22.9 show the audi o mode specificat ion for transmit data and that for receive data, respectively.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 833 of 1286 rej09b0158-0100 table 22.8 audio mode specifi cation for transmit data bit mode tdle tdre tlrep monaural 1 0 x stereo 1 1 0 left and right same audio output 1 1 1 note: x: don't care table 22.9 audio mode speci fication for receive data bit mode rdle rdre monaural 1 0 stereo 1 1 note: left and right same audio mode is not supported in receive data. to execute 8-bit monaural transmission or reception, use the left channel. control data: control data is written to or read from by the following registers. ? ? 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 (a) control data: one channel (b) control data: two channels control data (channel 0) control data (channel 0) control data (channel 1) figure 22.6 control data bit alignment
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 834 of 1286 rej09b0158-0100 the number of channels in control data is specified by the cd0e and cd1e bits in sicdar. table 22.10 shows the relationship between the number of channels in control data and bit settings. table 22.10 setting number of channels in control data bit number of channels cd0e cd1e 1 1 0 2 1 1 note: to use only one channel in control data, use channel 0. 22.4.5 control data interface control data performs control command output to the codec and status input from the codec. the siof supports the following tw o control data interface methods. ? ? siof_sck siof_rxd siof_txd siof_sync l-channel data r-channel data specifications: trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0001, fl[3:0] = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra[3:0] = 0010, rdra[3:0] = 0010, cd1a[3:0] = 0011 control channel 0 control channel 1 1 frame slot no.0 slot no.1 slot no.2 slot no.3 figure 22.7 control data interface (slot position)
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 835 of 1286 rej09b0158-0100 control by secondary fs (slave mode 2): the codec normally outputs the siof_sync signal as synchronization pulse (fs). in this method, the codec outputs the secondary fs specific to the control data transfer after 1/2 frame time has been passed (not the normal fs output timing) to transmit or receive control data. th is method is valid for siof slave mode. the following summarizes the co ntrol data interface procedure by the secondary fs. ? ? ? ? siof_sck siof_rxd siof_txd siof_sync l-channel data specifications: trmd[1:0] = 01, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0000, fl[3:0] = 1110 (frame length: 128 bits), tdre = 0, rdre = 0, cd1e = 0, tdra[3:0] = 0000, rdra[3:0] = 0000, cd1a[3:0] = 0000 lsb=1 (secondary fs request) 1 frame 1/2 fr ame 1 /2 fr ame normal fs nor mal fs secondary fs control channel 0 slot no.0 slot no.0 figure 22.8 control data interface (secondary fs)
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 836 of 1286 rej09b0158-0100 22.4.6 fifo overview: the transmit and receive fifos of th e siof have the following features. ? ? ? ? tfwm[2:0] number of requested stages transmit request used areas 000 1 empty area is 16 stages 100 4 empty area is 12 stages or more 101 8 empty area is 8 stages or more 110 12 empty area is 4 stages or more smallest 111 16 empty area is 1 stage or more largest table 22.12 conditions to issue receive request rfwm[2:0] number of requested stages receive request used areas 000 1 valid data is 1 stage or more 100 4 valid data is 4 stages or more 101 8 valid data is 8 stages or more 110 12 valid data is 12 stages or more smallest 111 16 valid data is 16 stages largest
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 837 of 1286 rej09b0158-0100 the number of stages of the fifo is always sixteen even if the data area or empty area exceeds the fifo size (the number of fifos). accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen fifo stages. th e fifo transmit or rece ive request is canceled when the above condition is not satisfied even if the fifo is not empty or full. number of fifos: the number of fifo stages used in transmission and reception is indicated by the following register. ? ?
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 838 of 1286 rej09b0158-0100 22.4.7 transmit and receive procedures transmission in master mode: figure 22.9 shows an example of settings and operation for master mode transmission. start no ye s no ye s end no. 1 2 3 4 5 6 7 8 set simdr, siscr, sitdar, sicdar, sitcr, and sifctr set the scke bit in sictr to 1 start siof_sck output set the fse and txe bits in sictr to 1 tdreq = 1? set sitdr transmit sitdr from siof_txd synchronously with siof_sync transfer ended? clear the txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit data, slot position for control data, control data, and fifo request threshold value set operation start for baud rate generator set the start for frame synchronous signal output and enable transmission set transmit data set to disable transmission output serial clock output frame synchronous signal and issue transmit transfer request * transmit end transmission flow chart siof settings siof operation note: * when interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the txe bit should be set to 1. figure 22.9 example of transmit operation in master mode
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 839 of 1286 rej09b0158-0100 reception in master mode: figure 22.10 shows an example of settings and operation for master mode reception. start no ye s no ye s end no. 1 2 3 4 5 6 7 8 set simdr, siscr, sirdar, sicdar, and sifctr set the scke bit in sictr to 1 start siofsck output set the fse and rxe bits in sictr to 1 rdreq = 1? transfer ended? clear the rxe bit in sictr to 0 set operating mode, serial clock, slot positions for receive data, slot position for control data, and fifo request threshold value set operation start for baud rate generator output serial clock flow chart siof settings siof operation set the start for frame synchronous signal output and enable reception issue receive transfer request according to the receive fifo threshold value reception end reception output frame synchronous signal read receive data set to disable reception read sirdr store siofrxd receive data in sirdr synchronously with siof_sync figure 22.10 example of recei ve operation in master mode
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 840 of 1286 rej09b0158-0100 transmission in slave mode: figure 22.11 shows an example of settings and oper ation for slave mode transmission. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sicdar, sitcr, and sifctr set the txe bit in sictr to 1 tdreq = 1? set sitdr transmit sitdr from siof_txd synchronously with siof_sync transfer ended? clear the txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit data, slot position for control data, control data, and fifo request threshold value set transmit data set to disable transmission issue transmit transfer request to enable transmission when frame synchronous signal is input transmit end transmission flow chart siof settings siof operation set to enable transmission figure 22.11 example of transmit operation in slave mode
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 841 of 1286 rej09b0158-0100 reception in slave mode: figure 22.12 shows an example of settings and operation for slave mode reception. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sirdar, sicdar, and sifctr set the rxe bit in sictr to 1 rdreq = 1? transfer ended? clear the rxe bit in sictr to 0 set operating mode, serial clock, slot positions for receive data, slot position for control data, and fifo request threshold value flow chart siof settings siof operation issue receive transfer request according to the receive fifo threshold value reception end reception read receive data set to disable reception read sirdr store siofrxd receive data in sirdr synchronously with siof_sync set to enable reception enable reception when the frame synchronous signal is input figure 22.12 example of recei ve operation in slave mode
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 842 of 1286 rej09b0158-0100 transmit/receive reset: the siof can separately reset the tr ansmit and receive units by setting the following bits to 1. ? ? type objects initialized transmit reset stop transmitting form the s iof_txd (high level is outputted) transmit fifo write pointer tcrdy, tfemp, and tdreq bits in sistr txe bit in sictr receive reset stop receiving form the siof_rxd receive fifo write pointer rcrdy, rfful, and rdreq bits in sistr rxe bit in sictr
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 843 of 1286 rej09b0158-0100 22.4.8 interrupts the siof has one type of interrupt. interrupt sources: interrupts can be issued by several sour ces. each source is shown as an siof status in sistr. table 22.14 lists the siof interrupt sources. table 22.14 siof interrupt sources no. classification bit name function name description 1 tdreq transmit fifo transfer request the transmit fifo stores data of specified size or more. 2 transmission tfemp transmit fifo empty the transmit fifo is empty. 3 rdreq receive fifo transfer request the receive fifo stores data of specified size or more. 4 reception rfful receive fifo full the receive fifo is full. 5 tcrdy transmit control data ready the transmit control register is ready to be written. 6 control rcrdy receive control data ready the receive control data register stores valid data. 7 tfudf transmit fifo underflow serial data transmit timing has arrived while the transmit fifo is empty. 8 tfovf transmit fifo overflow write to the transmit fifo is performed while the transmit fifo is full. 9 rfovf receive fifo overflow serial data is received while the receive fifo is full. 10 rfudf receive fifo underflow the receive fifo is read while the receive fifo is empty. 11 fserr fs error a synchronous signal is input before the specified bit number has been passed (in slave mode). 12 error saerr assign error the same slot is specified in both serial data and control data. whether an interrupt is issued or not as the result of an interrupt source is determined by the siier settings. if an interrupt source is set to 1 and th e corresponding bit in siier is set to 1, an siof interrupt is issued.
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 844 of 1286 rej09b0158-0100 regarding interrupt source: the transmit sources and receive so urces are signals indicating the siof state; after being set, if the state change s, they are automatically cleared by the siof. when the dma transfer is used, a dma transfer re quest of the fifo is di sabled for one cycle at the end of that dma transfer. processing when errors occur: on occurrence of each of the erro rs indicated as a status in sistr, the siof performs the following operations. ? ? ? ? ? ? ? ?
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 845 of 1286 rej09b0158-0100 22.4.9 transmit a nd receive timing examples of the siof serial transmission and reception are shown in figure 22.13 to figure 22.19. 8-bit monaural data (1): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, an frame length = 8 bits siof_sck siof_rxd siof_txd siof_sync l-channel data slot no.0 trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0000, fl[3:0] = 0000 (frame length: 8 bits) tdre = 0, rdre = 0, cd1e = 0, tdra[3:0] = 0000, rdra[3:0] = 0000, cd1a[3:0] = 0000 specifications: 1 frame 1-bit delay figure 22.13 transmit and receive timing (8-bit monaural data (1)) 8-bit monaural data (2): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, and frame length = 16 bits siof_sck siof_rxd siof_txd siof_sync l-channel data trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0000, fl[3:0] = 0100 (frame length: 16 bits) tdre = 0, rdre = 0, cd1e = 0, tdra[3:0] = 0000, rdra[3:0] = 0000, cd1a[3:0] = 0000 slot no.0 slot no.1 specifications: 1 frame 1-bit delay figure 22.14 transmit and receive timing (8-bit monaural data (2))
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 846 of 1286 rej09b0158-0100 16-bit monaural data: synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, and frame length = 64 bits siof_sck siof_rxd siof_txd siof_sync l-channel data trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 0, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0000, fl[3:0] = 1101 (frame length: 64 bits) tdre = 0, rdre = 0, cd1e = 0, tdra[3:0] = 0000, rdra[3:0] = 0000, cd1a[3:0] = 0000 slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame 1-bit delay figure 22.15 transmit and receive timing (16-bit monaural data) 16-bit stereo data (1): l/r method, rising edge sampling, slot no.0 used for left channel data, slot no.1 used for right channel data, and frame length = 32 bits siof_sck siof_rxd siof_txd siof_sync l-channel data trmd[1:0] = 11, tdle = 1, rdle = 1, cd0e = 0, redg = 1, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0000, fl[3:0] = 1100 (frame length: 32 bits) tdre = 1, rdre = 1, cd1e = 0, tdra[3:0] = 0001, rdra[3:0] = 0001, cd1a[3:0] = 0000 r-channel data slot no.0 slot no.1 specifications: 1 frame no bit delay figure 22.16 transmit and receive timing (16-bit stereo data (1))
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 847 of 1286 rej09b0158-0100 16-bit stereo data (2): l/r method, rising edge sampling, slot no.0 used for left-channel transmit data, slot no.1 used fo r left-channel receive data, slot no.2 used for right-channel transmit data, slot no.3 used for right-channel receive data, and frame length = 64 bits siof_sck siof_rxd siof_txd siof_sync trmd[1:0] = 11, tdle = 1, rdle = 1, cd0e = 0, redg = 1, tdla[3:0] = 0000, rdla[3:0] = 0001, cd0a[3:0] = 0000, fl[3:0] = 1101 (frame length: 64 bits), tdre = 1, rdre = 1, cd1e = 0, tdra[3:0] = 0010, rdra[3:0] = 0011, cd1a[3:0] = 0000 l-channel data r-channel data l-channel data r-channel data slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame no bit delay figure 22.17 transmit and receive timing (16-bit stereo data (2)) 16-bit stereo data (3): synchronous pulse method, falling edge sampling, slot no.0 used for left- channel data, slot no.1 used for right-channel data, slot no.2 used for control data for channel 0, slot no.3 used for control data for channel 1, and frame length = 128 bits siof_sck siof_rxd siof_txd siof_sync trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] =0010, fl[3:0] = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra[3:0] = 0001, rdra[3:0] = 0001, cd1a[3:0] = 0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 22.18 transmit and receive timing (16-bit stereo data (3))
section 22 serial i/o with fifo (siof) rev.1.00 dec. 13, 2005 page 848 of 1286 rej09b0158-0100 16-bit stereo data (4): synchronous pulse method, falling edge sampling, slot no.0 used for left- channel data, slot no.2 used for right-channel data, slot no.1 used for control data for channel 0 , slot no.3 used for control data for channel 1, and frame length = 128 bits siof_sck siof_rxd siof_txd siof_sync trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 1, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0001, fl[3:0] = 1110 (frame length: 128 bits) tdre = 1, rdre = 1, cd1e = 1, tdra[3:0] = 0010, rdra[3:0] = 0010, cd1a[3:0] = 0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 22.19 transmit and receive timing (16-bit stereo data (4)) synchronization-pulse output mode at end of each slot (syncat bit = 1): synchronous pulse method, falling edge sampling, slot no.0 used for left-channel data, slot no.1 used for right- channel data, slot no.2 used for control data for channel 0, slot no.3 used for control data for channel 1, and frame length = 128 bits in this mode, valid data must be set to slot no. 0. siof_sck siof_rxd siof_txd siof_sync trmd[1:0] = 00 or 10, tdle = 1, rdle = 1, cd0e = 1, redg = 0, tdla[3:0] = 0000, rdla[3:0] = 0000, cd0a[3:0] = 0010, fl[3:0] = 1110 (frame length: 128 bits), tdre = 1, rdre = 1, cd1e = 1, tdra[3:0] = 0001, rdra[3:0] = 0001, cd1a[3:0] = 0011 l-channel data r-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame figure 22.20 transmit and recei ve timing (16-bit stereo data)
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 849 of 1286 rej09b0158-0100 section 23 serial protocol interface (hspi) this lsi incorporates one channel of the serial protocol interface (hspi). 23.1 features the hspi has the following features. ? ? ? ? ? ?
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 850 of 1286 rej09b0158-0100 figure 23.1 is a block diagram of the hspi. spcr spcr: sprbr: spscr: spsr: sptbr: control register receive buffer register system control register status register transmit buffer register spsr spscr sptbr sprbr msb lsb hspi_tx hspi_rx interrupt (spii) [legend] hspi_cs hspi_clk bus interface register system control shift register clock division peripheral clock (pck) polarity selection sck generator figure 23.1 block diagram of hspi
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 851 of 1286 rej09b0158-0100 23.2 input/output pins the input/output pins of the hspi is shown in table 23.1. table 23.1 pin configuration pin name function i/o description hspi_clk serial bit clock pi n input/output clock input/output hspi_tx transmit data pin ou tput transmit data output hspi_rx receive data pin input receive data input hspi_cs chip select pin inpu t/output chip select note: these pins are multiplexed with the scif channel 0, flctl, gpio and mode control pins. 23.3 register descriptions table 23.2 shows the hspi regist er configuration. table 23.3 show s the register states in each processing mode. table 23.2 register configuration register name abbrev. r/w p4 address area 7 address size sync clock control register spcr r/w h'ffe5 0000 h'1fe5 0000 32 pck status register spsr r/w * h'ffe5 0004 h'1fe5 0004 32 pck system control register spscr r/w h'ffe5 0008 h'1fe5 0008 32 pck transmit buffer register sptbr r/ w h'ffe5 000c h'1fe5 000c 32 pck receive buffer register sprbr r h'ffe5 0010 h'1fe5 0010 32 pck note: to clear the flag, only 0s are written to bits 4 and 3. table 23.3 register states of hs pi in each processing mode register name abbrev. power-on reset by preset pin/wdt/h-udi manual reset by wdt/multiple exception sleep by sleep instruction module standby control register spcr h'0000 0000 h'0000 0000 retained retained status register spsr h'0000 0020 h'xxxx xx20 retained retained system control register spscr h'0000 0040 h'0000 0040 retained retained transmit buffer register sptbr h'0000 0000 h'0000 0000 retained retained receive buffer register sprbr h'0000 0000 h'0000 0000 retained retained
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 852 of 1286 rej09b0158-0100 23.3.1 control register (spcr) spcr is a 32-bit readable/writable register that c ontrols the transfer data of shift timing and specifies the clock polarity and frequency. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 clkc0 clkc1 clkc2 clkc3 clkc4 idiv clkp fbs ? ? ? ? ? ? ?? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 8 ? all 0 r reserved although the initial value is 0, these bits will be read as an undefined value. the write value should always be 0. 7 fbs 0 r/w first bit start controls the timing relationship between each bit of transferred data and the serial bit clock. 0: the first bit transmitted from the hspi module is set up such that it can be sampled by the receiving device on the first edge of hspi_clk after the hspi_cs pin goes low. similarly the first received bit is sampled on the first edge of hspi_clk after the hspi_cs pin goes low. 1: the first bit transmitted from the hspi module is set up such that it can be sampled by the receiving device on the second edge of hspi_clk after the hspi_cs pin goes low. similarly the first received bit is sampled on the second edge of hspi_clk after the hspi_cs pin goes low. 6 clkp 0 r/w serial clock polarity 0: hspi_clk signal is not inverted and so is low when inactive. 1: hspi_clk signal is inverted and so is high when inactive.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 853 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 idiv 0 r/w initial clock division ratio 0: the peripheral clock is divided by a factor of 4 initially to create an intermediate frequency, which is further divided to create the serial bit clock when master mode. 1: the peripheral clock is divided by a factor of 32 initially to create an intermediate frequency, which is further divided to create the serial bit clock when master mode. 4 to 0 clkc4 to clkc0 all 0 r/w clock division count these bits determine the number of intermediate frequency cycles long both the high and low periods of the serial bit clock. 00000: 1 intermediate frequency cycle. serial bit clock frequency = intermediate frequency / 2. 00001: 2 intermediate frequency cycles. serial bit clock frequency = intermediate frequency / 4. 00010: 3 intermediate frequency cycles. serial bit clock frequency = intermediate frequency / 6. : : 11111: 32 intermediate frequency cycles. serial bit clock frequency = intermediate frequency / 64. the serial bit clock frequency can be computed using the following formula: peripheral clock frequency initial division ratio ((clock division count + 1) 2) serial bit clock frequency = when the hspi is configured as a slave, the idiv and clkc bits are ignored and the hspi synchronizes to the externally supplied serial bit clock. the maximum value of the external serial bit clock that the module can operate with is peripheral clock frequency / 8. if any of the fbs, clkp, idiv or clkc bit values are changed, then the hspi will undergo the hspi software reset.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 854 of 1286 rej09b0158-0100 23.3.2 status register (spsr) spsr is a 32-bit readable/writable register. the stat us flag in spsr can confirm whether the hspi correctly operates or not. if the roie bit in spscr is set to 1, an interrupt request is generated due to the occurrence of the receive buffer over run error or the warning of the receive buffer overrun error. when the tfie bit in spscr is set to 1, an interrupt request is generated by the transmit complete status flag. if the appropriate enable bit in spscr is set to 1, an interrupt request is generated due to the r eceive fifo halfway, receive fifo full, transmit fifo empty, or transmit fifo halfway flag. if the rnie bit in sps cr is set to 1, an interrupt request is generated when the receive fifo is not empty. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 0 0 1 0 0 txfl txfn rxfl rxow rxoo rxem rxha rxfu txem txha txfu ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ?? r r r r/w r/w r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 11 ? undefined r reserved these bits are always read as an undefined value. the write value should always be 0. 10 txfu 0 r transmit fifo full flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the transmit fifo is full of bytes for transmission and cannot accept any more. it is cleared to 0 when data is transmitted from the transmit fifo. 9 txha 0 r transmit fifo halfway flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the transmit fifo reaches the halfway point, that is, it has 4 bytes of data and 4 spaces for more data. it is cleared to 0 when more data is written to the transmit fifo. it remains set to 1 until cleared to 0 even if the subsequent fifo level becomes under the halfway point (4 bytes). if txha = 1 and thie = 1 then the interrupt is generated.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 855 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 txem 1 r transmit fifo empty flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the transmit fifo is empty of data to transmit. it is cleared to 0 when more data is written to the transmit fifo. if txem = 1 and teie = 1 then the interrupt is generated. 7 rxfu 0 r receive fifo full flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the receive fifo is full of received bytes and cannot accept any more. it is cleared to 0 when data is read out of the receive fifo. if rxfu = 1 and rfie = 1 then the interrupt is generated. 6 rxha 0 r receive fifo halfway flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the receive fifo reaches the halfway point, that is, it has 4 bytes of data and 4 spaces for more data. this flag is cleared to 0 when the receive data is read from receive fifo and the fifo level becomes under 4 bytes (halfway point). it remain set to 1 until cleared to 0 regardless of the subsequent fifo levels. if rxha = 1 and rhie = 1 then the interrupt is generated. 5 rxem 1 r receive fifo empty flag this status flag is enabled only to operation in fifo mode. the flag is set to 1 when the receive fifo is empty of received data. it is cleared to 0 when more data is received into to the receive fifo. if rxem = 0 and rnie = 1 then the interrupt is generated. 4 rxoo 0 r/w * receive buffer overrun occurred flag this status flag is set to 1 when new data has been received but the previous received data has not been read from sprbr. the previously received data will not be overwritten by the newly received data. the rxoo flag remain set to 1 until writing a 0 to its bit position. if rxoo = 1 and roie = 1 then the interrupt is generated.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 856 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 rxow 0 r/w * receive buffer overrun warning flag this status flag is set to 1 when a new serial data transfer starts and the previous received data has not been read from sprbr. the rxow remain set to 1 until writing a 0 to its bit position. if rxow= 1 and roie = 1 then the interrupt is generated. 2 rxfl 0 r receive buffer full status flag this status flag indicates that new data is available in the sprbr and has not yet been read. it is set to 1 at the completion of a serial bus transfer at the point the shift register contents are loaded into the sprbr. this bit is cleared to 0 by reading sprbr. if rxfl = 1 and rxde = 1 then the dma transfer request enabled. 1 txfn 0 r transmit complete status flag this status flag indicates that the last transmission has completed. it is set to 1 when sptbr is able to write more data from the peripheral bus. this bit is cleared to 0 by writing more data sptbr. if txfn = 1 and tfie = 1 then the interrupt is generated. 0 txfl 0 r transmit buffer full status flag this status flag indicates sptbr has transmitted data. it is set to 1 when sptbr is written with data from the peripheral bus. this bit is cleared to 0 when sptbr is able to accept more data from the peripheral bus. if txfl = 0 (i.e. the sptbr is empty) and txde = 1 then the dma transfer request enabled. note: * these bits are readable/writable bits. when wr iting 0, these bits are initialized, while writing 1 is ignored.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 857 of 1286 rej09b0158-0100 23.3.3 system control register (spscr) spscr is a 32-bit readable/writable register that enables or disables interrupts or fifo mode, selects either lsb first or msb first in transm itting/receiving date, and master or slave mode. if any of the ffen, lmsb, csa or masl bit values are changed, then the module will undergo the hspi software reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 1 0 0 0 0 0 0 0 masl txde rxde roie tfie csa csv lmsb ffen rfie rhie rnie thie teie ?? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 14 ? all 0 r reserved although the initial value is 0, these bits will be read as an undefined value. the write value should always be 0. 13 teie 0 r/w transmit fifo empty interrupt enable 0: transmit fifo empty interrupt disabled 1: transmit fifo empty interrupt enabled 12 thie 0 r/w transmit fifo halfway interrupt enable 0: transmit fifo halfway interrupt disabled 1: transmit fifo halfway interrupt enabled 11 rnie 0 r/w receive fifo no t empty interrupt enable 0: receive fifo not empty interrupt disabled 1: receive fifo not em pty interrupt enabled 10 rhie 0 r/w receive fifo halfway interrupt enable 0: receive fifo halfway interrupt disabled 1: receive fifo halfway interrupt enabled 9 rfie 0 r/w receive fifo full interrupt enable 0: receive fifo full interrupt disabled 1: receive fifo full interrupt enabled
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 858 of 1286 rej09b0158-0100 bit bit name initial value r/w description 8 ffen 0 r/w fifo mode enable enables or disables the fifo mode. when fifo mode is enabled two 8-entry deep fifos are made available, one for transmit data and one for receive data. these fifos are read and written via sptbr and sprbr. when fifo mode is disabled the sptbr and sprbr are used directly so new data must be written to sptbr and read from sprbr for each and every transfer. fifo mode must be disabled if dma requests are also going to be used to service sptbr and sprbr. 0: fifo mode disabled 1: fifo mode enabled 7 lmsb 0 r/w lsb/msb first control 0: data is transmitted and received most significant bit (msb) first. 1: data is transmitted and received least significant bit (lsb) first. 6 csv 1 r/w chip select value controls the value output fr om the chip select when the hspi is a master and the chip select generation has been selected. 0: chip select output is low. 1: chip select output is high. 5 csa 0 r/w automatic/manual chip select 0: chip select output is aut omatically generated during data transfer. 1: chip select output is manually controlled, with its value being determined by the csv bit. 4 tfie 0 r/w transmit complete interrupt enable 0: transmit complete interrupt disabled 1: transmit complete interrupt enabled 3 roie 0 r/w receive overrun occurred / warning interrupt enable 0: receive overrun occurred / warning interrupt disabled 1: receive overrun occurred / warning interrupt enabled
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 859 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 rxde 0 r/w receive dma enable 0: receive dma transfer request disabled 1: receive dma transfer request enabled 1 txde 0 r/w transmit dma enable 0: transmit dma transfer request disabled 1: transmit dma transfer request enabled 0 masl 0 r/w master/slave select bit 0: hspi module configured as a slave 1: hspi module configured as a master 23.3.4 transmit bu ffer register (sptbr) sptbr is a 32-bit readable/writable register that stores data to be transmitted. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 td ? ? ? ? ? ? ?? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 8 ? all 0 r reserved although the initial value is 0, these bits will be read as an undefined value. the write value should always be 0. 7 to 0 td all 0 r/w transmit data data written to this register is transferred to the shift register for transmission. when reading these bits, always read as data stored in the transmit buffer.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 860 of 1286 rej09b0158-0100 23.3.5 receive buffer register (sprbr) sprbr is a 32-bit read-only register that stores the number of received data. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r r r r r r r r r r r r r r rr bit: initial value: r/w: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 rd ? ? ? ? ? ? ?? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 r r r r r r r r r r r r r r rr bit: initial value: r/w: bit bit name initial value r/w description 31 to 8 ? all 0 r reserved although the initial value is 0, these bits will be read as an undefined value. the write value should always be 0. 7 to 0 rd all 0 r receive data data from the shift register, which is stored as each byte, is received, if the previously received data has been read.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 861 of 1286 rej09b0158-0100 23.4 operation 23.4.1 operation overview without dma (fifo mode disabled) figure 23.2 shows the flow of a transmit/receive operation procedure. yes no no yes start reset the system select master or slave operation by setting the masl bit in spscr select required interrupts by setting tfie and roie bits in spscr check if txbuff is empty by reading the txfl bit in spsr write data to sptbr tx/rx data to/from slave another transmit required? end figure 23.2 operational flowchart depending on the settings of spcr, the master tran smits data to the slave on either the falling or rising edge of hspi_clk and samples data from the slave on the opposite edge. the data transfer between the master and slave comp letes when the transmit complete status flag (txfn) in spsr is set to 1. this flag should be used to identify when an hspi transfer event (byte transmitted and byte received) has occurred, even in the case where the hspi module is being used to receive data only (null data being transmitted). by default data is transmitted msb first, but lsb first is also possible depending on how the lmsb bit in spscr is set.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 862 of 1286 rej09b0158-0100 during the transmit function the slave responds by sending data to the master synchronized with the hspi_clk from the master transmitted. data fr om the slave is sampled and transferred to the shift register in the module and on completion of the transmit function, is transferred to sprbr. the hspi_cs pin is used to select the hspi module when the hspi is configured as a slave, and prepare it to receive data from an external master. when the fbs bit in spcr is 0, the hspi_cs pin must be driven high between successive bytes. when the fbs = 1, the hspi_cs pin can stay low for several byte transmissions. in this case, if the system is configured such that the fbs is always 1, then the hspi_cs line can be fixed at ground (if the hspi will only be used as a slave). 23.4.2 operation overview with dma the operation of the hspi when dma is used to perform transmit and receive data transfers is simpler than when dma is not used. the hspi mu st be configured as in the case for transfers without dma. fifo mode must be disabled. the dma controller (dmac) should then be configured to transfer the requir ed amount of data. dma requests can then be enabled in the hspi module and the transfers will then take place without further processor intervention. when the dmac indicates that all transfers have ended th en the dma request signals in the hspi module should be disabled to remove an y remaining dma requests. this is necessary as the hspi module will always request data to transmit. 23.4.3 operation with fifo mode enabled in order to reduce the interrupt overhead on the processor in the case fo r operation without dma mode, fifo mode has been provided. when fifo mode is enabled, up to 8 bytes can be written in advance for transmission and up to 8 bytes can be received before the rece ive fifo needs to be read. to transfer the specified amount of data between the hspi module and an external device, follow the following procedure: 1. set up the module for the required hspi transf er characteristics (master/slave, clock polarity etc.) and enable fifo mode. 2. write bytes into the transmit fi fo via sptbr. if more than 8 bytes are to be transmitted then enable the transmit fifo halfway interrupt to keep track of the fifo level as data is transmitted. 3. respond to the transmit fifo halfway interrupt when it occurs by writing more data to the transmit fifo and reading data fr om the receive fifo via sprbr. 4. when all of the transmit data has been writte n into the transmit fifo, disable the transmit fifo halfway interrupt and read the contents of the receive fifo until it is empty. enable the receive fifo not empty interrupt to keep track of when the final bytes of the transfer are received. 5. respond to the receive fifo not empty interrup t until all the expected data has been received.
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 863 of 1286 rej09b0158-0100 6. disable the module until it is required again. in some applications, an undefined amount of data will received from an external hspi device. if this is the case, follow the following procedure: 1. set up the module for the required hspi tran sfer characteristics (maste r/slave, clock polarity etc.) and enable fifo mode. 2. fill the transmit fifo with the data to tr ansmit. enable the receive fifo not empty interrupt. 3. respond to the receive fifo not empty interrupt and read data from the receive fifo until it is empty. write more data to the transmit fifo if required. 4. disable the module when the transfer is to stop. 23.4.4 timing diagrams the following diagrams explain the timing relationship of all shift and sample processes in the hspi. figure 23.3 shows the conditions when fbs = 0, while figure 23.4 shows the conditions when fbs = 1. it can be seen that if clkp in sp cr is 0 then transmit data is shifted on the falling edge of hspi_clk and receive data is sampled on the rising edge. the opposite is true when clkp = 1. sck_cycle hspi_clk (clkp = 0) hspi_clk (clkp = 1) 1 4 3 2 8 7 6 5 hspi_tx msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb * hspi_rx hspi_cs figure 23.3 timing conditions when fbs = 0
section 23 serial protocol interface (hspi) rev.1.00 dec. 13, 2005 page 864 of 1286 rej09b0158-0100 sck_cycle hspi_clk (clkp = 0) hspi_clk (clkp = 1) 1 4 3 2 8 7 6 5 msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb * hspi_tx hspi_rx hspi_rx figure 23.4 timing conditions when fbs = 1 23.4.5 hspi software reset if any of the fbs, clkp, idiv or clkc bit values are changed, then the hspi software reset is generated. the receive and transmit fifo pointers can be initialized by th e hspi software reset. the data transmission after the hspi software reset should protect transmitting and receiving protocol of hspi, and please perform it from the first. a guarantee of operation is not offered other than it. while the master device is not tran sferring data and the hspi is in slave mode, the hspi software reset should be generated before asserting the hspi_cs . this prevent the hspi from receiving an erroneous data. 23.4.6 clock polarity and transmit control spcr also allows the user to define the shift timing for transmit data and polarity. the fbs bit in spcr allows selection between two different transf er formats. the msb or lsb is valid on the falling edge of hspi_cs . the clkp bit in spcr allows for control of the polarity select block which controls which edges of hspi_clk shift and sample data in the master and slave. 23.4.7 transmit and receive routines the master and slave can be considered linked toge ther as a circular shift register synchronized with hspi_clk. the transmit byte from the master is replaced with the receive byte from the slave in eight hspi_clk cycles. both the transmit and receive func tions are double buffered to allow for continuous reads and writes. when fi fo mode is enabled eight entry fifos are available for both tran smit and receive data.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 865 of 1286 rej09b0158-0100 section 24 multimedia card interface (mmcif) this lsi supports a mu ltimedia card interface (mmcif). the mmc mode interface can be utilized. the mmcif is a clock-s ynchronous serial interface that tr ansmits/receives data that is distinguished in terms of command and response. a number of commands/responses are predefined in the multimedia card. as the mmcif specifies a command code and command type/response type upon the issuance of a co mmand, commands extended by the secure multimedia card (secure-mmc) and additional comma nds can be supported in the future within the range of combinations of currently defined command types/response types. 24.1 features the mmcif has the fo llowing features: ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 866 of 1286 rej09b0158-0100 figure 24.1 shows a block diagram of the mmcif. mmcif fifo mcdat f s tat tran err frdy mccmd mcclk peripheral bus peripheral bus interface data transmission/ reception control command transmission/ response reception control interrupt control mmc mode control card clock generator figure 24.1 block diagram of mmcif 24.2 input/output pins table 24.1 summarizes the pins of the mmcif. table 24.1 pin configuration pin name i/o function mcclk output card clock output mccmd input/output command output/response input mcdat input/output data input/output note: for insertion/detachment of a card or for signals switching over between open-drain and cmos modes, use ports of this lsi. these pins are multiplexed with the scif channel 1, gpio, and mode control pins.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 867 of 1286 rej09b0158-0100 24.3 register descriptions table 24.2 shows the mmcif register configuration. table 24.3 shows the register states in each processing mode. table 24.2 register configuration register name abbrev. r/w p4 address area 7 address size sync clock command register 0 cmdr0 r/w h'ffe6 0000 h'1fe6 0000 8 pck command register 1 cmdr1 r/w h'ffe6 0001 h'1fe6 0001 8 pck command register 2 cmdr2 r/w h'ffe6 0002 h'1fe6 0002 8 pck command register 3 cmdr3 r/w h'ffe6 0003 h'1fe6 0003 8 pck command register 4 cmdr4 r/w h'ffe6 0004 h'1fe6 0004 8 pck command register 5 cmdr5 r h'ffe6 0005 h'1fe6 0005 8 pck command start register cmdstrt r /w h'ffe6 0006 h'1fe6 0006 8 pck operation control register opcr r/ w h'ffe6 000a h'1fe6 000a 8 pck card status register cstr r h'ffe6 000b h'1fe6 000b 8 pck interrupt control register 0 intcr0 r/w h'ffe6 000c h'1fe6 000c 8 pck interrupt control register 1 intcr1 r/w h'ffe6 000d h'1fe6 000d 8 pck interrupt status register 0 intstr 0 r/w h'ffe6 000e h'1fe6 000e 8 pck interrupt status register 1 intstr1 r/w h'ffe6 000f h'1fe6 000f 8 pck transfer clock control register clkon r/w h'ffe6 0010 h'1fe6 0010 8 pck command timeout control register ctocr r/w h'ffe6 0011 h'1fe6 0011 8 pck transfer byte number count register tbcr r/w h'ffe6 0014 h'1fe6 0014 8 pck mode register moder r/w h'ffe6 0016 h'1fe6 0016 8 pck command type register cmdtyr r/w h'ffe6 0018 h'1fe6 0018 8 pck response type register rsptyr r/w h'ffe6 0019 h'1fe6 0019 8 pck transfer block number counter tbncr r/w h'ffe6 001a h'1fe6 001a 16 pck response register 0 rspr0 r/w h'ffe6 0020 h'1fe6 0020 8 pck response register 1 rspr1 r/w h'ffe6 0021 h'1fe6 0021 8 pck response register 2 rspr2 r/w h'ffe6 0022 h'1fe6 0022 8 pck response register 3 rspr3 r/w h'ffe6 0023 h'1fe6 0023 8 pck response register 4 rspr4 r/w h'ffe6 0024 h'1fe6 0024 8 pck
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 868 of 1286 rej09b0158-0100 register name abbrev. r/w p4 address area 7 address size sync clock response register 5 rspr5 r/w h'ffe6 0025 h'1fe6 0025 8 pck response register 6 rspr6 r/w h'ffe6 0026 h'1fe6 0026 8 pck response register 7 rspr7 r/w h'ffe6 0027 h'1fe6 0027 8 pck response register 8 rspr8 r/w h'ffe6 0028 h'1fe6 0028 8 pck response register 9 rspr9 r/w h'ffe6 0029 h'1fe6 0029 8 pck response register 10 rspr10 r/w h'ffe6 002a h'1fe6 002a 8 pck response register 11 rspr11 r/w h'ffe6 002b h'1fe6 002b 8 pck response register 12 rspr12 r/w h'ffe6 002c h'1fe6 002c 8 pck response register 13 rspr13 r/w h'ffe6 002d h'1fe6 002d 8 pck response register 14 rspr14 r/w h'ffe6 002e h'1fe6 002e 8 pck response register 15 rspr15 r/w h'ffe6 002f h'1fe6 002f 8 pck response register 16 rspr16 r/w h'ffe6 0030 h'1fe6 0030 8 pck crc status register rsprd r/w h'ffe6 0031 h'1fe6 0031 8 pck data timeout register dtoutr r/w h'ffe6 0032 h'1fe6 0032 16 pck data register dr r/w h'ffe6 0040 h'1fe6 0040 16 pck fifo pointer clear register fifoclr w h'ffe6 0042 h'1fe6 0042 8 pck dma control register dmacr r/w h'ffe6 0044 h'1fe6 0044 8 pck interrupt control register 2 intcr2 r/w h'ffe6 0046 h'1fe6 0046 8 pck interrupt status register 2 intstr2 r/w h'ffe6 0048 h'1fe6 0048 8 pck
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 869 of 1286 rej09b0158-0100 table 24.3 register states of hs pi in each processing mode register name abbrev. power-on reset by preset pin/wdt/ h-udi manual reset by wdt/ multiple exception sleep by sleep instruction module standby command register 0 cmdr0 h'00 h'00 retained retained command register 1 cmdr1 h'00 h'00 retained retained command register 2 cmdr2 h'00 h'00 retained retained command register 3 cmdr3 h'00 h'00 retained retained command register 4 cmdr4 h'00 h'00 retained retained command register 5 cmdr5 h'00 h'00 retained retained command start register cmdstr t h'00 h'00 retained retained operation control register opcr h'00 h'00 retained retained card status register cstr h'0x h'0x retained retained interrupt control register 0 intcr0 h'00 h'00 retained retained interrupt control register 1 intcr1 h'00 h'00 retained retained interrupt status register 0 in tstr0 h'00 h'00 retained retained interrupt status register 1 in tstr1 h'00 h'00 retained retained transfer clock control register clkon h'00 h'00 retained retained command timeout control register ctocr h'01 h'01 retained retained transfer byte number count register tbcr h'00 h'00 retained retained mode register moder h'00 h'00 retained retained command type register cmdtyr h'00 h'00 retained retained response type register rsptyr h'00 h'00 retained retained transfer block number counter tbncr h'0000 h'0000 retained retained response register 0 rspr0 h'00 h'00 retained retained response register 1 rspr1 h'00 h'00 retained retained response register 2 rspr2 h'00 h'00 retained retained response register 3 rspr3 h'00 h'00 retained retained response register 4 rspr4 h'00 h'00 retained retained response register 5 rspr5 h'00 h'00 retained retained
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 870 of 1286 rej09b0158-0100 register name abbrev. power-on reset by preset pin/wdt/ h-udi manual reset by wdt/ multiple exception sleep by sleep instruction module standby response register 6 rspr6 h'00 h'00 retained retained response register 7 rspr7 h'00 h'00 retained retained response register 8 rspr8 h'00 h'00 retained retained response register 9 rspr9 h'00 h'00 retained retained response register 10 rspr10 h'00 h'00 retained retained response register 11 rspr11 h'00 h'00 retained retained response register 12 rspr12 h'00 h'00 retained retained response register 13 rspr13 h'00 h'00 retained retained response register 14 rspr14 h'00 h'00 retained retained response register 15 rspr15 h'00 h'00 retained retained response register 16 rspr16 h'00 h'00 retained retained crc status register rsprd h'00 h'00 retained retained data timeout register dtoutr h'ffff h'ffff retained retained data register dr h'xxxx h'xxxx retained retained fifo pointer clear register fifoclr h'00 h'00 retained retained dma control register dmacr h'00 h'00 retained retained interrupt control register 2 intcr2 h'00 h'00 retained retained interrupt status register 2 ints tr2 h'0x h'0x retained retained [legend] x: undefined
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 871 of 1286 rej09b0158-0100 24.3.1 command registers 0 to 5 (cmdr0 to cmdr5) the cmdr registers are six 8-bit registers. a command is written to cmdr as shown in table 24.4, and the command is transmitted when the start bit in cmdstrt is set to 1. each command is transmitted in order form the msb (b it 7) in cmdr0 to the lsb (bit 0) in cmdr5. table 24.4 cmdr configuration register contents operation cmdr0 to cmdr4 command argument write command arguments. cmdr5 crc and end bit setting of crc is unnecessary (automatic calculation). end bit is fixed to 1 and its setting is unnecessary (automatic setting). the read value is 0. ? bit: initial value: r/w: 76543210 0000 (command argument) 0000 r/w r/w r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 7 to 0 (command argument) all 0 r/w command arguments see specifications for the mmc card. ? bit: initial value: r/w: 7654321 0 00000000 r crc end rr rr rrr bit bit name initial value r/w description 7 to 1 crc all 0 r these bits are alwa ys read as 0. the write value should always be 0. 0 end 0 r this bit is always read as 0. the write value should always be 0.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 872 of 1286 rej09b0158-0100 24.3.2 command start register (cmdstrt) cmdstrt is an 8-bit readable/writable register th at triggers the start of command transmission, representing the start of a comma nd sequence. the following operations should have been completed before the command sequence starts. ? ? ? ? ? bit: initial value: r/w: 7654321 0 00000000 r start r r r r r r r/w ?????? ? bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 start 0 r/w starts command transmission when 1 is written. this bit is automatically cleared after the mmcif received start command. when 0 is written to this bit, operation is not affected.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 873 of 1286 rej09b0158-0100 24.3.3 operation cont rol register (opcr) opcr is an 8-bit readable/writable register th at aborts command operation, and suspends or continues data transfer. bit: initial value: r/w: 7654321 0 00000000 r/w dataen rd_ conti cmd off r r/w r/w r r r r ????? bit bit name initial value r/w description 7 cmdoff 0 r/w command off aborts all command operations (mmcif command sequence) when 1 is written after a command is transmitted. this bit is cleared automatically after the mmcif received the cmdoff command. write enabled period: from command transmission completion to command sequence end write of 0: operation is not affected. write of 1: command sequence is forcibly aborted. note: do not write to this bit out of the write enable period. 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 rd_conti 0 r/w read continue read data reception is resumed when 1 is written while the sequence has been halted by fifo full or termination of block reading in multiple block read. this bit is cleared automatically when 1 is written and the mmcif received the rd_conti command. write enabled period: while read data reception is halted write of 0: operation is not affected. write of 1: resumes read data reception. note: do not write to this bit out of the write enable period.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 874 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 dataen 0 r/w data enable starts a write data transmission by a command with write data. this bit is cleared automatically when 1 is written and the mmcif received the dataen command. resumes write data transmission while the sequence has been halted by fifo empty or termination of block writing in multiple block write. write enabled period: (1) after receiving a response to a command with write data, (2) while sequence is halted by fifo empty, (3) when one block writing in multiple block write is terminated. write of 0: operation is not affected. write of 1: starts or resu mes write data transmission. note: do not write to this bit out of the write enable period. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. in write data transmission, the contents of th e command response and data response should be analyzed, and then transmission should be triggered. in addition, the data transmission should be temporarily halted by fifo full/empty, and it s hould be resumed when the preparation has been completed. in multiple block transfer, the transfer should be temporarily halted at every block break to select either to continue to the next block or to abort the multiple block transfer command by issuing the cmd12 command. to continue to the next block, the rd_conti and dataen bits should be set to 1. to issue the cmd12 command, the cmdoff bit should be set to 1 to abort the command sequence on the mmcif side. when using th e auto-mode for a pre-defined multiple block transfer, the setting of the rd_conti bit or the dataen bit between blocks can be omitted.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 875 of 1286 rej09b0158-0100 24.3.4 card status register (cstr) cstr indicates the mmcif status du ring command sequence execution. bit: initial value: r/w: 7654321 0 00000 00 r dtbusy dtbusy _tu req busy cwre fifo_ full fifo_ empty rr rr rrr ? ? bit bit name initial value r/w description 7 busy 0 r command busy indicates command execution status. when the cmdoff bit in opcr is set to 1, this bit is cleared to 0 because the mmcif command sequence is aborted. 0: idle state waiting for a command, or data busy state 1: command sequence execution in progress 6 fifo_full 0 r fifo full this bit is set to 1 when the fifo becomes full while data is being received from the card, and cleared to 0 when rd_conti is set to 1 or the command sequence is completed. indicates whether the fifo is empty or not. 0: the fifo is empty. 1: the fifo is full. 5 fifo_empty 0 r fifo empty this bit is set to 1 when the fifo becomes empty while data is being sent to the card, and cleared to 0 when data_en is set to 1 or the command sequence is completed. indicates whether the fifo holds data or not. 0: the fifo includes data. 1: the fifo is empty.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 876 of 1286 rej09b0158-0100 bit bit name initial value r/w description 4 cwre 0 r command register write enable indicates whether the cmdr command is being transmitted or has been transmitted. 0: the cmdr command has bee n transmitted, or the start bit in cmdstrt has not been set yet, so the new command can be written. 1: the cmdr command is waiting for transmission or is being transmitted. if a new command is written, a malfunction will result. 3 dtbusy 0 r data busy indicates command execution st atus. indicates that the card is in the busy state after the command sequence of a command without data transfer which includes the busy state in the response, or a command with write data has been ended. 0: idle state waiting for a command, or command sequence execution in progress 1: card is in the data busy state after command sequence termination. 2 dtbusy_tu undefined r data busy pin status indicates the mcdat pin level. by reading this bit, the mcdat level can be monitored. 0: a low level is input to the mcdat pin. 1: a high level is input to the mcdat pin. 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 req 0 r interrupt request indicates whether an interrupt is requested or not. an interrupt request is the logical or of the intstr0, intstr1 and intstr2 flags. the intstr0, intstr1 and intstr2 flags set is controlled by the enable bits in intcr0, intstr1 and intcr2. 0: no interrupt requested. 1: interrupt requested.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 877 of 1286 rej09b0158-0100 24.3.5 interrupt control regist ers 0 to 2 (intcr0 to intcr2) the intcr registers enable or disable interrupts. ? bit: initial value: r/w: 7654321 0 00000 0 00 r/w feie ffie drpie dtie crpie cmdie dbs yie r/w r/w r/w r/w r/w r/w r/w btie bit bit name initial value r/w description 7 feie 0 r/w fifo empty interrupt flag setting enable 0: disables fifo empty interrupt (disables fei flag setting). 1. enables fifo empty interrupt (enables fei flag setting). 6 ffie 0 r/w fifo full interrupt flag setting enable 0: disables fifo full interrupt (disables ffi flag setting). 1: enables fifo full interrupt (enables ffi flag setting). 5 drpie 0 r/w data response interrupt flag setting enable 0: disables data response interrupt (disables dpri flag setting). 1: enables data response interrupt (enables dpri flag setting). 4 dtie 0 r/w data transfer end interrupt flag setting enable 0: disables data transfer end interrupt (disables dti flag setting). 1: enables data transfer end interrupt (enables dti flag setting). 3 crpie 0 r/w command response receive end interrupt flag setting enable 0: disables command response receive end interrupt (disables crpi flag setting). 1: enables command response receive end interrupt (enables crpi flag setting).
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 878 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 cmdie 0 r/w command transmit end interrupt flag setting enable 0: disables command transmit end interrupt (disables cmdi flag setting). 1: enables command transmit end interrupt (enables cmdi flag setting). 1 dbsyie 0 r/w data busy end interrupt flag setting enable 0: disables data busy end in terrupt (disables dbsyi flag setting). 1: enables data busy end interrupt (enables dbsyi flag setting). 0 btie 0 r/w multiple block transfer end flag flag setting enable 0: disables multiple block transfer end flag setting 1: enables multiple block transfer end flag setting ? bit: initial value: r/w: 7654321 0 00000 0 00 r/w intr q2e intr q1e intr q0e crce rie dte rie cte rie r/w r/w r r r/w r/w r/w ? ? bit bit name initial value r/w description 7 intrq2e 0 r/w err interrupt enable 0: disables err interrupt. 1: enables err interrupt. 6 intrq1e 0 r/w tran interrupt enable 0: disables tran interrupt. 1: enables tran interrupt. 5 intrq0e 0 r/w fstat interrupt enable 0: disables fstat interrupt. 1: enables fstat interrupt. 4, 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 879 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 crcerie 0 r/w crc error interrupt flag setting enable 0: disables crc error interrupt (disables crceri flag setting). 1: enables crc error interrupt (enables crceri flag setting). 1 dterie 0 r/w data timeout error interrupt flag setting enable 0: disables data timeout error interrupt (disables dteri flag setting). 1: enables data timeout error interrupt (enables dteri flag setting). 0 cterie 0 r/w command timeout error interrupt flag setting enable 0: disables command timeout error interrupt (disables cteri flag setting). 1: enables command timeout error interrupt (enables cteri flag setting). ? bit: initial value: r/w: 7654321 0 00000 0 00 r/w frdyie r r r r r r r/w ? ?? ? ?? intr q3e bit bit name initial value r/w description 7 intrq3e 0 r/w frdy interrupt enable 0: disables frdy interrupt. 1: enables frdy interrupt. 6 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 frdyie 0 r/w fifo ready interrupt enable 0: disables fifo ready interrupt (disables frdy flag setting). 1: enables fifo ready interrupt (enables frdy flag setting).
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 880 of 1286 rej09b0158-0100 24.3.6 interrupt status registers 0 to 2 (intstr0 to intstr2) the intstr registers enable or disable mmcif interrupts fstat, tran, err and frdy. ? bit: initial value: r/w: 7654321 0 00000 0 00 r/w fei ffi drpi dti crpi cmdi dbsyi r/w r/w r/w r/w r/w r/w r/w bti bit bit name initial value r/w description interrupt output 7 fei 0 r/w fifo empty interrupt flag 0: no interrupt [clearing condition] write 0 after reading fei = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when fifo becomes empty while feie = 1 and data is being transmitted (when the fifo_empty bit in cstr is set) fstat 6 ffi 0 r/w fifo full interrupt flag 0: no interrupt [clearing condition] write 0 after reading ffi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when fifo becomes full while ffie = 1 and data is being received (when the fifo_full bit in cstr is set) fstat
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 881 of 1286 rej09b0158-0100 bit bit name initial value r/w description interrupt output 5 drpi 0 r/w data response interrupt flag 0: no interrupt [clearing condition] write 0 after reading drpi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when the crc status is received while drpie = 1. tran 4 dti 0 r/w data transfer end interrupt flag 0: no interrupt [clearing condition] write 0 after reading dti = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when the number of bytes of data transfer specified in tbcr ends while dtie = 1. tran 3 crpi 0 r/w command response receive end interrupt flag 0: no interrupt [clearing condition] write 0 after reading crpi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when command response reception ends while crpie = 1. tran 2 cmdi 0 r/w command transmit end interrupt flag 0: no interrupt [clearing condition] write 0 after reading cmdi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when command transmission ends while cmdie = 1. (when the cwre bit in cstr is cleared.) tran
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 882 of 1286 rej09b0158-0100 bit bit name initial value r/w description interrupt output 1 dbsyi 0 r/w data busy end interrupt flag 0: no interrupt [clearing condition] write 0 after reading dbsyi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when data busy state is canceled while dbsyie = 1. (when the dtbusy bit in cstr is cleared.) tran 0 bti 0 r/w multiple block transfer end flag 0: no interrupt [clearing condition] write 0 after reading bti = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when the number of bytes of data transfer specified in tbcr is reached while btie = 1 and tbncr = 0. tran
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 883 of 1286 rej09b0158-0100 ? bit: initial value: r/w: 7654321 0 00000 0 00 r crc eri dteri cteri r r r r r/w r/w r/w ????? bit bit name initial value r/w description interrupt output 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? 2 crceri 0 r/w crc error interrupt flag 0: no interrupt [clearing condition] write 0 after reading crceri = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when a crc error for command response or receive data or a crc status error for transmit data response is detected while crcerie = 1. for the command response, crc is checked when the rty4 in rsptyr is enabled. err 1 dteri 0 r/w data time out error interrupt flag 0: no interrupt [clearing condition] write 0 after reading dteri = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when a data timeout error specified in dtoutr occurs while dterie = 1. err 0 cteri 0 r/w command timeout error interrupt flag 0: no interrupt [clearing condition] write 0 after reading cteri = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when a command timeout error specified in tocr occurs while cterie = 1. err
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 884 of 1286 rej09b0158-0100 ? bit: initial value: r/w: 7654321 0 00000 0 0 r frdy _tu frdyi r r r r r r r/w ?????? ? bit bit name initial value r/w description interrupt output 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? 1 frdy_tu undefined r fifo ready flag regardless of set values of dmaen and frdyie, this bit is read as 0 when fifo data amount matches the condition set in dmacr[2:0], and otherwise, read as 1. ? 0 frdyi 0 r/w fifo ready interrupt flag 0: no interrupt [clearing condition] write 0 after reading frdyi = 1. (writing 1 is invalid) 1: interrupt requested [setting condition] when remained fifo data does not match the assert condition set in dmacr while dmaen = 1 and frdyie = 1. note: frdyi will be set on the setting condition after clearing. to clear it, disable the flag setting by frdyie in intcr2. frdy
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 885 of 1286 rej09b0158-0100 24.3.7 transfer clock control register (clkon) clkon controls the transfer clock frequency and clock on/off. at this time, use a sufficiently slow clock for transfer through open-drain type output in mmc mode. in a command sequence, do not perform clock on/off or frequency modification. bit: initial value: r/w: 7654321 0 00000 00 0 r/w clkon csel2 csel1 csel0 r r r r/w r/w r/w r/w ??? csel3 bit bit name initial value r/w description 7 clkon 0 r/w clock on 0: fixes the transfer clock output from the mcclk pin to low level. 1: outputs the transfer clock from the mcclk pin. 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 csel3 csel2 csel1 csel0 0 0 0 0 r/w r/w r/w r/w transfer clock frequency select 0000: reserved 0001: uses the 1/2-divided peripheral clock as a transfer clock. 0010: uses the 1/4-divided peripheral clock as a transfer clock. 0011: uses the 1/8-divided peripheral clock as a transfer clock. 0100: uses the 1/16-divided peripheral clock as a transfer clock. 0101: uses the 1/32-divided peripheral clock as a transfer clock. 0110: uses the 1/64-divided peripheral clock as a transfer clock. 0111: uses the 1/128-divided peripheral clock as a transfer clock. 1000: uses the 1/256-divided peripheral clock as a transfer clock. 1001 to 1111: setting prohibited note: to output transfer clock, it is necessary to set the clkon bit to 1, and set the csel[3:0] bits other than 0000 and 1001 to 1111.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 886 of 1286 rej09b0158-0100 24.3.8 command timeout control register (ctocr) ctocr specifies the period to generate a timeout for the command response. the counter (ctoutc), to which the peripheral bus does not have access, counts the transfer clock to monitor the command timeout. the initial value of ctoutc is 0, and ctoutc starts counting the transfer clock from th e start of command transmission . ctoutc is cleared and stops counting the transfer clock when command response reception has been completed, or when the command sequence has been aborted by setting the cmdoff bit to 1. when the command response cannot be received, ctoutc continues counting the transfer clock, and enters the command timeout error state when th e number of transfer clock cycles reaches the number specified in ctocr. when the cterie bit in intcr1 is set to 1, the cteri flag in intstr1 is set. as ctoutc continues counting tr ansfer clock, the cteri flag setting condition is repeatedly generated. to perform command timeout error handling, the command sequence should be aborted by setting the cmdoff bit to 1, and then the cteri flag should be cleared to prevent extra-interrupt generation. bit: initial value: r/w: 7654321 0 00000001 r ctsel0 ? r r r r r r r/w ????? ? bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 ctsel0 1 r/w command timeout select 0: 128 transfer clock cycles from command transmission completion to response reception completion 1: 256 transfer clock cycles from command transmission completion to response reception completion note: if r2 response (17-byte command response) is requested and ctsel0 is cleared to 0, a timeout is generated during response rec eption. therefore, set ctsel0 to 1.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 887 of 1286 rej09b0158-0100 24.3.9 transfer byte number count register (tbcr) tbcr is an 8-bit readable/writable register that specifies the number of bytes to be transferred (block size) for each single block transfer co mmand. tbcr specifies the number of data block bytes not including the start bit, end bit, and crc. the multiple block transfer command corresponds to the number of bytes of each data block. this setting is ignored by the stream transfer command. bit: initial value: r/w: 7654321 0 00000000 r c2 c3 c1 c0 r r r r/w r/w r/w r/w ??? ? bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 cs3 cs2 cs1 cs0 0 0 0 0 r/w r/w r/w r/w transfer data block size four or more bytes should be set before executing a command with data transfer. 0000: 1 byte (for forced erase) 0001: 2 bytes 0010: 4 bytes 0011: 8 bytes 0100: 16 bytes 0101: 32 bytes 0110: 64 bytes 0111: 128 bytes 1000: 256 bytes 1001: 512 bytes 1010: 1024 bytes 1011: 2048 bytes 1100 to 1111: setting prohibited
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 888 of 1286 rej09b0158-0100 24.3.10 mode register (moder) moder is an 8-bit readable/writable register that specifies the mmcif operating mode. the following sequence should be repeated when th e mmcif uses the multimedia card: send a command, wait for the end of the command sequence and the end of the data busy state, and send a next command. the series of operations from command sending, command response reception, data transmission/reception, and data response rece ption is called as the command sequence. the command sequence starts from sending a command by setting the start bit in cmdstrt to 1, and ends when all necessary data transmission /reception and response reception have been completed. the multimedia card supports the data busy state such that only the specific command is accepted to write/erase data to/from the flash memo ry in the card during command sequence execution and after command sequence execution has ended. the data busy state is indicated by a low level output from the card side to the mcdat pin. bit: initial value: r/w: 7654321 0 00000000 r mode r r r r r r r/w ? ?? ?? ? ? bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 mode 0 r/w operating mode specifies the mmcif operating mode. 0: operates in mmc mode 1: setting prohibited
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 889 of 1286 rej09b0158-0100 24.3.11 command type register (cmdtyr) cmdtyr is an 8-bit readable/writable register that specifies the comman d format in conjunction with rsptyr. bits ty1 and ty0 specify the existence and direction of transfer data, and bits ty6 to ty2 specify the additional settings. all of bits ty6 to ty2 should be cleared to 0 or only one of them should be set to 1. bits ty6 to ty2 can only be set to 1 if the corresponding settings in ty1 and ty0 allow that setting. if these bits are not set correctly, the operation cannot be guaranteed. when executing a single block transaction, set ty1 and ty0 to 01 or 10, and ty6 to ty2 to all 0s. bit: initial value: r/w: 7654321 0 00000000 r ty4 ty3 ty2 ty1 ty0 r/w r/w r/w r/w r/w r/w r/w ty6 ? ty5 bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 ty6 0 r/w type 6 specifies a predefined multiple block transaction. ty[1:0] should be set to 01 or 10. when using the command set to this bit, it is necessary to specify the transfer block size and the transfer block number in the tbcr and tbncr respectively. 5 ty5 0 r/w type 5 specifies a multiple block transaction when using secure mmc. ty[1:0] should be set to 01 or 10. using the command to set to this bit, it is necessary to specify the transfer block size and the transfer block number in the tbcr and tbncr respectively. 4 ty4 0 r/w type 4 set this bit to 1 when specifying the cmd12 command. bits ty1 and ty0 should be set to 00.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 890 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 ty3 0 r/w type 3 set this bit to 1 when specifying stream transfer. bits ty1 and ty0 should be set to 01 or 10. the command sequence of the stream transfer specified by this bit ends when it is aborted by the cmd12 command. 2 ty2 0 r/w type 2 set this bit to 1 when specifying a multiple block transfer. bits ty1 and ty0 should be set to 01 or 10. the command sequence of the multiple block transfer specified by this bit ends when it is aborted by the cmd12 command. 1 0 ty1 ty0 0 0 r/w r/w types 1 and 0 these bits specify the ex istence and direction of transfer data. 00: a command without data transfer 01: a command with read data reception 10: a command with write data transmission 11: setting prohibited 24.3.12 response type register (rsptyr) rsptyr is an 8-bit readable/writable register that specifies command format in conjunction with cmdtyr. bits rty2 to rty0 specify the number of response bytes, and bits rty5 and rty4 specify the additional settings. bit: initial value: r/w: 7654321 0 00000000 r rty5 rty4 rty2 rty1 rty0 r r/w r/w r r/w r/w r/w ? ??
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 891 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7, 6 ? all 0 r reserved this bit is always read as 0. the write value should always be 0. 5 rty5 0 r/w response type 5 sets data busy status from the mmc card. 0: a command without data busy 1: a command with data busy 4 rty4 0 r/w response type 4 specifies that the command response crc is checked through crc7. bits rty2 to rty0 should be set to 100. 0: does not check crc through crc7 1: checks crc through crc7 3 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 rty2 rty1 rty0 0 0 0 r/w r/w r/w response types 2 to 0 these bits specify the number of command response bytes. 000: a command needs no command response. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: a command needs 6-byte command responses. specified by r1, r1b, r3, r4, and r5 responses. 101: a command needs a 17-byte command response. specified by r2 response. 110: setting prohibited 111: setting prohibited note: when checking r2 response, read the value of rspr0 to rspr16 after receiving the response and check them by software.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 892 of 1286 rej09b0158-0100 table 24.5 summarizes the correspondence between the commands described in the multimediacard system specification version 3.1 and the settings of the cmdtyr and rsptyr registers. table 24.5 correspondence between commands and settings of cmdtyr and rsptyr cmd cmdtyr rsptyr index abbreviation resp ty6 ty5 ty4 t y3 ty2 ty[1:0] rty5 rty4 rty[2:0] cmd0 go_idle_state ? 00 000 cmd1 send_op_cond r3 00 100 cmd2 all_send_cid r2 00 101 cmd3 set_relative_addr r1 00 * 4 100 cmd4 set_dsr ? 00 000 cmd7 select/deselect_card r1b 00 1 * 4 100 cmd9 send_csd r2 00 101 cmd10 send_cid r2 00 101 cmd11 read_dat_until_stop r1 1 01 * 4 100 cmd12 stop_transmission r1b 1 00 1 * 4 100 cmd13 send_status r1 00 * 4 100 cmd15 go_inactive_state ? 00 000 cmd16 set_blocklen r1 00 * 4 100 cmd17 read_single_block r1 * 3 01 * 4 100 cmd18 read_multiple_block r1 * 2 * 2 01 * 4 100 cmd20 write_dat_until_stop r1 1 10 * 4 100 cmd23 set_block_count r1 00 * 4 100 cmd24 write_block r1 * 3 10 * 4 100 cmd25 write_multiple_block r1 * 2 * 2 10 * 4 100 cmd26 program_cid r1 10 * 4 100 cmd27 program_csd r1 10 * 4 100 cmd28 set_write_prot r1b 00 1 * 4 100 cmd29 clr_write_prot r1b 00 1 * 4 100 cmd30 send_write_prot r1 01 * 4 100
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 893 of 1286 rej09b0158-0100 cmd cmdtyr rsptyr index abbreviation resp ty6 ty5 ty4 t y3 ty2 ty[1:0] rty5 rty4 rty[2:0] cmd32 * 1 tag_sector_start r1 00 * 4 100 cmd33 * 1 tag_sector_end r1 00 * 4 100 cmd34 * 1 untag_sector r1 00 * 4 100 cmd35 tag_erase_group_ start r1 00 * 4 100 cmd36 tag_erase_group_end r1 00 * 4 100 cmd37 * 1 untag_erase_group r1 00 * 4 100 cmd38 erase r1b 00 1 * 4 100 cmd39 fast_io r4 00 * 4 100 cmd40 go_irq_state r5 00 * 4 100 cmd42 lock_unlock r1b 10 1 * 4 100 cmd55 app_cmd r1 00 * 4 100 cmd56 gen_cmd r1b * 5 1 * 4 100 notes: a blank: means value 0. 1. these commands are not supported after mmca ver3.1 specification cards. 2. set the ty6 bit and clear the ty2 bit when the transfer block number is set in advance, clear the ty6 bit and set the ty2 bit when the transfer block number is not set. 3. set this bit when using secu re mmc multiple block transaction. 4. set this bit when checking crc of comm and and response other than r2. note that it is impossible to check crc of r2. 5. set these bits to 01 in read and 10 in write access.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 894 of 1286 rej09b0158-0100 24.3.13 transfer block number counter (tbncr) a value other than 0 must be written to the tbncr register if a multiple block transfer is selected through the ty5 and ty6 bits in the cmdtyr. set the transfer block number in the tbncr. the value of tbncr is decremente d by one as each block transfer is executed and the command sequence ends when the tbncr value equals 0. tbncr bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 15 to 0 t bncr all 0 r/w transfer block number counter [clearing condition] when the specified number of blocks are transferred or 0 is written to tbncr.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 895 of 1286 rej09b0158-0100 24.3.14 response registers 0 to 16, d (rspr0 to rspr16, rsprd) rspr0 to rspr16 are command response registers, which are seventeen 8-bit registers. rsprd is an 8-bit crc status register. the number of command response bytes differs according to the command. the number of command response bytes can be specified by r sptyr in the mmcif. the command response is shifted-in from bit 0 in rspr16, and shifte d to the number of command response bytes mmc mode response rspr registers 6 bytes (r1, r1b, r3, r4, r5) 17 bytes (r2) rspr0 ? 1st byte rspr1 ? 2nd byte rspr2 ? 3rd byte rspr3 ? 4th byte rspr4 ? 5th byte rspr5 ? 6th byte rspr6 ? 7th byte rspr7 ? 8th byte rspr8 ? 9th byte rspr9 ? 10th byte rspr10 ? 11th byte rspr11 1st byte 12th byte rspr12 2nd byte 13th byte rspr13 3rd byte 14th byte rspr14 4th byte 15th byte rspr15 5th byte 16th byte rspr16 6th byte 17th byte rspr0 to rspr16 are simple shift registers. a command response that has been shifted in is not automatically cleared, and it is continuously shifted until it is shifted out from bit 7 in rspr0. to clear unnecessary bytes to h'00, write an arbitrary value to each rspr.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 896 of 1286 rej09b0158-0100 clearing an rspr is completed two transfer clock cycles after an ar bitrary value is written to the rspr. ? bit: initial value: r/w: 76543210 00000000 r/w rspr r/w r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 7 to 0 rspr h'00 r/w these bits are clear ed to h'00 by writing an arbitrary value. rspr0 to rspr16 comprise a continuous 17-byte shift register. ? bit: initial value: r/w: 7654321 0 00000000 r rsprd r r r/w r/w r/w r/w r/w ?? ? bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 to 0 rsprd 00000 r/w crc status [clearing condition] when writing any value to these bits, cleared to 00000. crc status is stored. crc status is command response from the card when data is written into the mmc card.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 897 of 1286 rej09b0158-0100 24.3.15 data timeout register (dtoutr) dtoutr specifies the period to generate a data timeout. the 16-bit counter (dtoutc) and a prescaler, to which the peripheral bus does not have access, count the peri pheral clock to monitor the data timeout. the prescaler always counts the peripheral clock, and outputs a count pulse for every 10,000 peripheral clock cy cles. the initial value of dtou tc is 0, and dtoutc starts counting the prescaler output from the start of the command sequ ence. dtoutc is cleared when the command sequence has ended, or when the command sequence has been aborted by setting the cmdoff bit to 1, after which the dtoutc stops counting the prescaler output. when the command sequence does not end, dt outc continues counting the prescaler output, and enters the data timeout error states when th e number of prescaler out puts reaches the number specified in dtoutr. when the dterie bit in in tcr1 is set to 1, the dteri flag in intstr1 is set. as dtoutc continues counting prescaler output, the dteri flag setting condition is repeatedly generated. to perform data timeout error handling, the command sequence should be aborted by setting the cmdoff bit to 1, and then the dteri flag should be cleared to prevent extra-interrupt generation. for a command with data busy status, data timeout cannot be monitored since the command sequence is terminated before entering the data busy state. timeout in th e data busy state should be monitored by firmware. dtoutr bit: initial value: r/w: 1514131211109876543210 1111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit bit name initial value r/w description 15 to 0 dtoutr all 1 r/w data timeout time/10,000 data timeout time: pe ripheral clock cycle dtoutr setting value 10,000.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 898 of 1286 rej09b0158-0100 24.3.16 data register (dr) dr is a register for reading/writing fifo data. word/byte access is enabled to addresses of this register. dr bit: initial value: r/w: 1514131211109876543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ???????? ?? ? ?? ? ?? bit bit name initial value r/w description 15 to 0 dr undefined r/w register for reading/writing fifo data. word/byte access is enabled. when dr is accessed in words, the upper and lower bytes are transmitted or received in that order. word access and byte access can be done in random order. however, (dr address + 1) cannot be accessed in bytes. the following shows ex amples of dr access. when data is written to dr in the following steps 1 to 4, the transmit data is stored in the fifo as shown in figure 24.2. 1. write word data h'0123 to dr. 2. write byte data h'45 to dr. 3. write word data h'6789 to dr. 4. write byte data h'ab to dr. when the receive data is stored in the fifo as shown in figure 24.2 (for example, after data is started to be received while the fifo is empty and data is received in the order of h'01, h'23, ..., h'ab), data can be read from dr in the following steps 5 to 8. 5. read byte data h'01 from dr. 6. read word data h'2345 from dr. 7. read byte data h'67 from dr. 8. read word data h'89ab from dr.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 899 of 1286 rej09b0158-0100 h'01 1 word (2 bytes) 64 words h'23 h'45 . . . . . . h'67 h'89 fifo h'ab figure 24.2 dr access example 24.3.17 fifo pointer clear register (fifoclr) the fifo write/read pointer is cleared by writing an ar bitrary value to fifoclr. bit: initial value: r/w: 76543210 00000000 w fifoclr ww ww www bit bit name initial value r/w description 7 to 0 fifoclr h'00 w the fifo pointer is cleared by writing an arbitrary value to this register.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 900 of 1286 rej09b0158-0100 24.3.18 dma contro l register (dmacr) dmacr sets dma request signal output. dmaen enables or disables a dma request signal. the dma request signal is output based on a value that has been set to set2 to set0. bit: initial value: r/w: 7654321 0 00000 0 00 r/w dmaen set2 set1 set0 r/w r r r r/w r/w r/w auto ??? bit bit name initial value r/w description 7 dmaen 0 r/w dma enable 0: disables output of dma request signal. 1: enables output of dma request signal. 6 auto 0 r/w auto mode for pre-defin ed multiple block transfer using dma transfer 0: disable auto mode 1: enable auto mode 5 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 set2 set1 set0 0 0 0 r/w r/w r/w dma request signal assert condition sets dma request signal assert condition. 000: not output 001: fifo remained data is 1/4 or less of fifo capacity. 010: fifo remained data is 1/2 or less of fifo capacity. 011: fifo remained data is 3/4 or less of fifo capacity. 100: fifo remained data is 1 byte or more. 101: fifo remained data is 1/4 or more of fifo capacity. 110: fifo remained data is 1/2 or more of fifo capacity. 111: fifo remained data is 3/4 or more of fifo capacity.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 901 of 1286 rej09b0158-0100 24.4 operation the multimedia card is an external storage media that can be easily connected or disconnected. the mmcif operates in mmc mode. insert a card and supply power to it. then operate the mmcif by applying the transfer clock after setting an appropriate transfer clock frequency. do not connect or disconnect the card during command sequence execution or in the data busy state. 24.4.1 operations in mmc mode mmc mode is an operating mode in which the transfer clock is output from the mcclk pin, command transmission/respons e receive occurs via the mccmd pin, and data is transmitted/received via the mcdat pin. in this mode the next command can be issued while data is being transmitted/received. this feature is efficient for multiple block or stream transfer. in this case, the next command is the cmd12 command, which aborts the current command sequence. in mmc mode, broadcast commands that simultane ously issue commands to multiple cards are supported. after information of the inserted cards is recognized by a broadcast command, a relative address is given to each card. one card is selected by the relative address, other cards are deselected, and then various commands are issued to the selected card. commands in mmc mode are basically classified into thre e types: broadcast, relative address, and flash memory operation commands. the card can be operated by issuing these commands appropriately accordin g to the card state. (1) operation of broadcast commands cmd0, cmd1, cmd2, and cmd4 are broadcas t commands. these commands and the cmd3 command comprise a sequence assigning relative addresses to individual cards. in this sequence, the cmd output format is open drain, and the command response is wired-or. during the issuance of this command sequence, the transfer clock frequency should be set to a sufficiently low value.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 902 of 1286 rej09b0158-0100 ? ? ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 903 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) cstr (cwre) (busy) (req) input/output pins command output (48 bits) command transmission started command transmission ended cleared by software command transmission period command sequence period figure 24.3 example of co mmand sequence for commands not requiring command response
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 904 of 1286 rej09b0158-0100 ye s start of command sequence set command data to cmdr0 to cmdr4 set command type to cmdtyr set command response type to rsptyr set the start bit in cmdstrt to 1 (cmdi) interrupt detected? end of command sequence no figure 24.4 example of operational flow for commands not requiring command response (4) operation of commands without data transfer broadcast, relative address, and flash memo ry operation commands include a number of commands that do not include da ta transfer. such commands execute the desired data transfer using command arguments and command responses. for a command that is related to time- consuming processing such as flash memory write/erase, the car d indicates the data busy state via the mcdat. figures 24.5 and 24.6 show examples of the command sequence for commands without data transfer. figure 24.7 shows the operational flow for commands without data transfer. ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 905 of 1286 rej09b0158-0100 ? ? ? ? ? mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) cstr (busy) (cwre) (req) (crpi) (dbsyi) (dtbusy_tu) (dtbusy) input/output pins command output (48 bits) command transmission started command response reception (no busy state) command transmission period command sequence execution period response reception completed figure 24.5 example of command seque nce for commands wi thout data transfer (no data busy state)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 906 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) cstr (cwre) (busy) (req) (crpi) (dbsyi) (dtbusy_tu) (dtbusy) input/output pins command output (48 bits) command transmission started command response reception command transmission period command sequence execution period response reception completed data busy period busy state completed (busy state) figure 24.6 example of command sequen ce for commands with out data transfer (with data busy state)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 907 of 1286 rej09b0158-0100 start of command sequence set command data to cmdr0 to cmdr4 set command type to cmdtyr set command response type to rsptyr set the start bit in cmdstrt to 1 ye s no (crceri) interrupt detected? ye s no (crpi) interrupt detected? ye s no r1b response? ye s no dtbusy detected? ye s no ye s no (dbsyi) interrupt detected? end of command sequence (cteri) interrupt detected? write cmdoff to 1 figure 24.7 example of operational flow for commands without data transfer
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 908 of 1286 rej09b0158-0100 (5) commands with read data flash memory operation commands include a nu mber of commands involving read data. such commands confirm the card status by the command argument and command response, and receive card information and flash memory data from the mcdat pin. in multiple block transfer, two transfer methods can be used; one is open-ended and another one is pre-defined. open-ended operation is suspended for each block transfer and an instruction to continue or end the command sequence is waited for. for pre-defined operation, the block number of the transmission is set before transfer. when the fifo is full between blocks in multip le block transfer, the command sequence is suspended. once the command sequ ence is suspended, process th e data in fifo if necessary before allowing the command sequence to continue. note: in multiple block transfer, when the co mmand sequence is ended (the cmdoff bit is written to 1) before command response r eception (crpi), the command response may not be received correctly. therefore, to receive the command response correctly, the command sequence must be continued (set the rd_cont bit to 1) until the command response reception ends. figures 24.8 to 24.11 show examples of the command sequence for commands with read data. figures 24.12 to 24.14 show the operational flows for commands with read data. ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 909 of 1286 rej09b0158-0100 ? ? ? mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (fifo_full) cmd17 (read_single_block) opcr (rd_conti) input/output pins command command response read data command transmission started single block read command execution sequence figure 24.8 example of command sequence for commands with read data (block size
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 910 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (fifo_full) cmd17 (read_single_block) opcr (rd_conti) input/output pins transfer clock transmission halted transfer clock transmission resumed command response command block data reception suspended read data read data block data reception resumed reading data from fifo single block read command execution sequence command transmission started figure 24.9 example of command sequence for commands with read data (block size > fifo size)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 911 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (bti) (fifo_full) cmd18(read_multiple_block) cmd12 (stop_transmission) opcr (rd_conti) input/output pins transfer clock transmission halted transfer clock transmission resumed read data block data reception ended multiblock read command execution sequence stop command execution sequence command command command transmission started command response read data read data command response figure 24.10 example of command sequence for commands with read data (multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 912 of 1286 rej09b0158-0100 cmd11 (read_dat_until_stop) cmd12 (stop_transmission) input/output pins transfer clock transmission resumed transfer clock transmission resumed stop command execution sequence data reception resumed data reception ended read data from fifo stream read command execution sequence mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (bti) (fifo_full) opcr (rd_conti) command read data read data read data command response command command response command transmission started transfer clock transmission halted data reception suspended figure 24.11 example of command sequence for commands with read data (stream transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 913 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 read response register execute cmd17 (cmdr to cmdstrt) set the number of transfer block size to (tbcr) no ye s (crceri) interrupt detected? ye s no cmd16 normal end? ye s no (crpi) inte rrupt detected? ye s no response status normal ended? ye s no end of command sequence (cteri) interrupt detected? ye s no (ffi) interrupt detected? set the cmdoff to 1 read data from fifo set the rd_conti to 1 read data from fifo no ye s (dteri) interrupt detected? no ye s (crceri) interrupt detected? no ye s [legend] len: block length[byte] cap: fifo size[byte] n (ffi): number of ffi from read sequence starts (dteri) interrupt detected? ye s no (dti) interrupt detected? ye s no cap len - cap n (ffi) set the cmdoff to 1 clear fifo figure 24.12 example of operational flow for commands with read data (single block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 914 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 read response register execute cmd18 (cmdr to cmdstrt) set the number of transfer block size to (tbcr) no ye s (crceri) interrupt detected? ye s no cmd16 normal end? ye s no (crpi) interrupt detected? ye s no response status normal ended? ye s no (cteri) interrupt detected? 12 figure 24.13 example of operational flow for commands with read data (1) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 915 of 1286 rej09b0158-0100 end of command sequence ye s no (ffi) interrupt detected? set the cmdoff to 1 read data from fifo set the rd_conti to 1 read data from fifo no ye s (dteri) interrupt detected? no ye s (crceri) interrupt detected? no ye s [legend] len: block length[byte] cap: fifo size[byte] n (ffi): number of ffi from read sequence starts n (dti): number of dti from read sequence start (dteri) interrupt detected? ye s no next block read? ye s no (dti) interrupt detected? ye s no cap len (1 + n (dti)) - cap n (ffi) set the cmdoff to 1 execute cmd12 set the cmdoff to 1 execute cmd12 clear fifo 12 figure 24.13 example of operational flow for commands with read data (2) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 916 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 read response register execute cmd18 (cmdr to cmdstrt) set the number of transfer block size to (tbcr) no ye s (crceri) interrupt detected? ye s no cmd16 normal end? execute cmd23 set the number of transfer block (tbncr) ye s no cmd23 normal end? ye s no (crpi) interrupt detected? ye s no response status normal ended? ye s no (cteri) interrupt detected? 12 figure 24.13 example of operational flow for commands with read data (3) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 917 of 1286 rej09b0158-0100 end of command sequence ye s no (ffi) interrupt detected? set the cmdoff to 1 read data from fifo set the rd_conti to 1 no ye s (dteri) interrupt detected? no ye s (crceri) interrupt detected? no ye s [legend] len: block length[byte] cap: fifo size[byte] n (ffi): number of ffi from read sequence starts n (dti): number of dti from read sequence start (dteri) interrupt detected? ye s no (bti) interrupt detected? ye s no (dti) interrupt detected? ye s no cap len (1 + n (dti)) - cap n (ffi) ye s no tbncr value = n (dti) ? set the cmdoff to 1 execute cmd12 read data from fifo set the cmdoff to 1 clear fifo 12 figure 24.13 example of operational flow for commands with read data (4) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 918 of 1286 rej09b0158-0100 start of command sequence clear fifo read response register execute cmd11 (cmdr to cmdstrt) no ye s (crceri) inte rrupt detected? ye s no (crpi) inte rrupt detected? ye s no response status normal ended? ye s no end of command sequence (cteri) interrupt detected? ye s no (ffi) interrupt detected? set the cmdoff to 1 read data from fifo set the rd_conti to 1 no ye s (dteri) inte rrupt detected? ye s no data read completed? set the cmdoff to 1 execute cmd12 execute cmd12 read data from fifo set the cmdoff to 1 clear fifo figure 24.14 example of operational flow for commands with read data (stream transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 919 of 1286 rej09b0158-0100 (6) commands with write data flash memory operation commands include a number of commands involving write data. such commands confirm the card status by the co mmand argument and command response, and transmit card information and flash memory data via the mcdat pin. for a command that is related to time-consuming processing such as flash memory write, the card indicates the data busy state via the mcdat pin. in multiple block transfer, two tr ansfer methods can be used; one is open-ended and the other is pre-defined. open-ended operation is suspended for each block transfer and an instruction to continue or end the command sequence is waited for. for pre-defined operation, the block number of the transmission is set before transfer. when the fifo is full between blocks in multiple block transfer, the command sequence is suspended. once the command sequ ence is suspended, process th e data in fifo if necessary before allowing the command sequence to continue. figures 24.15 to 24.18 show examples of the command sequence for comm ands with write data. figures 24.19 to 24.21 show the operational flows for commands with write data. ? ? ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 920 of 1286 rej09b0158-0100 ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 921 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy) (dtbusy_tu) (req) (crpi) (dti) (dbsyi) (fei) (fifo_empty) cmd24 (write_single_block) opcr (dataen) (drpi) input/output pins command command response command transmission started single block write command execution sequence write data status busy figure 24.15 example of command se quence for commands with write data (block size
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 922 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy) (dtbusy_tu) (req) (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) cmd24(write_single_block) opcr (dataen) input/output pins command command response command transmission started busy transfer clock transmission halted transfer clock transmission resumed block data transmission suspended writing data to fifo write data write data block data transmission resumed single block write command execution sequence figure 24.16 example of command se quence for commands with write data (block size > fifo size)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 923 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy) (dtbusy_tu) (req) (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) cmd25 write_multipe_block cmd12(stop_transmission) opcr (dataen) input/output pins write data write data write data status status block data transmission started block data reception ended next block data transmission started stop command execution sequence command command response command command response command transmission started figure 24.17 example of command se quence for commands with write data (multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 924 of 1286 rej09b0158-0100 mcclk mccmd mcdat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy) (dtbusy_tu) (req) (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) cmd20 (write_dat_until_stop) cmd12(stop_transmission) opcr (dataen) input/output pins command command response command stop command execution sequence busy transfer clock trans- mission halted transfer clock trans- mission halted transfer clock transmission resumed transfer clock transmission resumed writing data to fifo data transmission suspended data transmission suspended data transmission resumed data transmission ended stream write command execution sequence command response command transmission started write data write data write data figure 24.18 example of command se quence for commands with write data (stream transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 925 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 read response register execute cmd24 (cmdr to cmdstrt) set the number of transfer block size to tbcr no ye s (crceri) interrupt detected? ye s no cmd16 normal end? ye s no (crpi) interrupt detected? ye s no no response status normal ended? ye s no end of command sequence (cteri) interrupt detected? set the cmdoff to 1 writing data to fifo set the dataen to 1 ye s (dtbusy) detected? ye s (dbsyi) interrupt detected? no ye s (crceri) interrupt detected? no ye s [legend] len: block length[byte] cap: fifo size[byte] n (fei): number of fei from read sequence starts (dteri) interrupt detected? ye s no (drpi) interrupt detected? ye s cap n (fei) len no no ye s (dti) interrupt detected? no ye s (fei) interrupt detected? no figure 24.19 example of operational flow for commands with write data (single block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 926 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 read response register execute cmd25 (cmdr to cmdstrt) set the number of transfer block size to tbcr no ye s (crceri) interrupt detected? ye s no cmd16 normal end? ye s no (crpi) interrupt detected? ye s no response status normal ended? ye s no (cteri) interrupt detected? 12 figure 24.20 example of operational fl ow for commands with write data (1) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 927 of 1286 rej09b0158-0100 no end of command sequence writing data to fifo set the dataen to 1 ye s no next block write? ye s (dtbusy) detected? ye s (dbsyi) interrupt detected? no ye s * (crceri) interrupt detected? no ye s note: * write data for block size (block size < or = fifo size) or for fifo size (block size > fifo size). len: block length[byte] cap: fifo size[byte] n (fei): number of fei from read sequence starts n (drpi): number of drpi from write sequence starts [legend] (dteri) interrupt detected? ye s no (drpi) interrupt detected? ye s cap n (fei) - len (1 + n (dti)) len no no ye s (dti) interrupt detected? no ye s (fei) interrupt detected? no set the cmdoff to 1 set the cmdoff to 1 execute cmd12 12 figure 24.20 example of operational fl ow for commands with write data (2) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 928 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set the number of block to tbncr read response register execute cmd25 (cmdr to cmdstrt) set the number of transfer block size to tbcr no ye s (crceri) interrupt detected? ye s no cmd16 normal end? ye s no (crpi) interrupt detected? ye s no response status normal ended? ye s no (cteri) interrupt detected? execute cmd 23 ye s no cmd 23 normal end? 12 figure 24.20 example of operational fl ow for commands with write data (3) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 929 of 1286 rej09b0158-0100 no end of command sequence writing data to fifo set the dataen to 1 ye s (dtbusy) detected? ye s (dbsyi) interrupt detected? no ye s * (crceri) interrupt detected? no ye s note: * write data for block size (block size < or = fifo size) or for fifo size (block size > fifo size). len: block length[byte] cap: fifo size[byte] n (fei): number of fei from read sequence starts n (drpi): number of drpi from write sequence starts [legend] (dteri) interrupt detected? ye s no (drpi) interrupt detected? ye s cap n (fei) - len (1 + n (drpi)) len no no ye s tbncr = n(drpi)? no ye s (bti) interrupt detected? no ye s (dti) interrupt detected? no ye s (fei) interrupt detected? no set the cmdoff to 1 set the cmdoff to 1 set the cmdoff to 1 execute cmd12 12 figure 24.20 example of operational fl ow for commands with write data (4) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 930 of 1286 rej09b0158-0100 start of command sequence clear fifo read response register execute cmd20 (cmdr to cmdstrt) no ye s (crceri) interrupt detected? ye s no (crpi) interrupt detected? ye s no response status normal ended? ye s no (cteri) interrupt detected? end of command sequence writing data to fifo set the dataen to 1 ye s no all data write to fifo completed? ye s (fei) interrupt detected? no set the cmdoff to 1 set the cmdoff to 1 execute cmd12 figure 24.21 example of operational flow for commands with write data (stream transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 931 of 1286 rej09b0158-0100 24.5 mmcif interrupt sources table 24.7 lists the mmcif interrupt sources. the interrupt sources ar e classified into four groups, and four interrupt vectors are assigned. each interrupt source can be individually enabled by the enable bits in intcr0 to intcr2. disabled interrupt sources do not set the flag. table 24.7 mmcif interrupt sources name interrupt source interrupt flag fifo empty fei fstat fifo full ffi data response drpi data transfer end dti command response receive end crpi command transmit end cmdi tran data busy end dbsyi crc error crceri * data timeout error dteri err command timeout error cteri frdy fifo ready frdyi note: except for crc error of r2 command and response.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 932 of 1286 rej09b0158-0100 24.6 operations when using dma 24.6.1 operation in read sequence in order to transfer data in fifo with the dmac, set mmcif (dmacr) after setting the dmac*. transmit the read command after setting dmacr. figure 24.22 to 24.24 shows the operational flow for a read sequence. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 933 of 1286 rej09b0158-0100 ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 934 of 1286 rej09b0158-0100 start of command sequence end of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register set the dmacr to h'84 clear the dmacr to h'00 set the cmdoff to 1 clear the dmacr to h'00 cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (dti) interrupt detected? no ye s dma transfer end? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd17 (cmdr to cmdstrt) set the cmdoff to 1 clear the dmacr to h'00 clear fifo figure 24.22 example of read sequence flow (single block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 935 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd 18 (cmdr to cmdstrt) 1 2 figure 24.23 example of read sequence flow (1) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 936 of 1286 rej09b0158-0100 end of command sequence set the dmacr to h'84 clear the dmacr to h'00 set the cmdoff to 1 clear the dmacr to h'00 execute cmd12 set the cmdoff to 1 (dti) interrupt detected? no ye s dma transfer end? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no next block read? no ye s 12 set rd_conti to 1 set the cmdoff to 1 clear the dmacr to h'00 clear fifo execute cmd12 figure 24.23 example of read sequence flow (2) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 937 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr set the number of block to tbncr execute cmd 18 (cmdr to cmdstrt) execute cmd 23 cmd 23 normal end? no ye s 1 2 figure 24.23 example of read sequence flow (3) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 938 of 1286 rej09b0158-0100 end of command sequence set the dmacr to h'84 clear the dmacr to h'00 set the cmdoff to 1 clear the dmacr to h'00 set the cmdoff to 1 (dti) interrupt detected? no ye s dma transfer end? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no (bti) interrupt detected? no ye s tbncr = n (dti)? no ye s [legend] n (dti): number of dti from read sequence start 12 set rd_conti to 1 set the cmdoff to 1 clear the dmacr to h'00 clear fifo execute cmd12 figure 24.23 example of read sequence flow (4) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 939 of 1286 rej09b0158-0100 start of command sequence end of command sequence clear fifo set dmac-related condition set dmacr read response register set the cmdoff to 1 execute cmd12 set the cmdoff to 1 clear the dmacr to h'00 (crpi) interrupt detected? no ye s response status normal ended? no ye s dma transfer end? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no execute cmd11 (cmdr to cmdstrt) set the cmdoff to 1 execute cmd12 clear fifo figure 24.24 example of operational flow for stream read transfer
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 940 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr set the number of transfer block to tbncr execute cmd 18 (cmdr to cmdstrt) execute cmd 23 cmd 23 normal end? no ye s 1 2 figure 24.25 example of operational flow for auto-mode pre-defined multiple block read transfer (1)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 941 of 1286 rej09b0158-0100 end of command sequence set the dmacr to h'84 set the cmdoff to 1 clear the dmacr to h'00 clear the dmacr to h'00 clear fifo execute cmd12 set the cmdoff to 1 clear the dmacr to h'00 set the cmdoff to 1 (bti) interrupt detected? no ye s dma transfer end? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no 1 2 figure 24.25 example of operational flow for auto-mode pre-defined multiple block read transfer (2)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 942 of 1286 rej09b0158-0100 24.6.2 operation in write sequence to transfer data to fifo with the dmac, se t mmcif (dmacr) after setting the dmac. then, start transfer to the card after a fifo ready interrupt. figure 24.26 to 24.28 shows the operational flow for a write sequence. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 943 of 1286 rej09b0158-0100 ? ? ? ? ? ?
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 944 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd 24 (cmdr to cmdstrt) 1 2 figure 24.26 example of write sequ ence flow (1) (single block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 945 of 1286 rej09b0158-0100 end of command sequence set the cmdoff to 1 set the dataen bit to 1 (drpi) interrupt detected? no ye s (dbsyi) interrupt detected? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no (dtbusy) detected? no ye s (frdyi) interrupt detected or dma transfer end? no ye s clear the dmacr to h'00 dma transfer end? no ye s (dti) interrupt detected? no ye s 12 figure 24.26 example of write sequ ence flow (2) (single block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 946 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd 25 (cmdr to cmdstrt) 1 2 figure 24.27 example of write sequence flow (1) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 947 of 1286 rej09b0158-0100 end of command sequence set the dataen to 1 (drpi) interrupt detected? no ye s (dbsyi) interrupt detected? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no next block write? no ye s (dtbusy) detected? no ye s (frdyi) interrupt detected or dma transfer end? no ye s clear the dmacr to h'00 dma transfer end? no ye s (dti) interrupt detected? no ye s 12 set the cmdoff to 1 clear fifo clear the dmacr to h'00 execute cmd12 or tran set the cmdoff to 1 execute cmd12 or stop set the cmdoff to 1 figure 24.27 example of write sequence flow (2) (open-ended multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 948 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd 25 (cmdr to cmdstrt) 1 2 set the number of block to tbncr execute cmd 23 cmd 23 normal end? no ye s figure 24.27 example of write sequence flow (3) (pre-defined mult iple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 949 of 1286 rej09b0158-0100 end of command sequence set the dataen to 1 (drpi) interrupt detected? no ye s (dbsyi) interrupt detected? no ye s (crceri) interrupt detected? ye s no no (dteri) interrupt detected? ye s no (bti) interrupt detected? no ye s tbncr = n (drpi)? no ye s (dtbusy) detected? no ye s (frdyi) interrupt detected or dma transfer end? no ye s clear the dmacr to h'00 dma transfer end? ye s (dti) interrupt detected? no ye s 12 set the cmdoff to 1 clear fifo clear the dmacr to h'00 execute cmd12 or stop tran set the cmdoff to 1 set the cmdoff to 1 [legend] n (drpi): number of drpi from read sequence start figure 24.27 example of write sequence flow (4) (pre-defined multiple block transfer)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 950 of 1286 rej09b0158-0100 start of command sequence clear fifo set dmac-related condition set dmacr read response register (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no execute cmd 20 (cmdr to cmdstrt) end of command sequence set the dataen to 1 (frdyi) interrupt detected or dma transfer end? no ye s clear the dmacr to h'00 dma transfer end? no ye s (fei) interrupt detected? no ye s set the cmdoff to 1 execute cmd12 set the cmdoff to 1 figure 24.28 example of operational flow for stream write transfer
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 951 of 1286 rej09b0158-0100 start of command sequence clear fifo execute cmd16 set dmac-related condition set dmacr read response register cmd16 normal end? no ye s (crpi) interrupt detected? no ye s response status normal ended? no ye s (cteri) interrupt detected? no ye s (crceri) interrupt detected? ye s no set the number of transfer block size to tbcr execute cmd 25 (cmdr to cmdstrt) 1 2 set the number of block to tbncr execute cmd 23 cmd 23 normal end? no ye s figure 24.29 example of operational flow for auto-mode pre-defined multiple block write transfer (1)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 952 of 1286 rej09b0158-0100 end of command sequence (bti) interrupt detected? no ye s (dbsyi) interrupt detected? no ye s (crceri) interrupt detected? ye s no (dteri) interrupt detected? ye s no (dtbusy) detected? no ye s clear the dmacr to h'00 dma transfer end? no ye s 12 set the cmdoff to 1 clear fifo clear the dmacr to h'00 execute cmd12 or stop tran set the cmdoff to 1 set the cmdoff to 1 figure 24.29 example of operational flow for auto-mode pre-defined multiple block write transfer (2)
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 953 of 1286 rej09b0158-0100 24.7 register accesses with little endian specification when the little endian is speci fied, the access size for registers or that for memory where the corresponding data is stored should be fixed. for example, if data read from the mmcif with the word size is written to memory and then it is read from memory with the byte size, data misalignment occurs.
section 24 multimedia card interface (mmcif) rev.1.00 dec. 13, 2005 page 954 of 1286 rej09b0158-0100
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 955 of 1286 rej09b0158-0100 section 25 audio codec interface (hac) the hac, the audio codec digital controller interface, supports bidirectional data transfer which is a subset of audio codec 97 (ac'97) revision 2.1. the hac provides serial transmission to /reception from the ac97 codec. e ach channel of the hac can be connected to a single audio codec device. the hac carries out data extraction from/insertion into audio frames. for data slots within both receive and transmit frames, the pio transfer by the cpu or the dma tran sfer by the dmac can be used. 25.1 features the hac has the following features: ? supports digital interface to a subset of a single ac'97 revi sion 2.1 audio codec ? pio transfer of status slots 1 and 2 in rx frames ? pio transfer of command slots 1 and 2 in tx frames ? pio transfer of data slots 3 and 4 in rx frames ? pio transfer of data slots 3 and 4 in tx frames ? selectable 16-bit or 20-bit dma transfer of data slots 3 and 4 in rx frames ? selectable 16-bit or 20-bit dma transfer of data slots 3 and 4 in tx frames ? accommodates various sampling rates by qualifying slot data with tag bits and monitoring the tx frame request bits of rx frames ? generates data ready, data request, overrun and underrun interrupts ? supports cold reset, warm reset, and power-down mode
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 956 of 1286 rej09b0158-0100 figure 25.1 shows a block diagram of the hac. hac_res hac_sdout hac_sync hac_sdin hac_bitclk bit control signal contlol signal contlol signal interrupt request interrupt request internal bus interface (reception) internal bus interface (transmssion) hac receiver data[19:0] data[31:0] data[31:0] peripheral bus data[19:0] data[19:0] data[19:0] hac transmitter shift register for slot 1 shift register for slot 2 shift register for slot 3 shift register for slot 4 shift register for slot 1 shift register for slot 2 shift register for slot 3 shift register for slot 4 dma control dma control csar tx buffer csdr tx buffer pcml tx buffer pcmr tx buffer csar rx buffer csdr rx buffer pcml rx buffer pcmr rx buffer data[19:0] data[19:0] data[19:0] data[19:0] dma request dma request slot3, slot4 request signal figure 25.1 block diagram 25.2 input/output pins table 25.1 describes the hac pin configuration. table 25.1 pin configuration pin name i/o function hac_bitclk input hac serial data clock hac_sdin input hac serial data incoming to rx frame hac_sdout output hac serial data outgoing from tx frame hac_sync output hac frame sync hac_res output hac reset (negative logic signal) note: these pins are multiplexed with the siof, ssi and gpio pins.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 957 of 1286 rej09b0158-0100 25.3 register descriptions table 25.2 shows the hac register configuration. table 25.3 show s the register states in each processing mode. table 25.2 register configuration register name abbrev. r/w p4 address area 7 address size sync clock control and status register haccr r/w h'ffe4 0008 h'1fe4 0008 32 p ck command/status address register haccsar r/w h'ffe4 0020 h'1fe4 0020 32 p ck command/status data register haccsdr r/w h'ffe4 0024 h'1fe4 0024 32 p ck pcm left channel register hacpcml r/w h'ffe4 0028 h'1fe4 0028 32 p ck pcm right channel register hacpcmr r/w h'ffe4 0002c h'1fe4 002c 32 p ck tx interrupt enable register hactier r/w h'ffe4 0050 h'1fe4 0050 32 p ck tx status register hactsr r/w h'ffe4 0054 h'1fe4 0054 32 p ck rx interrupt enable register hacrier r/w h'ffe4 0058 h'1fe4 0058 32 p ck rx status register hacrsr r/w h'ffe4 005c h'1fe4 005c 32 p ck hac control register hacacr r/w h'ffe4 0060 h'1fe4 0060 32 p ck table 25.3 register states of hac in each processing mode register name abbrev. power-on reset by preset pin/wdt/ h-udi manual reset by wdt/ multiple exceptions sleep by sleep instruction module standby control and status register haccr h'0000 0200 h'0000 0200 retained retained command/status address register haccsar h'0000 0000 h'0000 0000 retained retained command/status data register haccsdr h'0000 0000 h'0000 0000 retained retained pcm left channel register hacpcml h'0000 0000 h'0000 0000 retained retained pcm right channel register hacpcm r h'0000 0000 h'0000 0000 retained retained tx interrupt enable register hactier h'0000 0000 h'0000 0000 retained retained tx status register hactsr h'f000 0000 h'f000 0000 retained retained rx interrupt enable register hacrier h'0000 0000 h'0000 0000 retained retained rx status register hacrsr h'0000 0000 h'0000 0000 retained retained hac control register hacacr h'8400 0000 h'8400 0000 retained retained
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 958 of 1286 rej09b0158-0100 25.3.1 control and status register (haccr) haccr is a 32-bit read/write register for contro lling input/output and monitoring the interface status. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ?? ?? ????? ? ? ? ?? ?? ?? ? ?? ? ??? ? bit: 0000000000000000 initial value: rrrrrrrrrrrrrrrr r rwr r r r r r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000010 00 00 000 rrrrwwrr cr cdrt wmrt st 0 bit bit name initial value r/w description 31 to 16 ? all 0 r reserved always 0 for read and write. 15 cr 0 r codec ready 0: the hac-connected codec is not ready. 1: the hac-connected codec is ready. 14 to 12 ? all 0 r reserved always read as 0. write prohibited. 11 cdrt 0 w hac cold reset use a cold reset only after power-on, or only to exit from the power-down mode by the power-down command. [write] 0: always write 0 to this bit before writing 1 again. 1: performs a cold reset on the hac. [read] always read as 0.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 959 of 1286 rej09b0158-0100 bit bit name initial value r/w description 10 wmrt 0 w hac warm reset use a warm reset only after power-up, or only to exit from the power-down mode by the power-down command. [write] 0: always write 0 to this bit before writing 1 again. 1: performs a warm reset on the hac. [read] always read as 0. 9 ? 1 r reserved always 1 for read and write. 8 to 6 ? all 0 r reserved always 0 for read and write. 5 st 0 w start transfer [write] 1: starts data transmission/reception. 0: stops data transmission/rec eption at the end of the current frame. do not take this action to terminate transmission/reception in normal operation. [read] always read as 0. 4 to 0 ? all 0 r reserved always 0 for read and write. to place the off-chip codec device into the power- down mode, write 1 to bit 12 of the register index 26 in the off-chip codec via the hac. when entering the power-down mode, the off-chip codec stops hac_bitclk and suspends the norm al operation. the off-c hip codec acts in the same manner at power-on. to resume the normal operation, perform a cold reset or a warm reset on the off-chip codec.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 960 of 1286 rej09b0158-0100 25.3.2 command/status a ddress register (haccsar) haccsar is a 32-bit read/write register that specifi es the address of the codec register to be read /written. when requesting a write to/read from a codec register, write the command register address to haccsar. then the hac transmits this register address to the codec via slot 1. after the codec has responded to a read request (hacrsr.stary = 1), the status address received via slot 1 can be read out from haccsar. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ?? ?? ????? ? ? ? bit: 0000000000000000 initial value: r r r r r r r r r r r r r/w r/w r/w r/w rrrrrrrr r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r/w r/w r/w r/w r r r r ca3/ sa3 ca2/ sa2 ca1/ sa1 ca0/ sa0 slr eq3 slr eq4 slr eq5 slr eq6 slr eq7 slr eq8 slr eq9 slr eq10 slr eq11 slr eq12 ca6/ sa6 rw ca5/ sa5 ca4/ sa4 0 bit bit name initial value r/w description 31 to 20 ? all 0 r reserved always 0 for read and write. 19 rw 0 r/w codec read/write command 0: notifies the off-chip codec device of a write access to the register specified in the address field (ca6/sa6 to ca0/sa0). write the data to haccsdr in advance. when hacacr.tx12_atomic is 1, the hac transmits haccsar and haccsdr as a pair in the same tx frame. when hacacr.tx12_atomic is 0, transmission of haccsar and haccsdr in the same tx frame is not guaranteed. 1: notifies the off-chip codec device of a read access to the register specified in the address field (ca6/sa6 to ca0/sa0).
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 961 of 1286 rej09b0158-0100 bit bit name initial value r/w description 18 17 16 15 14 13 12 ca6/sa6 ca5/sa5 ca4/sa4 ca3/sa3 ca2/sa2 ca1/sa1 ca0/sa0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w codec control register addresses 6 to 0 /codec status register addresses 6 to 0 [write] specify the address of the co dec register to be written. [read] indicate the status address received via slot 1, corresponding to the codec register whose data has been returned in haccsdr. 11 10 9 8 7 6 5 4 3 2 slreq3 slreq4 slreq5 slreq6 slreq7 slreq8 slreq9 slreq10 slreq11 slreq12 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r slot requests 3 to 12 valid only in the rx frame. indicate whether the codec is requesting slot data in the next tx frame. automatically set by hardware, and correspond to bits 11 to 2 of slot 1 in the rx frame. 0: slot data is requested. 1: slot data is not requested. 1, 0 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 962 of 1286 rej09b0158-0100 25.3.3 command/status data register (haccsdr) haccsdr is a 32-bit read/write data register us ed for accessing the codec register. write the command data to haccsdr. the hac then transmits the data to the codec via slot 2. after the codec has responded to a read reques t (hacrsr.stdry = 1), the status data received via slot 2 can be read out from haccsdr. in both read and write, haccsar stores the related codec register address. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ?? ?? ????? ? ? ? ? ? bit: 0000000000000000 initial value: r r r r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r r r r r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r/w r/w r/w r/w r/w r/w r/w r/w cd11/ sd11 cd10/ sd10 cd9/ sd9 cd8/ sd8 cd7/ sd7 cd6/ sd6 cd5/ sd5 cd4/ sd4 cd3/ sd3 cd2/ sd2 cd1/ sd1 cd0/ sd0 cd15/ sd15 cd14/ sd14 cd13/ sd13 cd12/ sd12 0 bit bit name initial value r/w description 31 to 20 ? all 0 r reserved always 0 for read and write. 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 cd15/sd15 cd14/sd14 cd13/sd13 cd12/sd12 cd11/sd11 cd10/sd10 cd9/sd9 cd8/sd8 cd7/sd7 cd6/sd6 cd5/sd5 cd4/sd4 cd3/sd3 cd2/sd2 cd1/sd1 cd0/sd0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w command data 15 to 0/status data 15 to 0 write data to these bits and then write the codec register address in haccsar. the hac then transmits the data to the codec. read these bits to get the cont ents of the codec register indicated by haccsar. 3 to 0 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 963 of 1286 rej09b0158-0100 25.3.4 pcm left channel register (hacpcml) hacpcml is a 32-bit read/write data register used for accessing the left channel of the codec in digital audio recording or stream playback. to transmit the pcm playback left channel data to the codec, write the data to hacpcml. to receive the pcm record left channel data from the codec, read hacpcml. the data is left justified to accommodate a codec with adc/dac resolution of 20 bits or less. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ?? ?? ????? ? bit: 0000000000000000 initial value: r r r r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r/w r/w r/w r/w r/w r/w r/w r/w d19 d18 d17 d16 d3 d2 d1 d0 d7 d6 d5 d4 d11 d10 d9 d8 d15 d14 d13 d12 0 bit bit name initial value r/w description 31 to 20 ? all 0 r reserved always 0 for read and write. 19 to 0 d19 to d0 all 0 r/w data 19 to 0 write the pcm playback left channel data to these bits. the hac then transmits the data to the codec on an on- demand basis. read these bits to get the pcm record left channel data from the codec.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 964 of 1286 rej09b0158-0100 in 16-bit packed dma mode, hacpcml is defined as follows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - bit: 0000000000000000 initial value: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r/w r/w r/w r/w r/w r/w r/w r/w rd3 rd1 rd2 rd0 rd7 rd6 rd5 rd4 rd11 rd10 rd9 rd8 rd15 rd14 rd13 rd12 ld3 ld1 ld2 ld0 ld7 ld6 ld5 ld4 ld11 ld10 ld9 ld8 ld15 ld14 ld13 ld12 0 bit bit name initial value r/w description 31 to 16 ld15 to ld0 all 0 r/w left data 15 to 0 write the pcm playback left channel data to these bits. the hac then transmits the data to the codec on an on- demand basis. read these bits to get the pcm record left channel data from the codec. 15 to 0 rd15 to rd0 all 0 r/w right data 15 to 0 write the pcm playback right channel data to these bits. the hac then transmits the data to the codec on an on-demand basis. read these bits to get the pcm record right channel data from the codec.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 965 of 1286 rej09b0158-0100 25.3.5 pcm right channel register (hacpcmr) hacpcmr is a 32-bit read/write register used for accessing the right channel of the codec in digital audio recording or stream playback. to transmit the pcm playback right channel data to the codec, write the data to ha cpcmr. to receive the pcm record right channel data from the codec, read hacpcmr. the data is left ju stified to accommodate a codec with adc/dac resolution of 20-bit or less. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ?? ?? ????? ? bit: 0000000000000000 initial value: r r r r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r/w r/w r/w r/w r/w r/w r/w r/w d19 d18 d17 d16 d3 d2 d1 d0 d7 d6 d5 d4 d11 d10 d9 d8 d15 d14 d13 d12 0 bit bit name initial value r/w description 31 to 20 ? all 0 r reserved always 0 for read and write. 19 to 0 d19 to d0 all 0 r/w data 19 to 0 write the pcm playback right channel data to these bits. the hac then transmits the data to the codec on an on-demand basis. read these bits to get the pcm record right channel data from the codec.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 966 of 1286 rej09b0158-0100 25.3.6 tx interrupt en able register (hactier) hactier is a 32-bit read/write register that enables or disables hac tx interrupts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ?? ?? ????????? ? ?? ? ? ? ? ? ? bit: 0000000000000000 initial value: rrr/wr/wrrrrrrrrrrrr rrrrrrrr r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 00 00 000 r r r r r r r/w r/w pltf unie prtf unie ? ?? ??? pltf rqie prtf rqie 0 bit bit name initial value r/w description 31, 30 ? all 0 r reserved always 0 for read and write. 29 pltfrqie 0 r/w pcml tx request interrupt enable 0: disables pcml tx request interrupts 1: enables pcml tx request interrupts 28 prtfrqie 0 r/w pcmr tx request interrupt enable 0: disables pcmr tx request interrupts 1: enables pcmr tx request interrupts 27 to 10 ? all 0 r reserved always 0 for read and write. 9 pltfunie 0 r/w pcml tx underrun interrupt enable 0: disables pcml tx underrun interrupts 1: enables pcml tx underrun interrupts 8 prtfunie 0 r/w pcmr tx underrun interrupt enable 0: disables pcmr tx underrun interrupts 1: enables pcmr tx underrun interrupts 7 to 0 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 967 of 1286 rej09b0158-0100 25.3.7 tx status register (hactsr) hactsr is a 32-bit read/write register that indicat es the status of the hac tx controller. writing 0 to the bit will initialize it. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ?? ???????? ? ?? ? ? ? ? ? ? bit: 1111000000000000 initial value: r/w r/w r/w r/w r r r r r r r r r r r r rrrrrrrr r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r r r r r r r/w r/w plt fun prt fun ? ?? ??? plt frq cmd dmt cmd amt prt frq 0 bit bit name initial value r/w description 31 cmdamt 1 r/w * 2 command address empty 0: csar tx buffer contains untransmitted data. 1: csar tx buffer is empty and ready to store data. * 1 30 cmddmt 1 r/w * 2 command data empty 0: csdr tx buffer contains untransmitted data. 1: csdr tx buffer is empty and ready to store data. * 1 29 pltfrq 1 r/w * 2 pcml tx request 0: pcml tx buffer contains untransmitted data. 1: pcml tx buffer is empty and needs to store data. in dma mode, writing to hacpcml will automatically clear this bit to 0. 28 prtfrq 1 r/w * 2 pcmr tx request 0: pcmr tx buffer contains untransmitted data. 1: pcmr tx buffer is empty and needs to store data. in dma mode, writing to hacpcmr will automatically clear this bit to 0. 27 to 10 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 968 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9 pltfun 0 r/w * 2 pcml tx underrun 0: no pcml tx underrun has occurred. 1: pcml tx underrun has occurred because the codec has requested slot 3 data but new data is not written to pcml. 8 prtfun 0 r/w * 2 pcmr tx underrun 0: no pcmr tx underrun has occurred. 1: pcmr tx underrun has occurred because the codec has requested slot 4 data but new data is not written to pcmr. 7 to 0 ? all 0 r reserved always 0 for read and write. notes: 1. cmdamt and cmddmt have no associated interrupts. poll these bits until they are read as 1 before writing a new command to haccsar/haccsdr. when bit 19 (rw) of haccsar is 0 and tx12_atomic is 1, take the following steps: 1. initialize cmddmt and cmdamt before fi rst accessing a codec register after hac initialization by any reset event. 2. after making the settings in haccsdr and haccsar, poll cmddmt and cmdamt until they are cleared to 1, and then initialize these bits. 3. now the next write to a register is available. 2. these bits are read/write. wr iting 0 to the bit initializes it but writing 1 has no effect.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 969 of 1286 rej09b0158-0100 25.3.8 rx interrupt en able register (hacrier) hacrier is a 32-bit read/write register that enables or disables hac rx interrupts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ?? ? ? ?? ????? ?? ?? ? ? ? ? ? ? bit: 0000000000000000 initial value: r r r r r r r r r r/w r/w r/w r/w r r r rrrrrrrr r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r r r/w r/w r r r r plrf ovie prrf ovie ?? ?? plrf rqie stdr yie star yie prrf rqie 0 bit bit name initial value r/w description 31 to 23 ? all 0 r reserved always 0 for read and write. 22 staryie 0 r/w status addr ess ready interrupt enable 0: disables status address ready interrupts. 1: enables status address ready interrupts. 21 stdryie 0 r/w status data ready interrupt enable 0: disables status dat a ready interrupts. 1: enables status data ready interrupts. 20 plrfrqie 0 r/w pcml rx request interrupt enable 0: disables pcml rx request interrupts. 1: enables pcml rx request interrupts. 19 prrfrqie 0 r/w pcmr rx request interrupt enable 0: disables pcmr rx request interrupts. 1: enables pcmr rx request interrupts. 18 to 14 ? all 0 r reserved always 0 for read and write. 13 plrfovie 0 r/w pcml rx overrun interrupt enable 0: disables pcml rx overrun interrupts. 1: enables pcml rx overrun interrupts. 12 prrfovie 0 r/w pcmr rx overrun interrupt enable 0: disables pcmr rx overrun interrupts. 1: enables pcmr rx overrun interrupts. 11 to 0 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 970 of 1286 rej09b0158-0100 25.3.9 rx status register (hacrsr) hacrsr is a 32-bit read/write register that i ndicates the status of the hac rx controller. writing 0 to the bit will initialize it. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ?? ? ? ? ? ? ? ?? ? ?? ?? ? ? ? ? ? ? bit: 0000000000000000 initial value: r r r r r r r r r r/w r/w r/w r/w r r r rrrrrrrr r/w: bit: initial value: r/w: 151413121110987654321 0 00000000 00 00 000 r r r/w r/w r r r r ?? ?? stary stdry plr frq prr frq plr fov prr fov 0 bit bit name initial value r/w description 31 to 23 ? all 0 r reserved always 0 for read and write. 22 stary 0 r/w status address ready 0: haccsar (status address) is not ready. 1: haccsar (status address) is ready. 21 stdry 0 r/w status data ready 0: haccsdr (status data) is not ready. 1: haccsdr (status data) is ready. 20 plrfrq 0 r/w pcml rx request 0: pcml rx data is not ready. 1: pcml rx data is ready and must be read. in dma mode, reading hacpcml automatically clears this bit to 0. 19 prrfrq 0 r/w pcmr rx request 0: pcmr rx data is not ready. 1: pcmr rx data is ready and must be read. in dma mode, reading hacpcmr automatically clears this bit to 0. 18 to 14 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 971 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 plrfov 0 r/w pcml rx overrun 0: no pcml rx data overrun has occurred. 1: pcml rx data overrun has occurred because the hac has received new data from slot 3 before pcml data is not read out. 12 prrfov 0 r/w pcmr rx overrun 0: no pcmr rx data overrun has occurred. 1: pcmr rx data overrun has occurred because the hac has received new data from slot 4 before pcmr data is not read out. 11 to 0 ? all 0 r reserved always 0 for read and write. note: * this register is read/write. writing 0 to the bit initializes it but writing 1 has no effect. 25.3.10 hac control register (hacacr) hacacr is a 32-bit read/write register used for controlling the hac interface. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ?? ?? ? ?? ?? ? ? ? ? ? ? bit: 1000010000000000 initial value: r r/w r/w r r r/w r r/w r/w r/w r/w r r r r r rrrrrrrr r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000 00 00 000 rrrrrrrr ?? ?? ?? tx12_ atomic rxdmal _en txdmal _en rxdmar _en txdmar _en dma rx16 dma tx16 0 bit bit name initial value r/w description 31 ? 1 r reserved always 1 for read and write.. 30 dmarx16 0 r/w 16-bit rx dma enable 0: disables 16-bit packed rx dma mode. enables the rxdmal_en and rxdmar_en settings. 1: enables 16-bit packed rx dma mode. disables the rxdmal_en and rxdmar_en settings.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 972 of 1286 rej09b0158-0100 bit bit name initial value r/w description 29 dmatx16 0 r/w 16-bit tx dma enable 0: disables 16-bit packed tx dma mode. enables the txdmal_en and txdmar_en settings. 1: enables 16-bit packed tx dma mode. disables the txdmal_en and txdmar_en settings. 28, 27 ? all 0 r reserved always 0 for read and write. 26 tx12_atomic 1 r/w tx slot 1 and 2 atomic control 0: transmits tx data in haccsar and that in haccsdr separately. (setting prohibited) 1: transmits tx data in haccsar and that in haccsdr in the same frame if bit 19 in haccsar is 0 (write). (haccsar must be written last.) 25 ? 0 r reserved always 0 for read and write. 24 rxdmal_en 0 r/w rx dma left enable 0: disables 20-bit rx dma for hacpcml. 1: enables 20-bit rx dma is for hacpcml. 23 txdmal_en 0 r/w tx dma left enable 0: disables 20-bit tx dma for hacpcml. 1: enables 20-bit tx dma for hacpcml. 22 rxdmar_en 0 r/w rx dma right enable 0: disables 20-bit rx dma for hacpcmr. 1: enables 20-bit rx dma for hacpcmr. 21 txdmar_en 0 r/w tx dma right enable 0: disables 20-bit tx dma for hacpcmr. 1: enables 20-bit tx dma for hacpcmr. 20 to 0 ? all 0 r reserved always 0 for read and write.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 973 of 1286 rej09b0158-0100 25.4 ac 97 frame slot structure figure 25.2 shows the ac97 frame slot structure. this lsi supports slots 0 to 4 only. slots 5 to 12 are out of scope. slot no. tag cmd data cmd addr pcml front line1 dac pcmr front pcm center pcmr surr pcml surr pcm lfe hset dac io ctrl line2 dac 0123456789101112 hac_sync hac_sd_out (transmit) hac_sd_in (receive) tag status data status addr pcm left line1 adc pcm right pcm mic reser ved reser ved reser ved hset adc io status line2 adc figure 25.2 ac97 frame slot structure table 25.4 ac97 transmit frame structure slot name description 0 sdata_out tag codec ids and tags indicating valid data 1 control cmd addr write port read/ write command and register address 2 control data write por t register write data 3 pcm l dac playback left channel pcm output data 4 pcm r dac playback right channel pcm output data 5 modem line 1 dac modem 1 output data (unsupported) * 6 pcm center center channel pcm data (unsupported) * 7 pcm surround l surround left channel pcm data (unsupported) * 8 pcm surround r surround right channel pcm data (unsupported) * 9 pcm lfe lfe channel pcm data (unsupported) * 10 modem line 2 dac modem 2 output data (unsupported) * 11 modem handset dac modem h andset output data (unsupported) * 12 modem io control modem control io output (unsupported) * notes: * there is no register fo r unsupported functions.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 974 of 1286 rej09b0158-0100 table 25.5 ac97 receive frame structure slot name description 0 sdata_in tag tags in dicating valid data 1 status addr read port regi ster address and slot request 2 status data read port register read data 3 pcm l adc record left channel pcm input data 4 pcm r adc record right channel pcm input data 5 modem line 1 adc modem 1 input data (unsupported) * 6 dedicated microphone adc optional pcm data (unsupported) * 7 to 9 reserved reserved 10 modem line 2 adc modem 2 input data (unsupported) * 11 modem handset input dac modem handset input data (unsupported) * 12 modem io status modem control io input (unsupported) * notes: * there is no register fo r unsupported functions. 25.5 operation 25.5.1 receiver the hac receiver receives serial audio data in put on the hac_sdin pin, synchronous to hac_bitclk. from slot 0, the receiver extracts tag bits that indicate which other slots contain valid data. it will update the recei ve data only when receiving vali d slot data indicated by the tag bits. supporting data only in slots 1 to 4, the receiver ignores tag bits and data related to slots 5 to 12. it loads valid slot data to the corresponding shift register to hold the data for pio or dma transfer, and sets the corresponding status bits. it is possible to read 20-bit data within a 32-bit register using pio. in the case of rx overrun, the new data will overwrite the current data in the rx buffer of the hac.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 975 of 1286 rej09b0158-0100 25.5.2 transmitter the hac transmitter outputs serial audio data on the hac_sdout pin, synchronous to hac_bit_clk. the transmitter sets the tag bits in slot 0 to indicate which slots in the current frame contain valid data. it loads data slots to the current tx frame in response to the corresponding slot request bits from the previous rx frame. the transmitter supports data only in slots 1 to 4. the tx buffer holds data that has been transferred using pio or dma, and sets the corresponding status bit. it is possible to write 20-bit data within a 32-bit register using pio. in the case of a tx underrun, the hac will transmit the current tx buffer data until the next data arrives. 25.5.3 dma the hac supports dma transfer for slots 3 and 4 of both the rx and tx frames. specify the slot data size for dma transfer, 16 or 20 bits, w ith the dmarx16 and dmatx16 bits in hacacr. when the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles. since each of the receiver and transmitter has its dma request, the stereo mode generates a dma request for slots 3 and 4 separately. the mono mode generates a dma request for just one slot. when the data size is 16 bits, data from slots 3 and 4 are packed into a single 32-bit quantity (left data and right data are in pcml), whic h requires only one local bus access cycle. it may be necessary to halt a dma transfer before the end count is reached , depending on system applications. if so, clear the corresponding dma bit in hacacr to 0 (dma disabled). to resume a dma transfer, reprogram the dmac and then set the corresponding dma bit to 1 (dma enabled). 25.5.4 interrupts interrupts can be used for flag events from the receiver and transmitter. make the setting for each interrupt in the corresponding interrupt enable register. interrupts include a request to the cpu to read/write slot data, overrun and underrun. to get the interrupt source, read the status register. writing 0 to the bit will clear the corresponding interrupt.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 976 of 1286 rej09b0158-0100 25.5.5 initialization sequence figure 25.3 shows an example of the initialization sequence. no no yes yes (1) hacacr = h'0000 0000 (2) set haccsar and haccsdr (3) hacacr = h'01e0 0000 start hac cold reset (haccr = h'0000 0a00) start dma transfer (receiver/transmitter) (haccr = h'0000 0020) codec ready? (haccr = h'0000 8000) set dmac set read address h'26(power-down ctrl/stat) (haccsar = h'000a 6000) external codec internal status adc, dac, analog, ref = ready? (haccsdr = h'0000 00f0) set read volume and sampling rate tx, rx enable (set hacacr = h'03e0 0000: 20-bit dmatx, slot 1 and slot 2 are atomic control) external codec device initialization hac module initialization note: refer to section 14, direct memory access controller (dmac). figure 25.3 initialization sequence
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 977 of 1286 rej09b0158-0100 no no yes yes e1 < loopcnt 1 write to codec. write 0 to tsr.cmdamt. write 0 to tsr.cmddmt. clear retrycnt to 0. write data to csdr. write addr to csar. clear loopcnt to 0. tsr.cmdamt = 1& tsr.cmddmt = 1 wait for 1 s. loopcnt ++ necessary setting: acr.tx12_atomic = 1 no yes 5 < retrycnt error return e1: number required for the target system (21 < e1 < 1000) input: addr: address of the codec register to be written to data: data to be written to the codec register retrycnt: software counter for error detection loopcnt: software counter for wait insertion notes: retrycnt ++ figure 25.4 sample flowchart for off-chip codec register write
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 978 of 1286 rej09b0158-0100 no yes no yes no yes no yes no yes no yes no yes regv = h'7c (vender id1) last_reg: address of the register read last time dummy read read_codec_aux (regn) : data acquisition regn = last_reg? read codec. input: regn (address of the codec register to be read) error data return error read_codec_aux input: regn (address of the codec register to be read) when external codec registers are read in sequence, data in the last register that was read may be read again in some codec devices. in this case, use the read procedure shown in this flowchart. send_read_request (regn) error error error error error data 2 return send_read_request (regn) get_codec_data (regn) get_codec_data (regn) : data 1 acquisition : data 2 acquisition dummy processing (discard the first data) read_codec_aux (regv) error error figure 25.5 sample flowchart fo r off-chip codec register read (1)
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 979 of 1286 rej09b0158-0100 no yes send_read_request set regn to csar. input: regn (address of the codec register to be read) write 0 to rsr.stary. write 0 to rsr.stdry. waitloop_cmdamt error error error error error return no no yes yes no yes get_codec_data clear loopcnt2 to 0. input: regn (address of the codec register to be read) waitloop_rsr addr (r) = regn? assign haccsdr read value to datat. datat return e2: number required for the target system (13 < e2) loopcnt2: software counter for wait insertion addr: variable to hold csar read value datat: variable to hold csdr read value notes: wait for 5 ms. loopcnt2 ++ assign haccsar read value to addr. e2 < loopcnt 2 figure 25.6 sample flowchart fo r off-chip codec register read (2)
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 980 of 1286 rej09b0158-0100 no no yes waitloop_cmdamt clear loopcnt3 to 0. tsr.cmdamt = 1 write 0 to tsr.cmdamt. wait for 1 s. loopcnt3 ++ return yes e3 < loopcnt 3 error no no yes waitloop_rsr clear loopcnt4 to 0. return notes: e3 and e4: numbers required for the target system (21 < e3, 21 < e4 < 1000) loopcnt3: software counter for wait insertion loopcnt4: software counter for wait insertion error rsr.stary = 1 & rsr.stdry = 1 write 0 to rsr.stary. write 0 to rsr.stdry. yes e4 < loopcnt 4 wait for 1 s. loopcnt4 ++ figure 25.7 sample flowchart fo r off-chip codec register read (3) it is possible to stop the supply of clock to the hac using the mstp0 bit in mstpcr. for details of mstpcr, refer to section 17, power-down mode.
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 981 of 1286 rej09b0158-0100 to cancel module standby mode and resume the supply of clock to the hac, write 1 to the mstp0 bit in mstpcr. af ter that, it enables a ll accesses to the hac. an example of the procedure to enter the module standby mode is shown below. 1. check that all data transactions have ended. also check that the transmit buffer of the hac is empty and the receive buffer of the ha c has been read out to be empty. 2. disable all dma requests and interrupt requests. 3. place the codec into power-down mode. 4. write 1 to the mstp0 bit in mstpcr. 25.5.6 notes the hac_sync signal is generated by the hac to indicate the position of slot 0 within a frame. 25.5.7 reference ac'97 component specification, revision 2.1
section 25 audio codec interface (hac) rev.1.00 dec. 13, 2005 page 982 of 1286 rej09b0158-0100
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 983 of 1286 rej09b0158-0100 section 26 serial soun d interface (ssi) module the serial sound interf ace (ssi) module is a module designed to send or receive audio data interface with a variety of devices offering philips format compatibility. it also provides additional modes for other common formats, as well as support for a burst and multi-channel mode. 26.1 features the ssi has the following features. ? ? ? ? ? ?
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 984 of 1286 rej09b0158-0100 ssi_ws ssi_sck ssi_sdata ssi_clk serial audio bus register ssicr ssisr ssitdr ssirdr ssi module dma request interrupt request ssi bridge bus data buffer barrel shifter control circuit bit counter serial clock control divider lsb msb shift register figure 26.1 block diagram of ssi module 26.2 input/output pins table 26.1 lists the pin configurations relating to the ssi module. table 26.1 pin configuration pin name i/o function ssi_sck i/o serial bit clock ssi_ws i/o word select ssi_sdata i/o serial data input/output ssi_clk input divider input clock (ove rsampling clock 256/384/512fs input) note: these pins are multiplexed with the siof, hac and gpio pins.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 985 of 1286 rej09b0158-0100 26.3 register descriptions table 26.2 shows the ssi register configuration. table 26.3 shows the register states in each processing mode. table 26.2 register configuration register name abbrev. r/w p4 address area 7 address size sync clock control register ssicr r/w h'ffe7 0000 h'1fe7 0000 32 pck status register ssisr r/w * 1 h'ffe7 0004 h'1fe7 0004 32 pck transmit data register ssitdr r/w h'ffe7 0008 h'1fe7 0008 32 pck receive data register ssirdr r h'ffe7 000c h'1fe7 000c 32 pck note: * to clear the flag, only 0s are written to bits 27 and 26. table 26.3 register states of ssi in each processing mode register name abbrev. power-on reset by preset pin/wdt/ h-udi manual reset by preset pin/wdt/ multiple exception sleep by sleep instruction module standby control register ssicr h'0000 0000 h'0000 0000 retained retained status register ssisr h'0200 0003 h'0200 0003 retained retained transmit data register ssitdr h'0000 0000 h'0000 0000 retained retained receive data register ssirdr h'0000 0000 h'0000 0000 retained retained
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 986 of 1286 rej09b0158-0100 26.3.1 control register (ssicr) ssicr is a 32-bit readable/writable register that co ntrols the irq, selects each polarity status, and sets operating mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ? ? 0 00 ? 0000 00000 bren ckdv pdta sdta del swsp spdp swsd sckd sckp muen cpen trmd en chnl1 chnl0 dwl2 iien oien dien dmen uien dwl1 dwl0 swl2 swl1 swl0 bit: initial value: r/w: bit: initial value: r/w: 151413121110987654321 0 r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 00 00 00000 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ? ? ? bit bit name initial value r/w description 31 to 29 ? ? r reserved these bits are always read as an undefined value. the write value should always be 0. 28 dmen 0 r/w dma enable enables or disables the dma request. 0: dma request disabled. 1: dma request enabled. 27 uien 0 r/w underflow interrupt enable 0: underflow interrupt disabled 1: underflow interrupt enabled 26 oien 0 r/w overflow interrupt enable 0: overflow interrupt disabled 1: overflow interrupt enabled 25 iien 0 r/w idle mode interrupt enable 0: idle interrupt disabled 1: idle interrupt enabled 24 dien 0 r/w data interrupt enable 0: data interrupt disabled 1: data interrupt enabled
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 987 of 1286 rej09b0158-0100 bit bit name initial value r/w description 23 22 chnl1 chnl0 0 0 r/w r/w channels these bits indicate the number of channels in each system word. these bits are ignored if cpen = 1. 00: 1 channel per system word 01: 2 channels per system word 10: 3 channels per system word 11: 4 channels per system word 21 20 19 dwl2 dwl1 dwl0 0 0 0 r/w r/w r/w data word length these bits indicate the encoded number of bits in a data word. these bits are ignored if cpen = 1. 000: 8 bits 001: 16 bits 010: 18 bits 011: 20 bits 100: 22 bits 101: 24 bits 110: 32 bits 111: setting prohibited 18 17 16 swl2 swl1 swl0 0 0 0 r/w r/w r/w system word length these bits indicate the encoded number of bits in a system word. these bits are ignored if cpen = 1. 000: 8 bits 001: 16 bits 010: 24 bits 011: 32 bits 100: 48 bits 101: 64 bits 110: 128 bits 111: 256 bits 15 sckd 0 r/w serial bit clock direction 0: serial clock input, slave mode 1: serial clock output, master mode 14 swsd 0 r/w serial ws direction 0: serial word select input, slave mode 1: serial word select output, master mode
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 988 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 sckp 0 r/w serial clock polarity 0: ssi_ws and ssi_sdata change on falling edge of ssi_sck (sampled on rising edge of sck) 1: ssi_ws and ssi_sdata change on rising edge of ssi_sck (sampled on falling edge of sck) sckp = 0 sckp = 1 ssi_sdata input sampling timing in receive mode (trmd = 0) ssi_sck rising edge ssi_sck falling edge ssi_sdata output change timing in transmit mode (trmd = 1) ssi_sck falling edge ssi_sck rising edge ssi_ws input sampling in slave mode (swsd = 0) ssi_sck rising edge ssi_sck falling edge ssi_ws output change timing in master mode (swsd = 1) ssi_sck falling edge ssi_sck rising edge 12 swsp 0 r/w serial ws polarity the function of this bit depends on whether the ssi module is in non-compressed mode or compressed mode. cpen = 0 (non compressed mode): 0: ssi_ws is low for the first channel, high for the second channel 1: ssi_ws is high for the first channel, low for the second channel cpen = 1 (compressed mode): 0: ssi_ws is active high flow control. ws = high means data should be transferred, low means data should not be transferred. 1: ssi_ws is active low flow control. ws = low means data should be transferred, high means data should not be transferred.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 989 of 1286 rej09b0158-0100 bit bit name initial value r/w description 11 spdp 0 r/w serial padding polarity this bit is ignored if cpen = 1. 0: padding bits are low 1: padding bits are high 10 sdta 0 r/w serial data alignment this bit is ignored if cpen = 1. 0: serial data is transmitted/ received first, followed by padding bits. 1: padding bits are transmitted/ received first, followed by serial data. 9 pdta 0 r/w parallel data alignment this bit is ignored if cpen = 1. if the data word length = 32, 16 or 8 then this bit has no meaning. this bit is applied to ssirdr in receive mode and to ssitdr in transmit mode. 0: parallel data (ssitdr or ssirdr) is left aligned 1: parallel data (ssitdr or ssirdr) is right aligned ? dwl = 000 (data word length: 8 bits), pdta ignored all data bits in ssirdr or ssitdr are used on the audio serial bus. four data words are transmitted/received in each 32-bit access. the first data word is derived from bits 7 to 0, the second from bits 15 to 8, the third from bits 23 to 16 and the last data word is stored in bits 31 to 24. ? dwl = 001 (data word length: 16 bits), pdta ignored all data bits in ssirdr or ssitdr are used on the audio serial bus. two data words are transmitted/received in each 32-bit access. the first data word is derived from bits 15 to 0 and the second data word is stored in bits 31 to 16.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 990 of 1286 rej09b0158-0100 bit bit name initial value r/w description 9 pdta 0 r/w ? dwl = 010, 011, 100, 101 (data word length: 18, 20, 22 and 24 bits), pdta = 0 (left aligned) ? the data bits which are used in ssirdr or ssitdr are the following: bits 31 to (32 ? number of bits having data word length specified by dwl). if dwl = 011 then data word length is 20 bits and bits 31 to 12 are used of either ssirdr or ssitdr. all other bits are ignored or reserved. ? dwl = 010, 011, 100, 101 (data word length: 18, 20, 22 and 24 bits), pdta = 1 (right aligned) the data bits which are used in ssirdr or ssitdr are the following: bits (number of bits having data word length specified by dwl - 1) to 0. if dwl = 011 then data word length is 20 bits and bits 19 to 0 are used of either ssirdr or ssitdr. all other bits are ignored or reserved. ? dwl = 110 (data word length: 32 bits), pdta ignored all data bits in ssirdr or ssitdr are used on the audio serial bus. 8 del 0 r/w serial data delay 0: 1 clock cycle delay between ssi_ws and ssi_sdata 1: no delay between ssi_ws and ssi_sdata this bit is ignored if cpen = 1. 7 bren 0 r/w burst mode enable 0: burst mode is disabled. 1: burst mode is enabled. burst mode is used in conjunction with compressed mode (cpen = 1). when burst mode is enabled the ssi_sck signal is gated. clock pulses are output only when there is valid serial data being output on ssi_sdata.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 991 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 to 4 ckdv all 0 r/w serial oversampling clock division ratio these bits define the division ratio between oversampling clock (hac_bit_clk) and the serial bit clock. these bits are ignored if sckd = 0. the serial bit clock is used for the shift register and is provided on the ssi_sck pin. 000: (serial bit clock frequency = oversampling clock frequency/1) 001: (serial bit clock frequency = oversampling clock frequency/2) 010: (serial bit clock frequency = oversampling clock frequency/4) 011: (serial bit clock frequency = oversampling clock frequency/8) 100: (serial bit clock frequency = oversampling clock frequency/16) 101: (serial bit clock frequency = oversampling clock frequency/6) 110: (serial bit clock frequency = oversampling clock frequency/12) 111: setting prohibited 3 muen 0 r/w mute enable when in transmit mode (trmd = 1), by making muen = 1, the output of ssi_sda ta will be in low level. 0: the ssi module is not muted 1: the ssi module is muted 2 cpen 0 r/w compressed mode enable 0: compressed mode disabled 1: compressed mode enabled note: in compressed mode (cpen=1), using operation mode except slave transmitter (swsd=0 and trmd=1). 1 trmd 0 r/w transmit/receive mode select 0: the ssi module is in receive mode 1: the ssi module is in transmit mode 0 en 0 r/w ssi module enable 0: the ssi module is disabled 1: the ssi module is enabled
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 992 of 1286 rej09b0158-0100 26.3.2 status register (ssisr) ssisr is configured by status fl ags that indicate the operating st atus of the ssi module and bits that indicate the current chan nel number and word number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ? ? 0 01 ? 0 ?? ? ????? ??? ? ?? ?? ? ?? ? chno1 chno0 swno idst ??? iirq oirq dirq dmrq uirq ???? ? bit: initial value: r/w: bit: initial value: r/w: 151413121110987654321 0 rrrrr/w * rrr r/w * rr r r r rr ? ? ?? ?? ????? ? 0011 rrrrr rrr rrr r r r rr ? ? ? bit bit name initial value r/w description 31 to 29 ? ? r reserved these bits are always read as an undefined value. the write value should always be 0. 28 dmrq 0 r dma request status flag this status flag allows the cpu to see the status of the dma request of ssi module. trmd = 0 (receive mode): ? if dmrq = 1 then ssirdr has unread data. ? if ssirdr is read then dmrq = 0 until there is new unread data. trmd = 1 (transmit mode): ? if dmrq = 1, ssitdr requests data to be written to continue the transmission onto the audio serial bus. ? once data is written to ssitdr then dmrq = 0 until further transmit data is requested.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 993 of 1286 rej09b0158-0100 bit bit name initial value r/w description 27 uirq 0 r/w * underflow error interrupt status flag this status flag indicates that the data has been supplied at a lower rate than the required rate. this bit is set to 1 regardless of the setting of uien bit. in order to clear it to 0, write 0 in it. if uirq = 1 and uien = 1, then an interrupt will be generated. when trmd = 0 (receive mode): if uirq = 1, it indicates that ssirdr was read out before dmrq and dirq bits would indicate the existence of new unread data. in this instance, the same received data may be stored twice by the host, which can lead to destruction of multi-channel data. when trmd = 1 (transmit mode): if uirq = 1, it indicates t hat the transmitted data was not written in ssitdr. by this, the same data may be transmitted one time too often, which can lead to destruction of multi-channel data. consequently, erroneous ssi data will be output, which makes this error more serious than underflow in the receive mode. note: when underflow error occurs, the data in the data buffer will be transmitted until the next data is written in.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 994 of 1286 rej09b0158-0100 bit bit name initial value r/w description 26 oirq 0 r/w * overflow error interrupt status flag this status flag indicates that the data has been supplied at a higher rate than the required rate. this bit is set to 1 regardless of the setting of oien bit. in order to clear it to 0, write 0 in it. if oirq = 1 and oien = 1, then an interrupt will be generated. when trmd = 0 (receive mode): if oirq = 1, it indicates t hat the previous unread data had not been read out before new unread data was written in ssirdr. this ma y cause the loss of data, which can lead to destruction of multi-channel data. when trmd = 1 (transmit mode): if oirq = 1, it indicates t hat ssitdr had data written in before the data in ssitdr wa s transferred to the shift register. this may cause the loss of data, which can lead to destruction of multi-channel data. note: when overflow error occurs, the data in the data buffer will be overwritten by the next data sent from the ssi interface. 25 iirq 1 r idle mode interrupt status flag this status flag indicates whether the ssi module is in the idle status. this bit is set to 1 regardless of the setting of iien bit, so that polling will be possible. the interrupt can be masked by clearing iien bit to 0, but writing 0 in this bit will not clear the interrupt. if iirq = 1 and iien = 1, then an interrupt will be generated. 0: the ssi module is not in the idle status. 1: the ssi module is in the idle status.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 995 of 1286 rej09b0158-0100 bit bit name initial value r/w description 24 dirq 0 r data interrupt status flag this status flag indicates that the ssi module requires that data be either read out or written in. this bit is set to 1 regardless of the setting of dien bit, so that polling will be possible. the interrupt can be masked by clearing dien bit to 0, but writing 0 in this bit will not clear the interrupt. if dirq = 1 and dien = 1, then an interrupt will be generated. when trmd = 0 (receive mode): 0: no unread data exists in ssirdr. 1: unread data exists in ssirdr. when trmd = 1 (transmit mode): 0: the transmit buffer is full. 1: the transmit buffer is em pty, and requires that data be written in ssitdr. 23 to 4 ? ? r reserved these bits are always read as an undefined value. the write value should always be 0. 3 2 chno1 chno0 0 0 r r channel number the number indicates the current channel. when trmd = 0 (receive mode): this bit indicates to which channel the current data in ssirdr belongs. when the data in ssirdr is updated by transfer from the shift register, this value will change. when trmd = 1 (transmit mode): this bit indicates the data of which channel should be written in ssitdr. when data is copied to the shift register, regardless whether the data is written in ssitdr, this value will change.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 996 of 1286 rej09b0158-0100 bit bit name initial value r/w description 1 swno 1 r serial word number the number indicates the current word number. when trmd = 0 (receive mode): this bit indicates which system word the current data in ssirdr is. regardless whether the data has been read out from ssirdr, when the data in ssirdr is updated by transfer from the shift register, this value will change. when trmd = 1 (transmit mode): this bit indicates which system word should be written in ssitdr. when data is copied to the shift register, regardless whether the data is written in ssitdr, this value will change. 0 idst 1 r idle mode status flag indicates that the serial bus activity has ceased. this bit is cleared if en = 1 and the serial bus is currently active. this bit can be set to 1 automatically under the following conditions. ssi = serial bus master transmitter (swsd = 1 and trmd = 1): this bit is set to 1 if no more data has been written to ssitdr and the current system word has been completed. it can also be set to 1 by clearing the en bit after sufficient data has be en written to ssitdr to complete the system word currently being output. ssi = serial bus master receiver (swsd = 1 and trmd = 0): this bit is set to 1 if the en bit is cleared and the current system word is completed. ssi = slave transmitter/ receiver (swsd = 0): this bit is set to 1 if the en bit is cleared and the current system word is completed. note: if the external device stops the serial bus clock before the current system word is completed then this bit will never be set. note: * these bits are readable/writable bits. if writ ing 0, these bits are initialized, although writing 1 is ignored.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 997 of 1286 rej09b0158-0100 26.3.3 transmit data register (ssitdr) ssitdr is a 32-bit register that stores data to be transmitted. data written to ssitdr is transferred to the shift re gister as it is required for transmission. if the data word length is less than 32 bits then its alignment should be as defined by the pdta control bit. reading this register will return the data in the buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 00 00 00000 0000 0 bit: initial value: r/w: bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 00 00 00000 00000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 26.3.4 receive data register (ssirdr) ssirdr is a 32-bit register that stores the received data. data in ssirdr is transferred from the shift register as each data word is received. if the data word length is less than 32 bits then its alignment should be as defined by the pdta control bit in ssicr. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 00 00 00000 0000 0 bit: initial value: r/w: bit: initial value: r/w: 151413121110987654321 0 rrrrr rrr rrr r r r rr 0 0 00 00 00000 00000 rrrrr rrr rrr r r r rr
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 998 of 1286 rej09b0158-0100 26.4 operation 26.4.1 bus format the ssi module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. the bus formats can be one of eight major modes as shown in table 26.4. table 26.4 bus formats of ssi module bus format tpmd cpen sckd swsd en muen dien iien oien uien del pdta sdta spdp swsp sckp swl[2:0] dwl[2:0] chnl[1:0] non-compressed slave receiver 0 0 0 0 non-compressed slave transmitter 1 0 0 0 non-compressed master receiver 0 0 1 1 non-compressed master transmitter 1 0 1 1 control bits configuration bits compressed slave receiver 0 1 0/1 0 compressed slave transmitter 1 1 0/1 0 compressed master receiver 0 1 0/1 1 compressed master transmitter 1 1 0/1 1 control bits ignored configu- ration bits ignored
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 999 of 1286 rej09b0158-0100 26.4.2 non-compressed modes the non-compressed mode is designed to support all serial audio streams which are split into channels. it can support philips, sony and matsus hita modes as well as many more variants on these modes. (1) slave receiver this mode allows the ssi module to receive serial data from another devi ce. the clock and word select signals used for the serial data stream are also supplied from an external device. if these signals do not conform to the format as speci fied in the ssi module then operation is not guaranteed. (2) slave transmitter this mode allows the ssi module to transmit serial data to another device. the clock and word select signals used for the serial data stream are also supplied from an external device. if these signals do not conform to the format as speci fied in the ssi module then operation is not guaranteed. (3) master receiver this mode allows the ssi module to receive serial data from another devi ce. the clock and word select signals are internally derived from the hac_bit_clk input clock. the format of these signals is as defined in the ssi module. if the incoming data does not conform to the defined format then operation is not guaranteed. (4) master transmitter this mode allows the ssi module to transmit serial data to another device. the clock and word select signals are internally derived from the hac_bit_clk input clock. the format of these signals is as defined in the configuration bits in the ssi module. (5) configuration fields - word length related all configuration bits relating to the word le ngth of ssicr are valid in non-compressed modes. there are many configurations that the ssi module can support and it is not sensible to show all of the serial data formats in this document. some of the combinations are shown below for the popular formats by philips, sony, and matsushita.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1000 of 1286 rej09b0158-0100 1. philips format figures 26.2 and 26.3 show the supported philips protocol both with padding and without. padding occurs when the data word length is smaller than the system word length. prev. sample msb lsb + 1 lsb msb lsb + 1 lsb next sample system word 1 = data word 1 system word 2 = data word 2 ssi_sck ssi_ws ssi_sdata sckp = 0, swsp = 0, del = 0, chnl = 00 system word length = data word length figure 26.2 philips format (with no padding) msb lsb msb lsb next system word 1 system word 2 data word 1 data word 2 padding padding ssi_sck ssi_ws ssi_sdata sckp = 0, swsp = 0, del = 0, chnl = 00, spdp = 0, sdta = 0 system word length > data word length figure 26.3 philips format (with padding) figure 26.4 shows the format used by sony. figure 26.5 shows the format used by matsushita. padding is assumed in both cases, but may not be present in a final implementation if the system word length equals the data word length.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1001 of 1286 rej09b0158-0100 2. sony format msb lsb msb lsb next system word 1 system word 2 data word 1 data word 2 padding padding ssi_sck ssi_ws ssi_sdata sckp = 0, swsp = 0, del = 1, chnl = 00, spdp = 0, sdta = 0 system word length > data word length figure 26.4 sony format (with serial data first, followed by padding bits) 3. matsushita format msb lsb system word 1 system word 2 data word 1 data word 2 padding padding msb lsb prev. ssi_sck ssi_ws ssi_sdata sckp = 0, swsp = 0, del = 1, chnl = 00, spdp = 0, sdta = 1 system word length > data word length figure 26.5 matsushita format (with paddi ng bits first, followed by serial data) (6) multi-channel formats there are some extend format of the philips' specification that allows more than 2 channels to be transferred within two system words. the ssi module supports the transfer of 4, 6 and 8 channels by the use of the chnl, swl and dwl bits. it is important that the system word length (swl) is greater than or equal to the number of channels (chnl) times the data word length (dwl). table 26.5 shows the number of padding bits for each of the valid configurations. if a setup is not valid it does not have a number in the following table and has instead a dash.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1002 of 1286 rej09b0158-0100 table 26.5 number of padding bits for each valid configuration padding bits per system word dwl[2:0] 000 001 010 011 100 101 110 chnl [1:0] decoded channels per system word swl [2:0] decoded word length 8 16 18 20 22 24 32 000 8 0 ? ? ? ? ? ? 001 16 8 0 ? ? ? ? ? 010 24 16 8 6 4 2 0 ? 011 32 24 16 14 12 10 8 0 100 48 40 32 30 28 26 24 16 101 64 56 48 46 44 42 40 32 110 128 120 112 110 108 106 104 96 00 1 111 256 248 240 238 236 234 232 224 000 8 ? ? ? ? ? ? ? 001 16 0 ? ? ? ? ? ? 010 24 8 ? ? ? ? ? ? 011 32 16 0 ? ? ? ? ? 100 48 32 16 12 8 4 0 ? 101 64 48 32 28 24 20 16 0 110 128 112 96 92 88 84 80 64 01 2 111 256 240 224 220 216 212 208 192 000 8 ? ? ? ? ? ? ? 001 16 ? ? ? ? ? ? ? 010 24 0 ? ? ? ? ? ? 011 32 8 ? ? ? ? ? ? 100 48 24 0 ? ? ? ? ? 101 64 40 16 10 4 ? ? ? 110 128 104 80 74 68 62 56 32 10 3 111 256 232 208 202 196 190 184 160 000 8 ? ? ? ? ? ? ? 001 16 ? ? ? ? ? ? ? 010 24 ? ? ? ? ? ? ? 011 32 0 ? ? ? ? ? ? 100 48 16 ? ? ? ? ? ? 101 64 32 0 ? ? ? ? ? 110 128 96 64 56 48 40 32 0 11 4 111 256 224 192 184 176 168 160 128
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1003 of 1286 rej09b0158-0100 in the case of the ssi module configured as a tr ansmitter then each word that is written to ssitdr is transmitted in order on the serial audio bus. in the case of the ssi module co nfigured as a receiver each word received on the serial audio bus is presented for reading in order by ssirdr. figures 26.6 to 26.8 show how 4, 6 and 8 channels are transferred on the serial audio bus. note that there are no padding bits in the first example, serial da ta is transmitted/received first and followed by padding bits in the second example, and padding bi ts are transmitted/received first and followed by serial data in the third ex ample. this selection is purely arbitrary. msb lsb data word 1 msb lsb msb lsb msb lsb data word 2 data word 3 data word 4 system word 1 system word 2 msb lsb data word 1 msb lsb msb lsb msb lsb data word 2 data word 3 data word 4 system word 1 system word 2 lsb msb ssi_sck ssi_ws ssi_sdata sckp = 0, swsp = 0, del = 1, chnl = 01, spdp = don't care, sdta = don't care system word length = data word length 2 figure 26.6 multi-channel fo rmat (4 channels, no padding) msb lsb system word 2 data word 1 msb lsb msb lsb msb data word 2 data word 3 padding system word 1 msb lsb msb lsb msb lsb data word 4 data word 5 data word 6 ssi_sck ssi_ws ssi_sdata padding sckp = 0, swsp = 0, del = 1, chnl = 10, spdp = 1, sdta = 0 system word length = data word length 3 figure 26.7 multi-channel format (6 channels with high padding)
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1004 of 1286 rej09b0158-0100 msb lsb system word 2 data word 1 msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb data word 2 data word 3 data word 4 data word 5 data word 6 data word 7 data word 8 padding system word 1 padding ssi_ws ssi_sdata ssi_sck sckp = 0, swsp = 0, del = 1, chnl = 11, spdp = 0, sdta = 1 system word length = data word length 4 figure 26.8 multi-channe l format (8 channels, with padding bits first, followed by serial data, with padding) (7) configuration fields - signal format fields there are several more configuration bits in non-compressed mode which will now be demonstrated. these bits are not mutually exclusiv e, however some configurations will probably not be useful for any other device.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1005 of 1286 rej09b0158-0100 they are demonstrated by referring to the followi ng basic sample format shown in figure 26.9. ssi_sck ssi_ws ssi_sdata key for this and following diagrams: 0 0 0 0 0 0 means a low level on the serial bus (padding or mute) 0 means a high level on the serial bus (padding) 1 arrow head indicates sampling point of receiver bit n in ssitdr tdn 1st channel 2nd channel td28 td31 td31 td30 td29 td28 td31 td30 td29 td28 swl = 6 bits (not attainable in ssi module, demonstration only) dwl = 4 bits (not attainable in ssi module, demonstration only) chnl = 00, sckp = 0, swsp = 0, spdp = 0, sdta = 0, pdta = 0, del = 0, muen = 0 4-bit data samples continuously written to ssitdr are transmitted onto the serial audio bus. figure 26.9 basi c sample format (transmit mode with example system/data word length) in figure 26.9, system word length of 6 bits and a data word length of 4 bits are used. neither of these are possible with the ssi modul e but are used only fo r clarification of the other configuration bits. 1. inverted clock ssi_sck ssi_ws ssi_sdata 0 0 0 0 0 0 1st channel 2nd channel td28 td31 td31 td30 td29 td28 td31 td30 td29 td28 as basic sample format configuration except sckp = 1 figure 26.10 inverted clock
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1006 of 1286 rej09b0158-0100 2. inverted word select ssi_sck ssi_ws ssi_sdata 0 0 0 0 0 0 1st channel 2nd channel td28 td31 td31 td30 td29 td28 td31 td30 td29 td28 as basic sample format configuration except swsp = 1 figure 26.11 inverted word select 3. inverted padding polarity ssi_sck ssi_ws ssi_sdata td28 td31 1st channel 2nd channel 11 11 1 1 td31 td30 td29 td28 td31 td30 td29 td28 as basic sample format configuration except spdp = 1 figure 26.12 invert ed padding polarity 4. padding bits first, followed by serial data, with delay ssi_sck ssi_ws ssi_sdata 0 0 0 td28 0 0 1st channel 2nd channel td30 td29 td31 td30 td29 td28 td31 td30 td29 td28 as basic sample format configuration except sdta = 1 figure 26.13 padding bits first, followed by serial data, with delay
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1007 of 1286 rej09b0158-0100 5. padding bits first, followed by serial data, without delay as basic sample format configuration except sdta = 1 and del = 1 0 0 0 td28 0 0 td29 0 td31 td30 td29 td28 td31 td30 td29 td28 ssi_sck ssi_ws ssi_sdata 1st channel 2nd channel figure 26.14 padding bits first, followed by serial data, without delay 6. serial data first, followed by padding bits, without delay as basic sample format configuration except del = 1 0 0 0 0 00 td31 td30 td31 td30 td29 td28 td31 td30 td29 td28 ssi_sck ssi_ws ssi_sdata 1st channel 2nd channel figure 26.15 serial data first, fo llowed by padding bits, without delay 7. parallel right aligned with delay as basic sample format configuration except pdta = 1 0 0 0 0 00 td3 td0 td3 td2 td1 td0 td3 td2 td1 td0 ssi_sck ssi_ws ssi_sdata 1st channel 2nd channel figure 26.16 parallel right aligned with delay
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1008 of 1286 rej09b0158-0100 8. mute enabled as basic sample format configuration except muen = 1 (td data ignored) 0 0 0 0 00 00 00 00 0 0 0 0 0 0 ssi_sck ssi_ws ssi_sdata 1st channel 2nd channel figure 26.17 mute enabled 26.4.3 compressed modes the compressed mode is used to transfer a continuous bit stream. this would typically be a compressed bit stream which requires downstr eam decoding. in streaming transfer (burst mode not enabled) there is no concept of a data word. however in order to receive and transmit it is necessary to tr ansfer between the serial bus and word formatted memory. therefore the word boundary selection is arbitrary during receive/transmit and must be dealt with by another module. when burst mode is enabled then data bits being transmitted can be identified by virtue of the fact th at the serial clock output is only activated when there is a word to be output and only the required nu mber of clock pulses necessary to clock out each 32-bit word are generated. the serial bit clock stops at a low level when ssicr.sckp = 0, and at a high level when ssicr.sckp = 1. note burst mode is only valid in the context of the ssi module being a transmitter of data. burst mode data cannot be received by this module. data is transmitted and received in blocks of 32 b its, and the first bit received/transmitted bit is bit 31 when stored in memory. the word select pin in this mode does not act as a system word start sign al as in non-compressed mode, but instead is used to indicate that the receiver can receive another data burst, or the transmitter can transmit another data burst. figures 26.18 and 26.19 show the compressed mode data transfer, with burst mode disabled, and enabled, respectively.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1009 of 1286 rej09b0158-0100 trmd = 1, cpen = 1, sckd = 1, swsd = 0, swsp = 0, bren = 0 msb lsb msb lsb data word 1 data word 2 msb lsb data word 3 null data ssi_sck ssi_ws ssi_sdata figure 26.18 compressed data format, sl ave transmitter, burst mode disabled trmd = 1, cpen = 1, sckd = 1, swsd = 0, swsp = 0, bren = 1 msb lsb msb lsb data word 1 data word 2 msb lsb data word 3 null data ssi_sck ssi_ws ssi_sdata figure 26.19 compressed data format, slave transmitter, and burst mode enabled (1) slave receiver this mode allows the module to receive a serial bit stream from another device and store it in memory. the shift register clock can be supplied from an external device or from an internal clock. the word select pin is used as an input flow control. assuming that swsp = 0 if ssi_ws is high then the module will receive the bit stream in blocks of 32 bits, one data bit per clock. if ssi_ws goes low then the module will complete the current 32-bit block and then stop any further reception, until ssi_ws goes high again. (2) slave transmitter this mode cannot be used.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1010 of 1286 rej09b0158-0100 (3) master receiver this mode allows the ssi module to receive a serial bit stream from another device and store it in memory. the shift register clock can be supplied from an external device or from an internal clock. the word select pin is used as an output flow control. the module always asserts the word select signal to indicate it can receive more data continuou sly. it is the responsibi lity of the host cpu to ensure it can transmit data to the ssi module in time to ensure no data is lost. (4) master transmitter this mode allows the module to transmit a serial bit stream from internal memory to another device. the shift register clock can be supplied from an external device or from an internal clock. the word select pin is used as an output flow control. the module always asserts the word select signal to indicate it will transmit more data conti nuously. word select signal is not asserted until the first word is ready to transmit however. it is the responsibility of the receiving device to ensure it can receive the serial data in time to ensure no data is lost. when the configuration for data transfer is completed, the ssi module can work with the minimum interaction with cpu. the cpu specifi es settings for the ssi module and dmac then handles overflow/ underflow interrupts if required.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1011 of 1286 rej09b0158-0100 26.4.4 operation modes there are three modes of operation: configuration, enabled and disabled. figure 26.20 shows the transition diagram between these operation modes. module configration (after reset) module enabled (normal tx/rx) en = 1 (idst = 0) module disabled (waiting until bus inactive) en = 0 (idst = 0) en = 0 (idst = 1) reset figure 26.20 transition diagram between operation modes (1) configuration mode this mode is entered after the module is released from reset. all required settings in the control register should be defined in this mode, before the ssi module is enabled by setting the en bit. setting the en bit causes the ssi module to enter the module enabled mode. (2) module enabled mode: operation of the module in this mode depends on the selected operating mode. for details, see section 26.4.5, transmit operation an d section 26.4.6, receive operation.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1012 of 1286 rej09b0158-0100 26.4.5 transmit operation transmission can be controlled in one of two ways: either dma or an interrupt driven. dma driven is preferred to reduce the cpu load. in dma control mode, an underflow or overflow of data or dmac transfer end is notified by using an interrupt. the alternative is using the interrupts that the ssi module generates to supply data as required. this mode has a higher interrupt load as the ssi module is only double buffered and will require data to be written at least every system word period. when disabling the ssi module, the ssi clock* must be supplied continuously until the module enters in the idle state, indicated by the iirq bit. figure 26.21 shows the transmit operation in the dma controller mode. figure 26.22 shows the transmit operation in the interrupt controller mode. note: * sckd = 0: clock input through the ssi_sck pin sckd = 1: clock input through the ssi_clk pin
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1013 of 1286 rej09b0158-0100 (1) transmission using dma controller release reset, specify configuration bits in ssicr start setup dma controller to provide data as required for transmission enable ssi module, enable dma, enable error interrupts wait for interrupt from dmac or ssi ssi error interrupt? has dmac tx data been completed? more data to be send? disable ssi module, disable dma disable error interrupt, enable idle interrupt wait for idle interrupt from ssi module reset ssi module if required end * note: * when ssi error interrupt occurs (underflow/overflow), back to start and execute flow again. yes no no yes yes no specify trmd, en, sckd, swsd, muen, del, pdta, sdta, spdp, swsp, sckp, swl, dwl, chnl en = 1, dmen = 1, uien = 1, oien = 1 en = 0, dmen = 0 uien = 0, oien = 0, iien = 1 figure 26.21 transmission using dma controller
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1014 of 1286 rej09b0158-0100 (2) transmission using int errupt data flow control release reset, specify configuration bits in ssicr start enable ssi module, enable dma, enable error interrupts wait for interrupt from ssi data interrupt? more data to be send? disable ssi module, disable dma disable error interrupt, enable idle interrupt wait for idle interrupt from ssi module reset ssi module if required end no yes yes no specify trmd, en, sckd, swsd, muen, del, pdta, sdta, spdp, swsp, sckp, swl, dwl, chnl en = 1, dien = 1, uien = 1, oien = 1 use ssi status register bits to realign data after underflow/overflow en = 0, dien = 0 uien = 0, oien = 0, iien = 1 load data of channel n for n = ( (chnl + 1) x 2) loop next channel figure 26.22 transmission usin g interrupt data flow control
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1015 of 1286 rej09b0158-0100 26.4.6 receive operation as with transmission the reception can be contro lled in one of two ways: either dma or an interrupt driven. figures 26.23 and 26.24 show the flow of operation. when disabling the ssi module, the ssi clock must be supplied continuously until the module enters in the idle state, which is indicated by the iirq bit. note: * sckd = 0: clock input through the ssi_sck pin sckd = 1: clock input through the ssi_clk pin
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1016 of 1286 rej09b0158-0100 (1) reception using dma controller no yes no release reset, specify configuration bits in ssicr setup dma controller to transfer data from ssi module to memory enable ssi module, enable dma, enable error interrupts wait for interrupt from dmac or ssi ssi error interrupt? has dmac rx data been completed? more data to be received? disable ssi module, disable dma disable error interrupt, enable idle interrupt wait for idle interrupt from ssi module reset ssi module if required end * note: * when ssi error interrupt occurs (underflow/overflow), back to start and execute flow again. specify trmd, en, sckd, swsd, muen, del, pdta, sdta, spdp, swsp, sckp, swl, dwl, chnl en = 1, dmen = 1, uien = 1, oien = 1 en = 0, dmen = 0 uien = 0, oien = 0, iien = 1 start yes no yes figure 26.23 reception using dma controller
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1017 of 1286 rej09b0158-0100 (2) reception using interr upt data flow control release reset, specify configuration bits in ssicr start enable ssi module, enable data interrupt, enable error interrupts wait for interrupt from ssi ssi error interrupt? more data to be received? disable ssi module, disable data interrupt disable error irq, enable idle irq wait for idle interrupt from ssi module reset ssi module if required end yes no yes no specify trmd, en, sckd, swsd, muen, del, pdta, sdta, spdp, swsp, sckp, swl, dwl, chnl en = 1, dien = 1, uien = 1, oien = 1 use ssi status register bits to realign data after underflow/overflow en = 0, dien = 0 uien = 0, oien = 0, iien = 1 read data from receive data register figure 26.24 reception using interrupt data flow control
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1018 of 1286 rej09b0158-0100 when an underflow or overflow error condition is met, the chno[1:0] and swno bits can be used to recover the ssi module to a known stat us. when an underflow or overflow occurs, the host cpu can read the number of channels and the number of system wo rds to determine what point the serial audio stream has reached. in th e transmitter case, the ho st cpu can skip forward through the data it wants to transmit until it finds the sample data that matches what the ssi module is expecting to transmit next, and so resynchronize with the audio data stream. in the receiver case, the host cpu can skip forward storing null sample data until it is ready to store the sample data that the ssi module is indicating that it will receive next to ensure consistency of the number of received data, and so resynchronize with the audio data stream. 26.4.7 serial clock control this function is used to control and select which clock is used for the serial bus interface. if the serial clock direction is set to input (sckd = 0), the ssi module is in clock slave mode, then the bit clock that is used in the shift register is derived from the ssi_sck pin. if the serial clock direction is set to output (sckd = 1), the ssi module is in clock master mode, and the shift register uses the bit clock derived from the hac_bit_clk input pin or its clock divided. this input clock is then divided by the ratio in the serial oversampling clock division ratio (ckdv) bit in ssicr and used as the bit clock in the shift register. in either case, the ssi_sck pin output is the same as the bit clock.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1019 of 1286 rej09b0158-0100 26.5 usage note 26.5.1 restrictions when an overflow occurs during receive dma operation if an overflow occurs during receive dma op eration, the module mu st be reactivated. the receive buffer of ssi has 32-bit common regist er both left channel and right channel. if an overflow occurs under the condition of control register (ssicr) data-word length (dwl2 to dwl0) is 32-bit and syst em-word length (swl2 to swl0) is 32-bit, ssi ha s received the data at right channel that should be received at left channel. if an overflow occurs through an overflow error in terrupt or overflow error status flag (the oirq bit in ssisr), disable the dma tran sfer of the ssi to halt its opera tion by writing 0 to the en bit and dmen bit in ssicr (then terminate the dma se tting). and clear the ove rflow status flag by writing 0 to the oirq bit, set the dma again and transfer restart.
section 26 serial sound interface (ssi) module rev.1.00 dec. 13, 2005 page 1020 of 1286 rej09b0158-0100
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1021 of 1286 rej09b0158-0100 section 27 nand flash me mory controller (flctl) the nand flash memory contro ller (flctl) provides interfaces for an external nand-type flash memory. 27.1 features nand-type flash memory interface: ? ? ? ? ? ? ? ?
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1022 of 1286 rej09b0158-0100 data error: ? ? ? ? ? ? ? ? ? ? ? fre and fwe pins operate with the frequency (fclk) on the pins which common control register (flcmncr) designated. to ensure the setup time, this operating frequencies must be specified within the maximum operating frequency of memory to be connected.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1023 of 1286 rej09b0158-0100 figure 27.1 shows a block diagram of the flctl. dmac 32 32 flash if nand flash fifo 256 bytes 32 4 8 8 8 32 32 cpg fcksel 1, 1/2, 1/4 fclk dma transfer requests (2 lines) peripheral bus peripheral bus interface interrupts (flste, fltend, fltrq0, fltrq1) registers interrupt control transmission/ reception control control signal note: fclk is an operating clock for interface signals with flash memory. qtsel peripheral clock pck flctl figure 27.1 flctl block diagram
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1024 of 1286 rej09b0158-0100 27.2 input/output pins the pin configuration of the flctl is listed in table 27.1. table 27.1 pin configuration corresponding flash memory pin pin name function i/o nand type description fce * 1 chip enable output ce enables flash memory connected to this lsi. fd7 to fd0 * 2 data i/o pins i/o i/o7 to i/o0 i/o pins for command, address, and data. fcle * 3 command latch enable output cle command latch enable (cle) asserted when a command is output. fale * 1 output enable output ale address latch enable (ale) asserted when an address is output and negated when data is input or output. fre * 4 read enable output re read enable ( re ) reads data at the falling edge of re . fwe * 5 write enable output we write enable flash memory latches a command, address, and data at the rising edge of we . frb * 4 ready/busy input r/ b ready/busy indicates ready state at high level; indicates busy state at low level. ? ? ? wp write protect/reset (not supported) when this pin goes low, erroneous erasure or programming at power on or off can be prevented. fse * 4 spare area enable output se spare area enable used to access spare area. this pin must be fixed at low in sector access mode. notes: 1. these pins are multiplexed with the h-udi pins. 2. these pins are multiplexed with t he intc, h-udi, gpio, and mode control pins. 3. this pin is multiplexed with the scif channel 0, pcic, and gpio pin. 4. these pins are multiplexed wi th the scif0, hspi, and gpio pins. 5. this pin is multiplexed with the scif channel 0, hspi, gpio, and mode control pin.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1025 of 1286 rej09b0158-0100 27.3 register descriptions table 27.2 shows the flctl regist er configuration. table 27.3 sh ows the register states in each processing mode. table 27.2 register configuration of flctl register name abbreviation r/w p4 address area 7 address access size common control register flcmncr r/w h'ffe9 0000 h'1fe9 0000 32 command control register flcmdcr r/w h'ffe9 0004 h'1fe9 0004 32 command code register flcmcdr r/w h'ffe9 0008 h'1fe9 0008 32 address register fladr r/w h'ffe9 000c h'1fe9 000c 32 data register fldatar r/w h'ffe9 0010 h'1fe9 0010 32 data counter register fldtcntr r/w h'ffe9 0014 h'1fe9 0014 32 interrupt dma control register flintdmacr r/w h'ffe9 0018 h'1fe9 0018 32 ready busy timeout setting register fl bsytmr r/w h'ffe9 001c h'1fe9 001c 32 ready busy timeout counter flbsycnt r h'ffe9 0020 h'1fe9 0020 32 data fifo register fldtfifo r/w h'ffe9 0024 h'1fe9 0024 32 control code fifo register flecfifo r/w h'ffe9 0028 h'1fe9 0028 32 transfer control register fltrcr r/w h'ffe9 002c h'1fe9 002c 8 table 27.3 register states of flctl in each processing mode register abbreviation power-on reset manual reset module standby sleep flcmncr h'0000 0000 h'0000 0000 retained retained flcmdcr h'0000 0000 h'0000 0000 retained retained flcmcdr h'0000 0000 h'0000 0000 retained retained fladr h'0000 0000 h'0000 0000 retained retained fldatar h'0000 0000 h'0000 0000 retained retained fldtcntr h'0000 0000 h'0000 0000 retained retained flintdmacr h'0000 0000 h'0000 0000 retained retained flbsytmr h'0000 0000 h'0000 0000 retained retained flbsycnt h'0000 0000 h'0000 0000 retained retained fldtfifo h'xxxx xxxx h'xx xx xxxx retained retained flecfifo h'xxxx xxxx h'xx xx xxxx retained retained fltrcr h'00 h'00 retained retained
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1026 of 1286 rej09b0158-0100 27.3.1 common control register (flcmncr) flcmncr is a 32-bit readable/writable register th at specifies the type (nand) of flash memory, access mode, and fce pin output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrr/wr 0000000000000000 r/w r r/w r/w r/w r/w r/w r/w r r r r r/w r r r/w bit: initial value: r/w: bit: initial value: r/w: qtsel fck sel eccpos[1:0] acm[1:0] nand wf se ce0 type sel bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 qtsel 0 r/w fourth-divided flash clock select 0: uses the value in fcksel 1: divides a peripheral clock (pck) provided from the cpg by four and uses it as fclk when fcksel = 0 note: when fcksel = 1, setting to 1 to this bit is prohibited. 16 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 15 fcksel 0 r/w flash clock select 0: divides a peripheral clock (pck) provided from the cpg by two and uses it as fclk 1: uses a peripheral clock (pck) provided from the cpg as fclk 14 ? 0 r reserved this bit is always read as 0. the write value should always be 0.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1027 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13, 12 eccpos [1:0] 00 r/w ecc position specification 1 and 0 specify the position (0/4th/8th byte) to place the ecc in the control code area. 00: places the ecc at the 0 to 7th byte of control code area 01: places the ecc at the 4t h to 11th byte of control code area 10: places the ecc at the 8t h to 15th byte of control code area 11: setting prohibited 11, 10 acm[1:0] 00 r/w acce ss mode specification 1 and 0 specify access mode. 00: command access mode 01: sector access mode 10: setting prohibited 11: setting prohibited 9 nandwf 0 r/w nand wait insertion operation 0: performs address or data input/output in one fclk cycle 1: performs address or data input/output in two fclk cycles 8 se 0 r/w spare area (control code area) enable bit 0: spare area access enable (can be access the data area and the control code area continuously) 1: spare area access disable in sector access mode, clear this bit to 0. 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ce0 0 r/w chip enable 0 0: disables the chip (outputs high level to the fce pin) 1: enables the chip (outputs low level to the fce pin) 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 typesel 0 r/w memory select 0: reserved 1: nand-type flash memory is selected note: set typesel to 1 to use flctl.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1028 of 1286 rej09b0158-0100 27.3.2 command control register (flcmdcr) flcmdcr is a 32-bit readable/wr itable register that issues a command in command access mode, specifies address issue, and specifi es source or destination of data transfer. in sector access mode, flcmdcr specifies the number of sector transfers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 151413121110987654321 0 0000000000000000 r r r r r r/w r/w r/w r r r/w r/w r/w r/w r/w r/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: adrmd cdsrc dosr selrw doadr adrcnt[1:0] docmd2 docmd1 sctcnt[15:0] bit bit name initial value r/w description 31 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 26 adrmd 0 r/w sector access address specification this bit is invalid in comma nd access mode. this bit is valid only in sector access mode. 0: the value of the address register is handled as a physical sector number. use this value usually in sector access. 1: the value of the address register is output as the address of flash memory. note: clear this bit to 0 in continuous sector access. 25 cdsrc 0 r/w data buffer specification specifies the data buffer to be read from or written to in the data stage * in command access mode. 0: specifies fldatar as the data buffer. 1: specifies fldtfifo as the data buffer. 24 dosr 0 r/w status read check specifies whether or not t he status read is performed after the second command has been issued in command access mode. 0: performs no status read 1: performs status read
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1029 of 1286 rej09b0158-0100 bit bit name initial value r/w description 23, 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 selrw 0 r/w data re ad/write specification specifies the direction of re ad or write in data stage. 0: read 1: write 20 doadr 0 r/w address sta ge execution specification specifies whether or not t he address stage is executed in command access mode. 0: performs no address stage 1: performs address stage 19, 18 adrcnt [1:0] 00 r/w address issue byte count specification specify the number of byte s for the address data to be issued in address stage * . 00: issue 1-byte address 01: issue 2-byte address 10: issue 3-byte address 11: issue 4-byte address 17 docmd2 0 r/w second command stage execution specification specifies whether or not the second command stage * is executed in command access mode. 0: does not execute the second command stage 1: executes the second command stage 16 docmd1 0 r/w first command stage execution specification specifies whether or not the first command stage * is executed in command access mode. 0: does not execute the first command stage 1: executes the first command stage 15 to 0 sctcnt [15:0] h'0000 r/w sector transfe r count specification specify the number of sect ors to be read continuously in sector access mode. these bits are counted down for each sector transfer end and st op when they reach 0. in command access mode, these bits become h'0001. when accessing one sector, set h'0001 to the sctcnt. note: * refer to figure 27.2 for command st age, address stage and data stage.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1030 of 1286 rej09b0158-0100 27.3.3 command code register (flcmcdr) flcmcdr is a 32-bit readable/writable register that specifies a command to be issued in command access or sector access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrrr 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: cmd[15:8] cmd[7:0] bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 8 cmd[15:8] h'00 r/w specify a command code to be issued in the second command stage. 7 to 0 cmd[7:0] h'00 r/ w specify a command code to be issued in the first command stage. 27.3.4 address register (fladr) fladr is a 32-bit readable/writabl e register that specifies an ad dress to be output in command access mode. in sector access mode , a physical sector number sp ecified in the physical sector address bits is converted into an address to be output. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: adr[31:24] adr[23:16] adr[15:8] adr[7:0]
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1031 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 24 adr[31:24] h'00 r/w fourth address data specify 4th data to be output to flash memory as an address in command access mode. 23 to 16 adr[23:16] h'00 r/w third address data specify 3rd data to be output to flash memory as an address in command access mode. 15 to 8 adr[15:8] h'00 r/w second address data specify 2nd data to be output to flash memory as an address in command access mode. 7 to 0 adr[7:0] h'00 r/w first address data specify 1st data to be output to flash memory as an address in command access mode. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 rrrrrrrrrrrrrrr/wr/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: adr[17:16] adr[15:0] bit bit name initial value r/w description 31 to 18 ? undefined r reserved these bits are always read as an undefined value (depends on the flctl operation mode). the write value should always be 0. 17 to 0 adr[17:0] h'00000 r/ w physical sector address specify a physical sector number to be accessed in sector access mode. the physical sector number is converted into an address and is output to flash memory.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1032 of 1286 rej09b0158-0100 27.3.5 data counter register (fldtcntr) fldtcntr is a 32-bit readable/writable register that specifies the number of bytes to be read or written in command access mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrrr 0000000000000000 r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: ecflw[7:0] dtflw[7:0] dtcnt[11:0] bit bit name initial value r/w description 31 to 24 ecflw[7:0] h'00 r flecfifo access count specify the number of longwords (4-byte) in flecfifo to be read or written. these bit values are used when the cpu reads from or writes to flecfifo. in flecfifo read, these bi ts specify the number of longwords of the data that can be read from flecfifo. in flecfifo write, these bi ts specify the number of longwords of empty area that can be written in flecfifo. 23 to 16 dtflw[7:0] h'00 r fldtfifo access count specify the number of longwords (4-byte) in fldtfifo to be read or written. these bit values are used when the cpu reads from or writes to fldtfifo. in fldtfifo read, these bi ts specify the number of longwords of the data that can be read from fldtfifo. in fldtfifo write, these bi ts specify the number of longwords of empty area that can be written in fldtfifo. 15 to 12 ? ali 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 dtcnt[11:0] h'000 r/w data count specification specify the number of bytes of data to be read or written in command access mode. (up to 2048 + 64 bytes can be specified.)
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1033 of 1286 rej09b0158-0100 27.3.6 data register (fldatar) fldatar is a 32-bit readable/writable register. it st ores input/output data used when 0 is written to the cdsrc bit in flcm dcr in command access mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: dt[31:24] dt[23:16] dt[15:8] dt[7:0] bit bit name initial value r/w description 31 to 24 dt[31:24] h' 00 r/w fourth data specify the 4th data to be inpu t or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 23 to 16 dt[23:16] h' 00 r/w third data specify the 3rd data to be inpu t or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 15 to 8 dt[15:8] h'00 r/w second data specify the 2nd data to be in put or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 7 to 0 dt[7:0] h'00 r/w first data specify the 1st data to be inpu t or output via the fd7 to fd0 pins. in write: specify write data in read: store read data
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1034 of 1286 rej09b0158-0100 27.3.7 interrupt dma control register (flintdmacr) flintdmacr is a 32-bit readable/writable regist er that enables or di sables dma transfer requests or interrupts. a transf er request from the fl ctl to the dmac is issued after each access mode has been started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r r r r r r r r r r r/w r/w r/w r/w r/w r/w 000000 000000000 r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: fifotrg[1:0] ac1 clr ac0 clr dreq1 en dreq0 en ste rb bto erb trr eqf1 trr eqf0 ster inte rber inte te inte tr inte1 tr inte0 bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1035 of 1286 rej09b0158-0100 bit bit name initial value r/w description 21, 20 fifotrg [1:0] 00 r/w fifo trigger setting change the condition for the fifo transfer request. in flash-memory read: 00: issue an interrupt to the cpu or a dma transfer request to the dmac when fldtfifo stores 4 bytes of data. 01: issue an interrupt to the cpu or a dma transfer request to the dmac when fldtfifo stores 16 bytes of data. 10: issue an interrupt to the cpu or a dma transfer request to the dmac when fldtfifo stores 128 bytes of data. 11: issue an interrupt to the cpu when fldtfifo stores 128 bytes of data, or issue a dma transfer request to the dmac when fldtfifo stores 16 bytes of data. in flash-memory programming: 00: issue an interrupt to the cpu when fldtfifo has empty area of 4 bytes or more (do not set dma transfer). 01: issue an interrupt or a dma transfer request to the cpu when fldtfifo has empty area of 16 bytes or more. 10: issue an interrupt to the cpu when fldtfifo has empty area of 128 bytes or more (do not set dma transfer). 11: issue an interrupt to the cpu when fldtfifo has empty area of 128 bytes or more, or issue a dma transfer request to the cpu when fldtfifo has empty area of 16 bytes or more. 19 ac1clr 0 r/w flecfifo clear clears the address counter of flecfifo. 0: retains the address counter value of flecfifo. in flash-memory access, this bit should be cleared to 0. 1: clears the address counter of flecfifo. after clearing the counter, this bit should be cleared to 0.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1036 of 1286 rej09b0158-0100 bit bit name initial value r/w description 18 ac0clr 0 r/w fldtfifo clear clears the address counter of fldtfifo. 0: retains the address counter value of fldtfifo. in flash-memory access, this bit should be cleared to 0. 1: clears the address counter of fldtfifo. after clearing the counter, this bit should be cleared to 0. 17 dreq1en 0 r/w flecfifodma request enable enables or disables the dma transfer request issued from flecfifo. 0: disables the dma transfer request issued from flecfifo 1: enables the dma transfer request issued from flecfifo 16 dreq0en 0 r/w fldtfifodma request enable enables or disables the dma transfer request issued from fldtfifo. 0: disables the dma transfer request issued from the fldtfifo 1: enables the dma transfer request issued from the fldtfifo 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 ? 0 r reserved although the initial value is 0, this bit will be read as an undefined value. the write value should always be 0. 8 sterb 0 r/w status error indicates the result of status read. this bit is set to 1 if the specific bit in the bits stat[7:0] in flbsycnt is set to 1 in status read. this bit is a flag. 1 cannot be written to this bit. only 0 can be written to clear the flag. 0: indicates that no status error occurs (the specific bit in the bits stat[7:0] in flbsycnt is 0.) 1: indicates that a status error occurs for details on the specific bit in stat7 to stat0 bits, see section 27.4.5, status read.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1037 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 btoerb 0 r/w timeout error this bit is set to 1 if a timeout error occurs (the bits rbtimcnt[19:0] in flbsycnt are decremented to 0). this bit is a flag. 1 cannot be written to this bit. only 0 can be written to clear the flag. 0: indicates that no timeout error occurs 1: indicates that a timeout error occurs 6 trreqf1 0 r/w flecfifo transfer request flag indicates that a transfer request is issued from flecfifo. this bit is a flag. 1 cannot be written to this bit. only 0 can be written to clear the flag. 0: indicates that no transfer request is issued from flecfifo 1: indicates that a transfer request is issued from flecfifo 5 trreqf0 0 r/w fldtfifo transfer request flag indicates that a transfer request is issued from fldtfifo. this bit is a flag. 1 cannot be written to this bit. only 0 can be written to clear the flag. 0: indicates that no transfer request is issued from fldtfifo 1: indicates that a transfer request is issued from fldtfifo 4 sterinte 0 r/w interrupt enable at status error enables or disables an interrupt request to the cpu when a status error has occurred. 0: disables the interrupt request to the cpu by a status error 1: enables the interrupt reque st to the cpu by a status error
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1038 of 1286 rej09b0158-0100 bit bit name initial value r/w description 3 btointe 0 rw interrupt enable at timeout error enables or disables an interrupt request to the cpu when a timeout error has occurred. 0: disables the interrupt request to the cpu by a timeout error 1: enables the interrupt request to the cpu by a timeout error 2 teinte 0 r/w transfer end interrupt enable enables or disables an interrupt request to the cpu when a transfer has been ended (trend bit in fltrcr). 0: disables the transfer end interrupt request to the cpu 1: enables the transfer end interrupt request to the cpu 1 trinte1 0 r/w flecfifo transfer request enable to cpu enables or disables an interrupt request to the cpu by a transfer request issued from flecfifo. 0: disables an interrupt request to the cpu by a transfer request from flecfifo. 1: enables an interrupt request to the cpu by a transfer request from flecfifo. when the dma transfer is enabled, this bit should be cleared to 0. 0 trinte0 0 r/w fldtfifo transfer request enable to cpu enables or disables an interrupt request to the cpu by a transfer request issued from fldtfifo. 0: disables an interrupt request to the cpu by a transfer request from fldtfifo 1: enables an interrupt request to the cpu by a transfer request from fldtfifo when the dma transfer is enabled, this bit should be cleared to 0.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1039 of 1286 rej09b0158-0100 27.3.8 ready busy timeout setting register (flbsytmr) flbsytmr is a 32-bit readable/writable register that specifies the timeout time when the frb pin is busy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r r r r r r r r r r r r r/w r/w r/w r/w 0000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: rbtmout[19:16] rbtmout[15:0] bit bit name initial value r/w description 31 to 20 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 19 to 0 rbtmout[19:0] h'000 00 r/w ready busy timeout specify timeout time h'0000 0: setting prohibited h'0000 1: 1 pck cycle h'0000 2 or more: (setting value - 1) x 2 pck cycles
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1040 of 1286 rej09b0158-0100 27.3.9 ready busy timeout counter (flbsycnt) flbsycnt is a 32-bit read-only register. the status of flash memory obta ined by the status read is stored in the bits stat[7:0]. the timeout time set in the bits rbtmout[19: 0] in flbsytmr is copied to the bits rbtimcnt[19:0] and counting down is started when the frb pin is placed in a busy state. when values in the rbtimcnt[19:0] become 0, 1 is set to the btoerb bit in flintdmacr, thus notifying that a timeout error has occurred. in this case, an flste interrup t request can be issued if an interrupt is enabled by the rberinte bit in flintdmacr. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrrr 0000000000000000 rrrrrrrrrrrrrrrr bit: initial value: r/w: bit: initial value: r/w: stat[7:0] rbtimcnt[19:16] rbtimcnt[15:0] bit bit name initial value r/w description 31 to 24 stat[7:0] h'00 r indicate the flash memory status obtained by the status read. 23 to 20 ? all 0 r reserved these bits are always read as 0. 19 to 0 rbtimcnt[19:0] h'00000 r ready busy timeout counter when the frb pin is placed in a busy state, the values of the bits rbtmout[19:0] in flbsytmr are copied to these bits. these bits are counted down while the frb pin is busy. a timeout error occurs when these bits are decremented to 0.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1041 of 1286 rej09b0158-0100 27.3.10 data fifo register (fldtfifo) fldtfifo is used to read or write the data fifo area. note that the direction of read or write speci fied by the selrw bit in flcmdcr must match that specified in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: dtfo[31:24] dtfo[23:16] dtfo[15:8] dtfo[7:0] ???????????????? ???????????????? bit bit name initial value r/w description 31 to 24 dtfo[31:24] undefined r/w first data specify 1st data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 23 to 16 dtfo[23:16] undefined r/w second data specify 2nd data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 15 to 8 dtfo[15:8] undefined r/w third data specify 3rd data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 7 to 0 dtfo[7:0] undefined r/w fourth data specify 4th data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1042 of 1286 rej09b0158-0100 27.3.11 control code fifo register (flecfifo) flecfifo is used to read or write the control code fifo area. note that the direction of read or write speci fied by the selrw bit in flcmdcr must match that specified in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit: initial value: r/w: ecfo[31:24] ecfo[23:16] ecfo[15:8] ecfo[7:0] ???????????????? ???????????????? bit bit name initial value r/w description 31 to 24 ecfo[31:24] undefined r/w first data specify 1st data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 23 to 16 ecfo[23:16] undefined r/w second data specify 2nd data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 15 to 8 ecfo[15:8] undefined r/w third data specify 3rd data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data 7 to 0 ecfo[7:0] undefined r/w fourth data specify 4th data to be input or output via the fd7 to fd0 pins. in write: specify write data in read: store read data
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1043 of 1286 rej09b0158-0100 27.3.12 transfer control register (fltrcr) setting the trstrt bit to 1 initiates access to fl ash memory. access completion can be checked by the trend bit. 7654321 0 00000000 rrrrrrr/w r/w bit: initial value: r/w: trend trstrt bit bit name initial value r/w description 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 trend 0 r/w processing end flag bit indicates that the processing performed in the specified access mode has been completed. the write value should always be 0. 0 trstrt 0 r/w transfer start by setting this bit from 0 to 1 when the trend bit is 0, processing in the access mode specified by the access mode specification bits ac m[1:0] is initiated. 0: stops transfer 1: starts transfer
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1044 of 1286 rej09b0158-0100 27.4 operation 27.4.1 operating modes two operating modes are supported. ? ? cle command stage address stage data stage ale we re i/o7 to i/o0 r/ b h'00 a2 a1 a3 1 2 3 4 58 figure 27.2 read operation timing for nand-type flash memory (1)
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1045 of 1286 rej09b0158-0100 figures 27.3 and 27.4 show examples of programming operation for nand-type flash memory. cle ale we re i/o7 to i/o0 r/ b h'80 a2 a1 a3 1 2 3 4 5 8 figure 27.3 programming operation timing for nand-type flash memory (1) cle ale we re i/o7 to i/o0 r/ b h'10 h'70 status figure 27.4 programming operation timing for nand-type flash memory (2)
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1046 of 1286 rej09b0158-0100 27.4.3 sector access mode in sector access mode, flas h memory can be read or programmed in sector units by specifying the number of physical sectors to be accessed. since 512-byte data is stored in fldtfifo and 16-byte control code is stored in flecfifo, the dreq1en and dreq0en bits in flintdmacr can be set to transfer by the dma. figure 27.5 shows the relationship of dma transfer between sectors in flash memory (data and control code) and memory on the address space. flctl fldt fifo flec fifo flash memory data (512 bytes) control code (16 bytes) dma (channel 0) transfer dma (channel 1) transfer address area (external memory area) data area control code area figure 27.5 relationship between dma transfer and sector (data and control code), and memory and dma transfer
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1047 of 1286 rej09b0158-0100 physical sector: figure 27.6 shows the relationship between the physical sector address of nand-type flash memory and the address of flash memory. bit17 bit0 3rd 3rd 4th 4th 2nd 2nd 1st 00000000 bit17 bit0 00 00 0 0 1st 2nd 3rd 4th physical sector address for nand-type flash memory physical sector address bit (fladr17 to fladr0) order of address output to nand-type flash memory i/o figure 27.6 relationship between s ector number and address expansion of nand-type flash memory
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1048 of 1286 rej09b0158-0100 continuous s ector access: continuous physical sectors can be read or written by specifying the start physical sector of nand-type flash memory and the number of sectors to be transferred. figure 27.7 shows an example of physical sector specification register and transfer count specification register settings when transferring logical sectors 0 to 40, which are not contiguous because of an unusable sector in nand-type flash memory. 00 12 0 0 11 11 12 13 13 40 40 300 12 300 1 13 28 physical sector values specified in registers by the cpu. physical sector specification register sector transfer count specification register sector 0 to sector 11 are transferred sector 12 is transferred sector 13 to sector 40 are transferred logical sector transfer start transfer start transfer start (fladr, adr17 to 0) (flcmdcr,sctcnt) figure 27.7 sector access when unusable sector exis ts in continuous sectors 27.4.4 ecc error correction the flctl does not perform ecc processing. an ecc generation, error detection and correction must be performed by software.
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1049 of 1286 rej09b0158-0100 27.4.5 status read the flctl can read the status register of a n and-type flash memory. the data in the status register of a nand-type flash memory is input through the i/o7 to i/o0 pins and stored in the bits stat[7:0] in flbsycnt. the bits stat[7:0] in flbsycnt can be read by the cpu. if a program error or erase error is de tected when the status register value is stored in the bits stat[7:0] in flbsycnt, the sterb bit in flintdmacr is set to 1 and generates an interrupt to the cpu if the sterinte bit in flintdmacr is enabled. status read of nand-type flash memory: the status register of nand-type flash memory can be read by inputting command h'70 to nand-type flash memory. if programming is executed in command access mode or sector access mode while the dosr bit in flcm dcr is set to 1, the flctl automatically inputs command h'70 to nand-type flash memory and reads the status register of nand-type flash memory. when the status register of nand-type flash memory is read, the i/o7 to i/o0 pins indicate the following informatio n as described in table 27.4. table 27.4 status read of nand-type flash memory i/o status (definition) description i/o7 program protection 0: cannot be programmed 1: can be programmed i/o6 ready/busy 0: busy state 1: ready state i/o5 to i/o1 reserved ? i/o0 program/erase 0: pass 1: fail
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1050 of 1286 rej09b0158-0100 27.5 example of register setting figure 27.8 to 28.10 show examples of regist er setting and processing flow in each access mode. command access (block erase) yes no set common control register (flcmncr) acm [1:0] = 00 (command access mode) ce0 = 1 (chip enable) typesel = 1 (select nand type flash memory) command control register (flcmdcr) docmd1 = 1 (perform 1st command stage) docmd2 = 1 (perform 2nd command stage) doadr = 1 (perform address stage) adrmd = 1 (address register value is output as memory address) adrcnt [1:0] = 01 (issue 2-byte address) dosr = 1 (perform status read) command code register (flcmcdr) cmd [7:0] = h'60 (block erase command) cmd [15:8] = h'd0 (block erase execute command) address register (fladr) set erase address to adr[7:0], adr[15:8] transfer control register (fltrcr) trstrt = 1 (start flash memory accessing) perform block erase of flash memory issue first command issue address issue second command read status fltrcr.trend = 1? end of flash memory access fltrcr.trend = 0 (clear processing end flag) read status check status (flbsycnt.stat [7:0]) end figure 27.8 nand flash command access (block erase)
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1051 of 1286 rej09b0158-0100 sector access (flash write) yes no set common control register (flcmncr) acm [1:0] = 01 (sector access mode) ce0 = 1 (chip enable) typesel = 1 (nand flash memory) specify ecc position to eccpos [1:0] set command control register (flcmdcr) selrw = 1 (flash write) docmd1 = 1 (perform first command stage) docmd2 = 1 (perform second command stage) doadr = 1 (perform address stage) adrmd = 1 (specify sector access address) adrcnt [1:0] = 10 (issue 3-byte address) dosr = 1 (perform status read) specify number of sector transfer to sctcnt [15:0] set command code register (flcmcdr) cmd [7:0] = h'80 (flash write command) cmd [15:8] = h'10 (flash write execute command) set interrupt dma control register (flintdmacr) dreq1en = 1 (enable dma transfer request from flecfifo) dreq0en = 1 (enable dma transfer request from fldtfifo) set address register (fladr) specify physical sector address to adr [17:0] set transfer control register (fltrcr) trstrt = 1 (transfer start) set interrupt dma control register (flintdmacr) dreq1en = 1 (enable dma transfer request from flecfifo) dreq0en = 1 (enable dma transfer request from fldtfifo) perform flash memory writing issue first command issue address data stage (sector access) issue second command read status fltrcr.trend = 1? end of flash memory access fltrcr.trend = 0 (clear processing end flag) read status check flbsycnt.stat [7:0] end set dmac related registers (example of channel 0, 1) 1. dma source address registers (sar0, sar1) sar0 [31:0]: set start address of writing data sar1 [31:0]: set start address of writing control code 2. dma destination address registers (dar0, dar1) dar0 [31:0]: set fldtfifo address dar1 [31:0]: set flecfifo address 3. dma transfer count registers (tcr0, tcr1) tcr0 [31:0] = h'0000 0080 (512 bytes = 4 x 128) tcr1 [31:0] = h'0000 0004 (16 bytes = 4 x 4) 4. dma channel control registers (chcr0, chcr1) sm [1:0] = 01 (source address is incremented) rs [3:0] = 1000 (on-chip peripheral module request) ts [2:0] = 010 (longword) de = 1 (dma transfer enable) 5. dma extended resource selector (dmars0) dmars0 [15:0] = h'8783 (flctl control code and data part transmit and receive) set dma operation register (dmaor0) dme = 1 (enable channel 0 to 5 transfer) figure 27.9 nand flash sector access (flash write) using dma
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1052 of 1286 rej09b0158-0100 command access (flash read) yes no set common control register (flcmncr) acm [1:0] = 00 (command access mode) ce0 = 1 (chip enable) typesel = 1 (select nand type flash memory) set command control register (flcmdcr) docmd1 = 1 (perform first command stage) doadr = 1 (perform address stage) adrmd = 1 (address register value is output as memory address) adrcnt [1:0] = 10 (issue 3-byte address) dosr = 1 (perform status read) set command code register (flcmcdr) cmd [7:0] = h'00 (flash read) address register (fladr) set address to adr [7:0], adr [15:8], adr [23:16] data counter register (fldtcntr) specify number of bytes of read data to dtcnt [11:0] interrupt dma control register (flintdmacr) set enable bit of dma transfer or interrupt request in use set transfer control register (fltrcr) trstrt=1 (start flash memory accessing) perform flash memory reading issue first command issue address issue second command read status fltrcr.trend = 1? end of flash memory access fltrcr.trend = 0 (clear processing end flag) read status check status (flbsycnt.stat [7:0]) end figure 27.10 nand flash command access (flash read)
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1053 of 1286 rej09b0158-0100 27.6 interrupt sources the flctl has six interrupt sources: status error, ready/busy timeout error, ecc error, transfer end, fifo0 transfer request, and fifo1 transfer request. each of the interrupt sources has its corresponding interrupt flag and the interrupt can be requested independently to the cpu if the interrupt is enabled by the interrupt enable bit. note that the status error and ready/busy timeout error use the common flste interrupt to the cpu. table 27.5 flctl interrupt requests interrupt source interrupt flag enable bit description sterb sterinte status error flste interrupt btoerb rberinte ready/busy timeout error fltend interrupt trend teinte transfer end fltrq0 interrupt trreqf0 trinte0 fifo0 transfer request fltrq1 interrupt trreqf1 trinte1 fifo1 transfer request note: flags for the fifo0 overrun error/underr un error and fifo1 overrun error/underrun error also exist. however, no interrupt is requested to the cpu. 27.7 dma transfer specifications the flctl can request dma transfers separately to the data area fldtfifo and control code area flecfifo. table 27.6 summarizes dma transf er enable or disable states in each access mode. table 27.6 dma transfer specifications sector access mode command access mode fldtfifo dma transfer enabled dma transfer enabled flecfifo dma transfer enabled dma transfer disabled for details on dmac settings, see section 14 , direct memory acces s controller (dmac).
section 27 nand flash memory controller (flctl) rev.1.00 dec. 13, 2005 page 1054 of 1286 rej09b0158-0100
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1055 of 1286 rej09b0158-0100 section 28 general purpose i/o (gpio) 28.1 features this lsi has twelve general ports (a to h, j to m), which provide 75 input/output pins and 8 output pins in total. each port pins is multiplexed pin with on-chip modules, selected of use whether general purpose i/os (gpio) or on-chip modules by port control register (pacr to phcr and pjcr to pmcr) and on-chip module sel ect register (omselr). the gpio has the following features. ? ? ?
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1056 of 1286 rej09b0158-0100 table 28.1 multiplexed pins cont rolled by port control registers pin name port gpio multiplexed module gpio interrupt ad31 a pa7 input/output pcic ad30 a pa6 input/output pcic ad29 a pa5 input/output pcic ad28 a pa4 input/output pcic ad27 a pa3 input/output pcic ad26 a pa2 input/output pcic ad25 a pa1 input/output pcic ad24 a pa0 input/output pcic ad23 b pb7 input/output pcic ad22 b pb6 input/output pcic ad21 b pb5 input/output pcic ad20 b pb4 input/output pcic ad19 b pb3 input/output pcic ad18 b pb2 input/output pcic ad17 b pb1 input/output pcic ad16 b pb0 input/output pcic ad15 c pc7 input/output pcic ad14 c pc6 input/output pcic ad13 c pc5 input/output pcic ad12 c pc4 input/output pcic ad11 c pc3 input/output pcic ad10 c pc2 input/output pcic ad9 c pc1 input/output pcic ad8 c pc0 input/output pcic ad7 d pd7 input/output pcic ad6 d pd6 input/output pcic ad5 d pd5 input/output pcic ad4 d pd4 input/output pcic ad3 d pd3 input/output pcic ad2 d pd2 input/output pcic
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1057 of 1286 rej09b0158-0100 pin name port gpio multiplexed module gpio interrupt ad1 d pd1 input/output pcic ad0 d pd0 input/output pcic irq/ irl7 /fd7 e pe6 input/output intc/flctl available req1 e pe5 input/output pcic available req2 e pe4 input/output pcic available req3 e pe3 input/output pcic available gnt1 e pe2 input/output pcic available gnt2 e pe1 input/output pcic available gnt3 e pe0 input/output pcic available d31 f pf7 input/output lbsc d30 f pf6 input/output lbsc d29 f pf5 input/output lbsc d28 f pf4 input/output lbsc d27 f pf3 input/output lbsc d26 f pf2 input/output lbsc d25 f pf1 input/output lbsc d24 f pf0 input/output lbsc d23 g pg7 input/output lbsc d22 g pg6 input/output lbsc d21 g pg5 input/output lbsc d20 g pg4 input/output lbsc d19 g pg3 input/output lbsc d18 g pg2 input/output lbsc d17 g pg1 input/output lbsc d16 g pg0 input/output lbsc scif1_sck/mccmd * h ph7 input/output scif1/mmcif scif1_txd/mcclk/mode5 * h ph6 output scif1/mmcif/? scif1_rxd/mcdat * h ph5 input/output scif1/mmcif scif0_sck/hspi_clk/ fre * h ph4 input/output scif0/hspi/flctl scif0_txd/hspi_tx/ fwe /mode8 * h ph3 output scif0/hspi/flctl/? scif0_rxd/hspi_rx/frb * h ph2 input/output scif0/hspi/flctl
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1058 of 1286 rej09b0158-0100 pin name port gpio multiplexed module gpio interrupt scif0_cts / intd /fcle * h ph1 input/output scif0/pcic/flctl available scif0_rts / hspi_cs / fse * h ph0 input/output scif0/hspi/flctl available siof_txd/hac_sdout/ssi_sdata * j pj5 input/output siof/hac/ssi siof_rxd/hac_sdin/ssi_sck * j pj4 input/output siof/hac/ssi siof_sync/hac_sync/ssi_ws * j pj3 input/output siof/hac/ssi siof_mclk/ hac_res * j pj2 input/output siof/hac siof_sck/hac_bitclk/ssi_clk * j pj1 input/output siof/hac/ssi tclk/ iois16 * j pj0 input/output tmu/lbsc available dreq0 k pk7 input/output dmac dreq1 k pk6 input/output dmac dreq2 / intb /audata0 * k pk5 input/output dmac/lbsc/h-udi available dreq3 / intc /audata1 * k pk4 input/output dmac/lbsc/h-udi available dack2 / mresetout /audata2 * k pk3 input/output dmac/lbsc/h-udi dack3 / irqout /audata3 * k pk2 input/output dmac/lbsc/h-udi drak2 / ce2a * k pk1 output dmac/lbsc/h-udi drak3 / ce2b /audsync * k pk0 output dmac/lbsc/h-udi dack0 /mode0 l pl3 output dmac/? dack1 /mode1 l pl2 output dmac/? drak0 /mode2 l pl1 output dmac/? drak1 /mode7 l pl0 output dmac/? breq m pm1 input/output lbsc back m pm0 input/output lbsc irq/ irl4 /fd4/mode3 * ? ? intc/flctl/? irq/ irl5 /fd5/mode4 * ? ? intc/flctl/? irq/ irl6 /fd6/mode6 * ? ? intc/flctl/? audata0/fd0 * ? ? h-udi/flctl audata1/fd1 * ? ? h-udi/flctl audata2/fd2 * ? ? h-udi/flctl audata3/fd3 * ? ? h-udi/flctl audck/fale * ? ? h-udi/flctl audsync/ fce * ? ? h-udi/flctl
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1059 of 1286 rej09b0158-0100 pin name port gpio multiplexed module gpio interrupt status0/cmt_ctr0 * ? ? power down modes/cmt status1/cmt_ctr1 * ? ? power down modes/ cmt note: * a module that uses this pin is selected by omselr.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1060 of 1286 rej09b0158-0100 28.2 register descriptions table 28.2 shows the gpio register configuration. table 28.3 shows the register states in each processing mode. table 28.2 register configuration register name abbrev. r/w p4 address area 7 address access size * sync clock port a control register pacr r/w h'ffea 0000 h'1fea 0000 16 pck port b control register pbcr r/w h'ffea 0002 h'1fea 0002 16 pck port c control register pccr r/w h'ffea 0004 h'1fea 0004 16 pck port d control register pdcr r/w h'ffea 0006 h'1fea 0006 16 pck port e control register pecr r/w h'ffea 0008 h'1fea 0008 16 pck port f control register pfcr r/w h'ffea 000a h'1fea 000a 16 pck port g control register pgcr r/w h'ffea 000c h'1fea 000c 16 pck port h control register phcr r/w h'ffea 000e h'1fea 000e 16 pck port j control register pjcr r/w h'ffea 0010 h'1fea 0010 16 pck port k control register pkcr r/w h'ffea 0012 h'1fea 0012 16 pck port l control register plcr r/w h'ffea 0014 h'1fea 0014 16 pck port m control register pmcr r/w h'ffea 0016 h'1fea 0016 16 pck port a data register padr r/w h'ffea 0020 h'1fea 0020 8 pck port b data register pbdr r/w h'ffea 0022 h'1fea 0022 8 pck port c data register pcdr r/w h'ffea 0024 h'1fea 0024 8 pck port d data register pddr r/w h'ffea 0026 h'1fea 0026 8 pck port e data register pedr r/w h'ffea 0028 h'1fea 0028 8 pck port f data register pfdr r/w h'ffea 002a h'1fea 002a 8 pck port g data register pgdr r/w h'ffea 002c h'1fea 002c 8 pck port h data register phdr r/w h'ffea 002e h'1fea 002e 8 pck port j data register pjdr r/w h'ffea 0030 h'1fea 0030 8 pck port k data register pkdr r/w h'ffea 0032 h'1fea 0032 8 pck port l data register pldr r/w h'ffea 0034 h'1fea 0034 8 pck port m data register pmdr r/w h'ffea 0036 h'1fea 0036 8 pck port e pull-up control register pepu pr r/w h'ffea 0048 h'1fea 0048 8 pck port h pull-up control register phpupr r/w h'ffea 004e h'1fea 004e 8 pck
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1061 of 1286 rej09b0158-0100 register name abbrev. r/w p4 address area 7 address access size * sync clock port j pull-up control register pjpupr r/w h'ffea 0050 h'1fea 0050 8 pck port k pull-up control register pkpu pr r/w h'ffea 0052 h'1fea 0052 8 pck port m pull-up control register pmpupr r/w h'ffea 0056 h'1fea 0056 8 pck input pin pull-up control register 1 ppupr1 r/w h'ffea 0060 h'1fea 0060 16 pck input pin pull-up control register 2 ppupr2 r/w h'ffea 0062 h'1fea 0062 16 pck on-chip module select register omselr r/w h'ffea 0080 h'1fea 0080 16 pck note: * there are 8-bit and 16-bit registers and access registers in designate size.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1062 of 1286 rej09b0158-0100 table 28.3 register states of gp io in each processing mode register name abbrev. power-on reset by preset pin/ wdt/h-udi manual reset by wdt/ multiple exception sleep by sleep instruction port a control register pacr h'0000 retained retained port b control register pbcr h'0000 retained retained port c control register pccr h'0000 retained retained port d control register pdcr h'0000 retained retained port e control register pecr h'3000 retained retained port f control register pfcr h'0000 retained retained port g control register pgcr h'0000 retained retained port h control register phcr h'ffff retained retained port j control register pjcr h'ffff retained retained port k control register pkcr h'ffff retained retained port l control register plcr h'ffff retained retained port m control register pmcr h'ffff retained retained port a data register padr h'00 retained retained port b data register pbdr h'00 retained retained port c data register pcdr h'00 retained retained port d data register pddr h'00 retained retained port e data register pedr h'x0 retained retained port f data register pfdr h'00 retained retained port g data register pgdr h'00 retained retained port h data register phdr h'xx retained retained port j data register pjdr h'xx retained retained port k data register pkdr h'xx retained retained port l data register pldr h'00 retained retained port m data register pmdr h'0x retained retained port e pull-up control register pepupr h'ff retained retained port h pull-up control register phpupr h'ff retained retained port j pull-up control register pjpupr h'ff retained retained port k pull-up control register pkpupr h'ff retained retained port m pull-up control register pmpupr h'ff retained retained input pin pull-up control register 1 ppupr1 h'ffff retained retained input pin pull-up control register 2 ppupr2 h'ffff retained retained on-chip module select register omselr h'0000 retained retained
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1063 of 1286 rej09b0158-0100 28.2.1 port a control register (pacr) pacr is a 16-bit readable/writable register that selects the pin function. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pa0 md0 pa0 md1 pa1 md0 pa1 md1 pa2 md0 pa2 md1 pa3 md0 pa3 md1 pa4 md0 pa4 md1 pa5 md0 pa5 md1 pa6 md0 pa6 md1 pa7 md1 pa7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pa7md1 pa7md0 0 0 r/w r/w pa7 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 13 12 pa6md1 pa6md0 0 0 r/w r/w pa6 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 11 10 pa5md1 pa5md0 0 0 r/w r/w pa5 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 9 8 pa4md1 pa4md0 0 0 r/w r/w pa4 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 7 6 pa3md1 pa3md0 0 0 r/w r/w pa3 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1064 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 4 pa2md1 pa2md0 0 0 r/w r/w pa2 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 3 2 pa1md1 pa1md0 0 0 r/w r/w pa1 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 1 0 pa0md1 pa0md0 0 0 r/w r/w pa0 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 28.2.2 port b control register (pbcr) pbcr is a 16-bit readable/writable register that selects the pin function. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pb0 md0 pb0 md1 pb1 md0 pb1 md1 pb2 md0 pb2 md1 pb3 md0 pb3 md1 pb4 md0 pb4 md1 pb5 md0 pb5 md1 pb6 md0 pb6 md1 pb7 md1 pb7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pb7md1 pb7md0 0 0 r/w r/w pb7 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1065 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 12 pb6md1 pb6md0 0 0 r/w r/w pb6 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 11 10 pb5md1 pb5md0 0 0 r/w r/w pb5 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 9 8 pb4md1 pb4md0 0 0 r/w r/w pb4 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 7 6 pb3md1 pb3md0 0 0 r/w r/w pb3 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 5 4 pb2md1 pb2md0 0 0 r/w r/w pb2 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 3 2 pb1md1 pb1md0 0 0 r/w r/w pb1 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 1 0 pb0md1 pb0md0 0 0 r/w r/w pb0 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1066 of 1286 rej09b0158-0100 28.2.3 port c control register (pccr) pccr is a 16-bit readable/writable register that selects the pin function. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pc0 md0 pc0 md1 pc1 md0 pc1 md1 pc2 md0 pc2 md1 pc3 md0 pc3 md1 pc4 md0 pc4 md1 pc5 md0 pc5 md1 pc6 md0 pc6 md1 pc7 md1 pc7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pc7md1 pc7md0 0 0 r/w r/w pc7 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 13 12 pc6md1 pc6md0 0 0 r/w r/w pc6 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 11 10 pc5md1 pc5md0 0 0 r/w r/w pc5 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 9 8 pc4md1 pc4md0 0 0 r/w r/w pc4 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 7 6 pc3md1 pc3md0 0 0 r/w r/w pc3 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1067 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 4 pc2md1 pc2md0 0 0 r/w r/w pc2 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 3 2 pc1md1 pc1md0 0 0 r/w r/w pc1 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 1 0 pc0md1 pc0md0 0 0 r/w r/w pc0 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 28.2.4 port d control register (pdcr) pdcr is a 16-bit readable/writable register that selects the pin function. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pd0 md0 pd0 md1 pd1 md0 pd1 md1 pd2 md0 pd2 md1 pd3 md0 pd3 md1 pd4 md0 pd4 md1 pd5 md0 pd5 md1 pd6 md0 pd6 md1 pd7 md1 pd7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pd7md1 pd7md0 0 0 r/w r/w pd7 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1068 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 12 pd6md1 pd6md0 0 0 r/w r/w pd6 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 11 10 pd5md1 pd5md0 0 0 r/w r/w pd5 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 9 8 pd4md1 pd4md0 0 0 r/w r/w pd4 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 7 6 pd3md1 pd3md0 0 0 r/w r/w pd3 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 5 4 pd2md1 pd2md0 0 0 r/w r/w pd2 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 3 2 pd1md1 pd1md0 0 0 r/w r/w pd1 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited 1 0 pd0md1 pd0md0 0 0 r/w r/w pd0 mode 00: pcic module 01: port output 10: port input (pull-up mos: off) 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1069 of 1286 rej09b0158-0100 28.2.5 port e control register (pecr) pecr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00 pe0 md0 pe0 md1 pe1 md0 pe1 md1 pe2 md0 pe2 md1 pe3 md0 pe3 md1 pe4 md0 pe4 md1 pe5 md0 pe5 md1 pe6 md0 pe6 md1 ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 ? all 0 r/w reserved these bits are always read as 0, and the write value should always be 0. 13 12 pe6md1 pe6md0 1 1 r/w r/w pe6 mode 00: intc/flctl module (irq/ irl7 /fd7) * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 11 10 pe5md1 pe5md0 0 0 r/w r/w pe5 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on) 9 8 pe4md1 pe4md0 0 0 r/w r/w pe4 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on) 7 6 pe3md1 pe3md0 0 0 r/w r/w pe3 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1070 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5 4 pe2md1 pe2md0 0 0 r/w r/w pe2 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on) 3 2 pe1md1 pe1md0 0 0 r/w r/w pe1 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on) 1 0 pe0md1 pe0md0 0 0 r/w r/w pe0 mode 00: pcic module 01: port output 10: setting prohibited 11: port input (pull-up mos: on) note: * can be selectable the modules that use th is pin by on-chip module select register. 28.2.6 port f control register (pfcr) pfcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pf0 md0 pf0 md1 pf1 md0 pf1 md1 pf2 md0 pf2 md1 pf3 md0 pf3 md1 pf4 md0 pf4 md1 pf5 md0 pf5 md1 pf6 md0 pf6 md1 pf7 md1 pf7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pf7md1 pf7md0 0 0 r/w r/w pf7 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1071 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 6 pf6md1 pf6md0 0 0 r/w r/w pf6 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 7 6 pf5md1 pf5md0 0 0 r/w r/w pf5 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 7 6 pf4md1 pf4md0 0 0 r/w r/w pf4 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 7 6 pf3md1 pf3md0 0 0 r/w r/w pf3 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 5 4 pf2md1 pf2md0 0 0 r/w r/w pf2 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 3 2 pf1md1 pf1md0 0 0 r/w r/w pf1 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 1 0 pf0md1 pf0md0 0 0 r/w r/w pf0 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1072 of 1286 rej09b0158-0100 28.2.7 port g control register (pgcr) pgcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 pg0 md0 pg0 md1 pg1 md0 pg1 md1 pg2 md0 pg2 md1 pg3 md0 pg3 md1 pg4 md0 pg4 md1 pg5 md0 pg5 md1 pg6 md0 pg6 md1 pg7 md1 pg7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pg7md1 pg7md0 0 0 r/w r/w pg7 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 13 12 pg6md1 pg6md0 0 0 r/w r/w pg6 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 11 10 pg5md1 pg5md0 0 0 r/w r/w pg5 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 9 8 pg4md1 pg4md0 0 0 r/w r/w pg4 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1073 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 6 pg3md1 pg3md0 0 0 r/w r/w pg3 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 5 4 pg2md1 pg2md0 0 0 r/w r/w pg2 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 3 2 pg1md1 pg1md0 0 0 r/w r/w pg1 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 1 0 pg0md1 pg0md0 0 0 r/w r/w pg0 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1074 of 1286 rej09b0158-0100 28.2.8 port h control register (phcr) phcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 ph0 md0 ph0 md1 ph1 md0 ph1 md1 ph2 md0 ph2 md1 ph3 md0 ? ph4 md0 ph4 md1 ph5 md0 ph5 md1 ph6 md0 ? ph7 md1 ph7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 ph7md1 ph7md0 1 1 r/w r/w ph7 mode 00: scif1/mmcif module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 13 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 12 ph6md 1 r/w ph6 mode 0: scif1/mmcif module * 1: port output 11 10 ph5md1 ph5md0 1 1 r/w r/w ph5 mode 00: scif1/mmcif module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 9 8 ph4md1 ph4md0 1 1 r/w r/w pth4 mode 00: scif0/hspi/flctl module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 7 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1075 of 1286 rej09b0158-0100 bit bit name initial value r/w description 6 ph3md 1 r/w ph3 mode 0: scif0/hspi/flctl module * 1: port output 5 4 ph2md1 ph2md0 1 1 r/w r/w ph2 mode 00: scif0/hspi/flctl module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 3 2 ph1md1 ph1md0 1 1 r/w r/w ph1 mode 00: scif0/hspi/flctl module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 1 0 ph0md1 ph0md0 1 1 r/w r/w ph0 mode 00: scif0/hspi/flctl module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) note: * can be selectable the modules that use th is pin by on-chip module select register. 28.2.9 port j control register (pjcr) pjcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 pj0 md0 pj0 md1 pj1 md0 pj1 md1 pj2 md0 pj2 md1 pj3 md0 pj3 md1 pj4 md0 pj4 md1 pj5 md0 pj5 md1 ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1076 of 1286 rej09b0158-0100 bit bit name initial value r/w description 15 to 12 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 11 10 pj5md1 pj5md0 1 1 r/w r/w pj5 mode 00: siof/hac/ssi module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 9 8 pj4md1 pj4md0 1 1 r/w r/w pj4 mode 00: siof/hac/ssi module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 7 6 pj3md1 pj3md0 1 1 r/w r/w pj3 mode 00: siof/hac/ssi module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 5 4 pj2md1 pj2md0 1 1 r/w r/w pj2 mode 00: siof/hac module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 3 2 pj1md1 pj1md0 1 1 r/w r/w pj1 mode 00: siof/hac/ssi module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 1 0 pj0md1 pj0md0 1 1 r/w r/w pj1 mode 00: tmu0/lbsc module * 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) note: * can be selectable the modules that use th is pin by on-chip module select register.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1077 of 1286 rej09b0158-0100 28.2.10 port k control register (pkcr) pkcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 pk0 md0 ? pk1 md0 ? pk2 md0 pk2 md1 pk3 md0 pk3 md1 pk4 md0 pk4 md1 pk5 md0 pk5 md1 pk6 md0 pk6 md1 pk7 md1 pk7 md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 14 pk7md1 pk7md0 1 1 r/w r/w pk7 mode 00: dmac module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 13 12 pk6md1 pk6md0 1 1 r/w r/w pk6 mode 00: dmac module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 11 10 pk5md1 pk5md0 1 1 r/w r/w pk5 mode 00: dmac/pcic/h-udi module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 9 8 pk4md1 pk4md0 1 1 r/w r/w pk4 mode 00: dmac/pcic/h-udi module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1078 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 6 pk3md1 pk3md0 1 1 r/w r/w pk3 mode 00: dmac/reset/h-udi module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 5 4 pk2md1 pk2md0 1 1 r/w r/w pk2 mode 00: dmac/intc/h-udi module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 3 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 2 pk1md0 1 r/w pk1 mode 0: dmac/lbsc/h-udi module 1: port output 1 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 0 pk0md 1 r/w pk0 mode 0: dmac/lbsc/h-udi module 1: port output note: can be selectable the modules that use this pin by on-chip module select register.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1079 of 1286 rej09b0158-0100 28.2.11 port l control register (plcr) plcr is a 16-bit readable/writable register that selects the pin function. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 pl0 md0 ? pl1 md0 ? pl2 md0 ? pl3 md0 ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 to 7 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 6 pl3md 1 r/w pl3 mode 0: dmac module 1: port output 5 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 4 pl2md 1 r/w pl2 mode 0: dmac module 1: port output 3 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 2 pl1md 1 r/w pk1 mode 0: dmac module 1: port output 1 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 0 pl0md 1 r/w pl0 mode 0: dmac module 1: port output
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1080 of 1286 rej09b0158-0100 28.2.12 port m control register (pmcr) pmcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 pl0 md0 pl0 md1 pl1 md0 pl1 md1 ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 to 4 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 3 2 pm1md1 pm1md0 1 1 r/w r/w pm1 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on) 1 0 pm0md1 pm0md0 1 1 r/w r/w pm1 mode 00: lbsc module 01: port output 10: port input (pull-up mos: off) 11: port input (pull-up mos: on)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1081 of 1286 rej09b0158-0100 28.2.13 port a data register (padr) padr is an 8-bit readable/writable register that stores port a data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pa0dt pa1dt pa2dt pa3dt pa4dt pa5dt pa6dt pa7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pa7dt 0 r/w 6 pa6dt 0 r/w 5 pa5dt 0 r/w 4 pa4dt 0 r/w 3 pa3dt 0 r/w 2 pa2dt 0 r/w 1 pa1dt 0 r/w 0 pa0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out. 28.2.14 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores port b data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pb0dt pb1dt pb2dt pb3dt pb4dt pb5dt pb6dt pb7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pb7dt 0 r/w 6 pb6dt 0 r/w 5 pb5dt 0 r/w 4 pb4dt 0 r/w 3 pb3dt 0 r/w 2 pb2dt 0 r/w 1 pb1dt 0 r/w 0 pb0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1082 of 1286 rej09b0158-0100 28.2.15 port c data register (pcdr) pcdr is an 8-bit readable/writable register that stores port c data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pc0dt pc1dt pc2dt pc3dt pc4dt pc5dt pc6dt pc7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pc7dt 0 r/w 6 pc6dt 0 r/w 5 pc5dt 0 r/w 4 pc4dt 0 r/w 3 pc3dt 0 r/w 2 pc2dt 0 r/w 1 pc1dt 0 r/w 0 pc0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out. 28.2.16 port d data register (pddr) pddr is an 8-bit readable/writable register that stores port d data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pd0dt pd1dt pd2dt pd3dt pd4dt pd5dt pd6dt pd7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pd7dt 0 r/w 6 pd6dt 0 r/w 5 pd5dt 0 r/w 4 pd4dt 0 r/w 3 pd3dt 0 r/w 2 pd2dt 0 r/w 1 pd1dt 0 r/w 0 pd0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1083 of 1286 rej09b0158-0100 28.2.17 port e data register (pedr) pedr is an 8-bit readable/writable register that stores port e data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 pe0dt pe1dt pe2dt pe3dt pe4dt pe5dt pe6dt ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 ? 0 r/w reserved this bit is always read as 0, and the write value should always be 0. 6 pe6dt pin input r/w 5 pe5dt 0 r/w 4 pe4dt 0 r/w 3 pe3dt 0 r/w 2 pe2dt 0 r/w 1 pe1dt 0 r/w 0 pe0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1084 of 1286 rej09b0158-0100 28.2.18 port f data register (pfdr) pfdr is an 8-bit readable/writable register that stores port f data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pf0dt pf1dt pf2dt pf3dt pf4dt pf5dt pf6dt pf7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pf7dt 0 r/w 6 pf6dt 0 r/w 5 pf5dt 0 r/w 4 pf4dt 0 r/w 3 pf3dt 0 r/w 2 pf2dt 0 r/w 1 pf1dt 0 r/w 0 pf0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out. 28.2.19 port g data register (pgdr) pgdr is an 8-bit readable/writable register that stores port g data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pg0dt pg1dt pg2dt pg3dt pg4dt pg5dt pg6dt pg7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pg7dt 0 r/w 6 pg6dt 0 r/w 5 pg5dt 0 r/w 4 pg4dt 0 r/w 3 pg3dt 0 r/w 2 pg2dt 0 r/w 1 pg1dt 0 r/w 0 pg0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1085 of 1286 rej09b0158-0100 28.2.20 port h data register (phdr) phdr is an 8-bit readable/writable register that stores port h data. 0 1 2 3 4 5 6 7 0 0 ph0dt ph1dt ph2dt ph3dt ph4dt ph5dt ph6dt ph7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: ?????? bit bit name initial value r/w description 7 ph7dt pin input r/w 6 ph6dt 0 r/w 5 ph5dt pin input r/w 4 ph4dt pin input r/w 3 ph3dt 0 r/w 2 ph2dt pin input r/w 1 ph1dt pin input r/w 0 ph0dt pin input r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out. however, bit 6 and 3 are exclusively used as output ports. 28.2.21 port j data register (pjdr) pjdr is an 8-bit readable/writable register that stor es port j data. 0 1 2 3 4 5 6 7 0 0 pj0dt pj1dt pj2dt pj3dt pj4dt pj5dt ? ? ? ?? ?? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved these bits are always read as 0, and the write value should always be 0. 5 pj5dt pin input r/w 4 pj4dt pin input r/w 3 pj3dt pin input r/w 2 pj2dt pin input r/w 1 pj1dt pin input r/w 0 pj0dt pin input r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. when the pin functions as a general input po rt, if the port is read, the status of the corresponding pin will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1086 of 1286 rej09b0158-0100 28.2.22 port k data register (pkdr) pkdr is an 8-bit readable/writable register that stores port k data. 0 1 2 3 4 5 6 7 0 0 pk0dt pk1dt pk2dt pk3dt pk4dt pk5dt pk6dt pk7dt r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: ? ?? ?? ? bit bit name initial value r/w description 7 pk7dt pin input r/w 6 pk6dt pin input r/w 5 pk5dt pin input r/w 4 pk4dt pin input r/w 3 pk3dt pin input r/w 2 pk2dt pin input r/w 1 pk1dt 0 r/w 0 pk0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the corresponding value of this register will be read out. when the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out. however, bit 0 is exclusively used as an output port. 28.2.23 port l data register (pldr) pldr is an 8-bit readable/writable register that stores port l data. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 pl0dt pl1dt pl2dt pl3dt ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 to 4 ? all 0 r/w reserved these bits are always read as 0, and the write value should always be 0. 3 pl3dt 0 r/w 2 pl2dt 0 r/w 1 pl1dt 0 r/w 0 pl0dt 0 r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the corresponding value of this register will be read out.
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1087 of 1286 rej09b0158-0100 28.2.24 port m data register (pmdr) pmdr is an 8-bit readable/writable register that stores port m data. 0 1 2 3 4 5 6 7 x x 0 0 0 0 0 0 pm0dt pm1dt ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 to 2 ? all 0 r/w reserved these bits are always read as 0, and the write value should always be 0. 1 pm1dt pin input r/w 0 pm0dt pin input r/w these bits store output data of a pin which is used as a general output port. when the pin functions as a general output port, if the port is read, the corresponding value of this register will be read out. when the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out. 28.2.25 port e pull-up control register (pepupr) pepupr is an 8-bit readable/writable register that individually controls the pull-up for this port. bit 6 of this register corresponds to port e6 (pe6 ), and when the pin is set to the on-chip module, the pull-up control is performed. however, if the pin is set to the gpio in the pecr, the setting for this register is invalid. 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 ? ? ? ? ? ? pe6 pupr ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w:
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1088 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 ? 1 r/w reserved this bit is always read as 1, and the write value should always be 1. 6 pe6pupr 1 r/w pull-up control of the pin of port e can be set. 0: pe6 pull-up off 1: pe6 pull-up on 5 to 0 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 28.2.26 port h pull-up control register (phpupr) phpupr is an 8-bit readable/writable register that individually controls the pull-up for this port. each bit of this register corresponds to port h (ph7 to ph0), and when these pins are set to the on- chip modules, the pull-up control is performed individually. however, if these pins are set to the gpio in the phcr, the setting in this register is invalid. 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 ph0 pupr ph1 pupr ph2 pupr ph3 pupr ph4 pupr ph5 pupr ph6 pupr ph7 pupr r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 ph7pupr 1 r/w 6 ph6pupr 1 r/w 5 ph5pupr 1 r/w 4 ph4pupr 1 r/w 3 ph3pupr 1 r/w 2 ph2pupr 1 r/w 1 ph1pupr 1 r/w 0 ph0pupr 1 r/w pull-up control of the pins of port h can be set individually. 0: phn pull-up off 1: phn pull-up on note: n = 7 to 0
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1089 of 1286 rej09b0158-0100 28.2.27 port j pull-up control register (pjpupr) pjpupr is an 8-bit readable/writable register that individually controls the pull-up for this port. each bit of this register corresp onds to port j (pj5 to pj0), and when these pins are set to the on- chip modules, the pull-up control is performed individually. however, if these pins are set to the gpio in the pjcr, the setting in this register is invalid. 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 pj0 pupr pj1 pupr pj2 pupr pj3 pupr pj4 pupr pj5 pupr ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7, 6 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 5 pj5pupr 1 r/w 4 pj4pupr 1 r/w 3 pj3pupr 1 r/w 2 pj2pupr 1 r/w 1 pj1pupr 1 r/w 0 pj0pupr 1 r/w pull-up control of the pins of port j can be set individually. 0: pjn pull-up off 1: pjn pull-up on note: n = 5 to 0
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1090 of 1286 rej09b0158-0100 28.2.28 port k pull-up control register (pkpupr) pkpupr is an 8-bit readable/writable register that individually controls the pull-up for this port. each bit of this register corresponds to port k (pk7 to pk0), and when these pins are set to the on- chip modules, the pull-up control is performed individually. however, if these pins are set to the gpio in the pkcr, the setting in this register is invalid. 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 pk0 pupr pk1 pupr pk2 pupr pk3 pupr pk4 pupr pk5 pupr pk6 pupr pk7 pupr r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 pk7pupr 1 r/w 6 pk6pupr 1 r/w 5 pk5pupr 1 r/w 4 pk4pupr 1 r/w 3 pk3pupr 1 r/w 2 pk2pupr 1 r/w 1 pk1pupr 1 r/w 0 pk0pupr 1 r/w pull-up control of the pins of port k can be set individually. 0: pkn pull-up off 1: pkn pull-up on note: n = 7 to 0
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1091 of 1286 rej09b0158-0100 28.2.29 port m pull-up control register (pmpupr) pmpupr is an 8-bit readable/writable register that individually controls the pull-up for this port. each bit of this register corres ponds to port m (pm7 to pm0), and when these pins are set to the on-chip modules, the pull-up control is performed individually. however, if these pins are set to the gpio in the pmcr, the setting in this register is invalid. 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 pm0 pupr pm1 pupr ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 7 to 2 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 1 pm1pupr 1 r/w 0 pm0pupr 1 r/w pull-up control of the pins of port m can be set individually. 0: pmn pull-up off 1: pmn pull-up on note: n = 1 to 0
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1092 of 1286 rej09b0158-0100 28.2.30 input-pin pull-up control register 1 (ppupr1) ppupr1 is a 16-bit readable/writable register that individually controls the pull-up for the pin corresponding to each bit of the register field. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 ctr0 pup ctr1 pup rdy pup ? ? ? ? ? ? ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 to 3 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 2 rdypup 1 r/w controls pull-up of rdy 0: rdy pull-up off 1: rdy pull-up on 1 ctr1pup 1 r/w controls pull-up of cmt_ctr1 0: cmt_ctr1 pull-up off 1: cmt_ctr1 pull-up on 0 ctr0pup 1 r/w controls pull-up of cmt_ctr0 0: cmt_ctr1 pull-up off 1: cmt_ctr1 pull-up on
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1093 of 1286 rej09b0158-0100 28.2.31 input-pin pull-up control register 2 (ppupr2) ppupr2 is a 16-bit readable/writable register that individually controls the pull-up for the pin corresponding to each bit of the register field. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 irl2 pup irl3 pup irl0 pup irl1 pup fd1 pup fd3 pup fd2 pup nmi pup fd0 pup ? ? ? ? ? ?? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 to 12 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 11 fd3pup 1 r/w controls pull-up of fd3 0: fd3 pull-up off 1: fd3 pull-up on 10 fd2pup 1 r/w controls pull-up of fd2 0: fd2 pull-up off 1: fd2 pull-up on 9 fd1pup 1 r/w controls pull-up of fd1 0: fd1 pull-up off 1: fd1 pull-up on 8 fd0pup 1 r/w controls pull-up of fd0 0: fd0 pull-up off 1: fd0 pull-up on 7 nmipup 1 r/w controls pull-up of nmi 0: nmi pull-up off 1: nmi pull-up on 6 to 4 ? all 1 r/w reserved these bits are always read as 1, and the write value should always be 1. 3 irl3pup 1 r/w controls pull-up of irq/ irl3 0: irq/ irl3 pull-up off 1: irq/ irl3 pull-up on
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1094 of 1286 rej09b0158-0100 bit bit name initial value r/w description 2 irl2pup 1 r/w controls pull-up of irq/ irl2 0: irq/ irl2 pull-up off 1: irq/ irl2 pull-up on 1 irl1pup 1 r/w controls pull-up of irq/ irl1 0: irq/ irl1 pull-up off 1: irl1 pull-up on 0 irl0pup 1 r/w controls pull-up of irq/ irl0 0: irq/ irl0 pull-up off 1: irq/ irl0 pull-up on 28.2.32 on-chip module select register (omselr) omselr is a 16-bit readable/writable register. mo dules using pins multiplexed are specified by this register. for details of pin multiplexing, see table 28.1, multiplexed pins controlled by port control registers. this register is valid only when on-chip modul es are selected by pecr (pe6), phcr, pjcr, or pkcr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 omsel 0 omsel 1 omsel 2 omsel 3 omsel 4 omsel 5 omsel 6 ? omsel 8 omsel 9 omsel 10 omsel 11 omsel 12 omsel 13 ? omsel 14 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: r/w: bit bit name initial value r/w description 15 ? 0 r/w reserved this bit is always read as 0, and the write value should always be 0. 14 omsel14 0 r/w out of the modules reset (status) and cmt, select the one using the pins status0/cmt_ctr0 and status1/cmt_ctr1. 0: selects reset (status) 1: selects cmt
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1095 of 1286 rej09b0158-0100 bit bit name initial value r/w description 13 omsel13 0 r/w out of the modules scif1 and mmcif, select the one using the pins scif1_sck/mccmd, scif1_txd/mcclk, an d scif1_rxd/mcdat. 0: selects scif1 1: selects mmcif 12 omsel12 0 r/w out of the modules h-udi, intc, and flctl, select the one using the pins audata[3:0]/fd[3:0], audck/fale, audsync/ fce , irq/ irl4 /fd4, irq/ irl5 /fd5, irq/ irl6 /fd6, and irq/ irl7 /fd7. 0: h-udi, intc 1: flctl 11 10 omsel11 omsel10 0 0 r/w r/w out of the modules scif0, hspi, pcic, and flctl, select the one using the pins scif0_sck/hspi_clk/ fre , scif0_txd/hspi_tx/ fwe /mode8, scif0_rxd/hspi_rx/frb, scif0_cts / intd /fcle, and scif0_rts / hspi_ce / fse 00: scif0 01: hspi, pcic 10: flctl 11: scif0 * , pcic note: * cannot use modem control pin scif0_cts (this pin is used by pcic), and scif0_rts pin should be pulled-up by phpupr ph0 bit. 9 8 omsel9 omsel8 0 0 r/w r/w out of the modules siof, hac, and ssi, select the one using the pins siof_txd/hac_sdout/ssi_sdata, siof_rxd/hac_sdin/ssi_sck, siof_sync/hac_sync/ssi_ws, siof_mclk/ hac_res , and siof_sck/hac_bitclk/ssi_clk 00: siof 01: hac 10: ssi 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1096 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7 ? 0 r/w reserved this bit is always read as 0, and the write value should always be 0. 6 omsel6 0 r/w out of the modules tmu and lbsc, select the one using the pin tclk/ iois16 . 0: tmu 1: lbsc 5 4 omsel5 omsel4 0 0 r/w r/w out of the modules dmac, pcic, and h-udi, select the one using the pins dreq3 / intc /audata1, and dreq2 / intb /audata0 00: dmac 01: pcic 10: h-udi 11: setting prohibited 3 2 omsel3 omsel2 0 0 r/w r/w out of the modules dmac, intc, reset, and h-udi, select the one using the pins dack3 / irqout /audata3 and dack2 / mresetout /audata2 00: dmac 01: intc, reset 10: h-udi 11: setting prohibited 1 0 omsel1 omsel0 1 1 r/w r/w out of the modules dmac, lbsc, and h-udi, select the one using the pins drak3 / ce2b /audsync and drak2 / ce2a /audck 00: dmac 01: lbsc 10: h-udi 11: setting prohibited
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1097 of 1286 rej09b0158-0100 28.3 usage example 28.3.1 port output function to use the gpio as an output port, set the corresponding port control register. to output the data of port data register (padr to pmdr) from the gpio output port, write b'01 to the corresponding two bits in port control register (pacr to pmcr). then for each output port, the settings of port pull-up control register (pepupr, phpupr, pjpupr, pkpupr and pmpupr) and on-chip module select register (omselr) are invalid. figure 28.1 shows an example of port data output timing. setting the output data to port data register and then the port outputs the data after one peripheral clock (pck). output data set output data clkout port a data register pck pa7 to pa0 output data figure 28.1 port data output timing (example of port a)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1098 of 1286 rej09b0158-0100 28.3.2 port input function to use the gpio as an input port, set the corresponding port control register. to input the data from the gpio port, write b'10 or b'11 to the corresponding two bits in port control register (pacr to pkcr and pmcr). then the pull-up mos is off by b'10 and on by b'11. the input data to each port can be read out from the corresponding bit in port data register. then for each input port, the settings of port pull-up control register (pepupr, phpupr, pjpupr, pkpupr and pmpupr) and on-chip module select register (omselr) are invalid. figure 28.2 shows an example of port data input timing. the input data from each port can be read out from corresponding port data register after the 2nd rising edge of the peripheral clock (pck). data input clkout port a data register pck pa7 to pa0 input data input data figure 28.2 port data input timing (example of port a)
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1099 of 1286 rej09b0158-0100 28.3.3 on-chip module function to use the peripheral modules, first select the on-chip module by setting corresponding bit in on- chip module select register (omselr). when the corresponding port is input or input/output port, it is necessary for each port to set the pull-up mos by setting port pull-up control register (pepupr, phpupr, pjpupr, pkpupr and pmpupr). write b'0 when pull-up mos is off or b'1 when pull-up mos is on to the corresponding bit. for an output port, the pull-up mos is off regardless of the settings of the port pull-up control register. after that write b'00 to the corresponding two bits in port control register (pacr to pmcr).
section 28 general purpose i/o (gpio) rev.1.00 dec. 13, 2005 page 1100 of 1286 rej09b0158-0100
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1101 of 1286 rej09b0158-0100 section 29 user break controller (ubc) the user break controller (ubc) provides versatile functions to facilitate program debugging. these functions help to ease creation of a se lf-monitor/debugger, which allows easy program debugging using this lsi alone, without using the in-circuit emulator. various break conditions can be set in the ubc: instruction fetch or re ad/write access of an operand, operand size, data contents, address value, and program stop timing for instruction fetch. 29.1 features 1. the following break conditions can be set. break channels: two (channels 0 and 1) user break conditions can be set independently for channels 0 and 1, and can also be set as a single sequential condition for the two channels, that is, a sequential break. (sequential break involves two cases such that th e channel 0 break condition is sa tisfied in a certain bus cycle and then the channel 1 break condition is satisfi ed in a different bus cycle, and vice versa.) ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1102 of 1286 rej09b0158-0100 figure 29.1 shows the ubc block diagram. sab internal bus access comparator address comparator channel 0 operation control channel 1 operation control access comparator address comparator data comparator control cbr0 car0 camr0 crr0 cbr1 car1 camr1 cdr1 cdmr1 cetr1 crr1 ccmfr cbcr user break is requested. sdb access control cbr0: crr0: car0: camr0: cbr1: crr1: car1: camr1: cdr1: cdmr1: cetr1: ccmfr: cbcr: sab: sdb: [legend] asid comparator asid comparator asid match condition setting register 0 match operation setting register 0 match address setting register 0 match address mask setting register 0 match condition setting register 1 match operation setting register 1 match address setting register 1 match address mask setting register 1 match data setting register 1 match data mask setting register 1 execution count break register channel match flag register break control register operand address bus operand data bus figure 29.1 block diagram of ubc
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1103 of 1286 rej09b0158-0100 29.2 register descriptions the ubc has the following registers. table 29.1 register configuration name abbreviation r/w p4 address * area 7 address * access size match condition setting register 0 cbr0 r/w h'ff200000 h'1f200000 32 match operation setting register 0 crr0 r/w h'ff20000 4 h'1f200004 32 match address setting register 0 car0 r/w h'ff200008 h'1f200008 32 match address mask setting register 0 camr0 r/w h'ff20000c h'1f20000c 32 match condition setting register 1 cbr1 r/w h'ff200020 h'1f200020 32 match operation setting register 1 crr1 r/w h'ff20002 4 h'1f200024 32 match address setting register 1 car1 r/w h'ff200028 h'1f200028 32 match address mask setting register 1 camr1 r/w h'ff20002c h'1f20002c 32 match data setting register 1 cdr1 r/w h'ff 200030 h'1f200030 32 match data mask setting register 1 cdmr1 r/w h'ff200034 h'1f200034 32 execution count break register 1 cetr1 r/w h'ff200038 h'1f200038 32 channel match flag register ccmfr r/w h'ff200600 h'1f200600 32 break control register cb cr r/w h'ff200620 h'1f200620 32 note: * p4 addresses are used when area p4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the tlb.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1104 of 1286 rej09b0158-0100 table 29.2 register status in each processing state register name abbreviation power-on reset manual reset sleep match condition setting register 0 cbr0 h'20000000 retained retained match operation setting register 0 crr0 h'00002000 retained retained match address setting register 0 car0 undefined retained retained match address mask setting register 0 camr0 undefined retained retained match condition setting register 1 cbr1 h'20000000 retained retained match operation setting register 1 crr1 h'00002000 retained retained match address setting register 1 car1 undefined retained retained match address mask setting register 1 camr1 undefined retained retained match data setting register 1 cdr1 undefined retained retained match data mask setting register 1 cdmr1 undefined retained retained execution count break register 1 cetr1 undefined retained retained channel match flag register ccmfr h'00000000 retained retained break control register cb cr h'00000000 retained retained the access size must be the same as the control regist er size. if the size is different, the register is not written to if attempted, and reading the regist er returns the undefined value. a desired break may not occur between the time when the instructio n for rewriting the contro l register is executed and the time when the written value is actually reflect ed on the register. in order to confirm the exact timing when the control register is update d, read the data which has been written most recently. the subsequent instructions are valid fo r the most recently written register value.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1105 of 1286 rej09b0158-0100 29.2.1 match condition setting registers 0 and 1 (cbr0 and cbr1) cbr0 and cbr1 are readable/writable 32-bit regi sters which specify the break conditions for channels 0 and 1, respectively. the following break conditions can be set in the cbr0 and cbr1: (1) whether or not to include the match flag in the conditions, (2) whether or not to include the asid, and the asid value when included, (3) wh ether or not to include the data value, (4) operand size, (5) whether or not to include the ex ecution count, (6) bus type, (7) instruction fetch cycle or operand access cycle, and (8 ) read or write access cycle. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0010000000000000 mfe aie mfi aiv sz cd id rw ce r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r r/w r/w r/w r r r r r/w r/w r/w r/w r r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 mfe 0 r/w match flag enable specifies whether or not to include the match flag value specified by the mfi bit of this register in the match conditions. when the specified match flag value is 1, the condition is determined to be satisfied. 0: the match flag is not incl uded in the match conditions; thus, not checked. 1: the match flag is included in the match conditions. 30 aie 0 r/w asid enable specifies whether or not to include the asid specified by the aiv bit of this register in the match conditions. 0: the asid is not included in the match conditions; thus, not checked. 1: the asid is included in the match conditions.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1106 of 1286 rej09b0158-0100 bit bit name initial value r/w description 29 to 24 mfi 100000 r/w match flag specify specifies the match flag to be included in the match conditions. 000000: mf0 bit of the ccmfr register 000001: mf1 bit of the ccmfr register others: reserved (setting prohibited) note: the initial value is the reserved value, but when 1 is written into cbr0[0], mfi must be set to 000000 or 000001. and note that the channel 0 is not hit when mfe bit of this register is 1 and mfi bits are 000000 in the condition of ccrmf.mf0 = 0. 23 to 16 aiv all 0 r/w asid specify specifies the asid value to be included in the match conditions. 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 to 12 sz all 0 r/w operand size select specifies the operand size to be included in the match conditions. this bit is valid only when the operand access cycle is specified as a match condition. 000: the operand size is not included in the match conditions; thus, not checked (any operand size specifies the match condition). * 1 001: byte access 010: word access 011: longword access 100: quadword access * 2 others: reserved (setting prohibited) 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1107 of 1286 rej09b0158-0100 bit bit name initial value r/w description 7, 6 cd all 0 r/w bus select specifies the bus to be included in the match conditions. this bit is valid only when the operand access cycle is specified as a match condition. 00: operand bus for operand access others: reserved (setting prohibited) 5, 4 id all 0 r/w instructi on fetch/operand access select specifies the instruction fe tch cycle or operand access cycle as the match condition. 00: instruction fetch cycl e or operand access cycle 01: instruction fetch cycle 10: operand access cycle 11: instruction fetch cycl e or operand access cycle 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 , 1 rw all 0 r/w bus command select specifies the read/write cycle as the match condition. this bit is valid only when the operand access cycle is specified as a match condition. 00: read cycle or write cycle 01: read cycle 10: write cycle 11: read cycle or write cycle 0 ce 0 r/w channel enable validates/invalidates the channel. if this bit is 0, all the other bits of this register are invalid. 0: invalidates the channel. 1: validates the channel. notes: 1. if the data value is included in the match conditions, be sure to specify the operand size. 2. if the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and the match data mask setting register.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1108 of 1286 rej09b0158-0100 ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0010000000000000 mfe aie mfi aiv dbe sz etbe cd id rw ce r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 mfe 0 r/w match flag enable specifies whether or not to include the match flag value specified by the mfi bit of this register in the match conditions. when the specified match flag value is 1, the condition is determined to be satisfied. 0: the match flag is not included in the match conditions; thus, not checked. 1: the match flag is included in the match conditions. 30 aie 0 r/w asid enable specifies whether or not to include the asid specified by the aiv bit of this register in the match conditions. 0: the asid is not included in the match conditions; thus, not checked. 1: the asid is included in the match conditions. 29 to 24 mfi 100000 r/w match flag specify specifies the match flag to be included in the match conditions. 000000: the mf0 bit of the ccmfr register 000001: the mf1 bit of the ccmfr register others: reserved (setting prohibited) note: the initial value is the reserved value, but when 1 is written into cbr1[0], mfi must be set to 000000 or 000001. and note t hat the channel 1 is not hit when mfe bit of this register is 1 and mfi bits are 000001 in the condition of ccrmf.mf1 = 0. 23 to 16 aiv all 0 r/w asid specify specifies the asid value to be included in the match conditions.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1109 of 1286 rej09b0158-0100 bit bit name initial value r/w description 15 dbe 0 r/w data value enable * 3 specifies whether or not to include the data value in the match condition. this bit is valid only when the operand access cycle is specified as a match condition. 0: the data value is not included in the match conditions; thus, not checked. 1: the data value is included in the match conditions. 14 to 12 sz all 0 r/w operand size select specifies the operand size to be included in the match conditions. this bit is valid only when the operand access cycle is specified as a match condition. 000: the operand size is not included in the match condition; thus, not checked (any operand size specifies the match condition). * 1 001: byte access 010: word access 011: longword access 100: quadword access * 2 others: reserved (setting prohibited) 11 etbe 0 r/w execution count value enable specifies whether or not to include the execution count value in the match conditions. if this bit is 1 and the match condition satisfaction count matches the value specified by the cetr1 regi ster, the operation specified by the crr1 register is performed. 0: the execution count value is not included in the match conditions; thus, not checked. 1: the execution count value is included in the match conditions. 10 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7, 6 cd all 0 r/w bus select specifies the bus to be included in the match conditions. this bit is valid only when the operand access cycle is specified as a match condition. 00: operand bus for operand access others: reserved (setting prohibited)
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1110 of 1286 rej09b0158-0100 bit bit name initial value r/w description 5, 4 id all 0 r/w instructi on fetch/operand access select specifies the instruction fe tch cycle or operand access cycle as the match condition. 00: instruction fetch cycl e or operand access cycle 01: instruction fetch cycle 10: operand access cycle 11: instruction fetch cycl e or operand access cycle 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2, 1 rw all 0 r/w bus command select specifies the read/write cycle as the match condition. this bit is valid only when the operand access cycle is specified as a match condition. 00: read cycle or write cycle 01: read cycle 10: write cycle 11: read cycle or write cycle 0 ce 0 r/w channel enable validates/invalidates the channel. if this bit is 0, all the other bits in this register are invalid. 0: invalidates the channel. 1: validates the channel. notes: 1. if the data value is included in the match conditions, be sure to specify the operand size. 2. if the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and the match data mask setting register. 3. the ocbi instruction is handled as longw ord write access without the data value, and the pref, ocbp, and ocbwb instructions are handled as longword read access without the data value. theref ore, do not include the data va lue in the match conditions for these instructions.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1111 of 1286 rej09b0158-0100 29.2.2 match operation setting registers 0 and 1 (crr0 and crr1) crr0 and crr1 are readable/writable 32-bit regist ers which specify the operation to be executed when channels 0 and 1 satisfy the match condition, respectively. the following operations can be set in the crr0 and crr1 registers: (1) breaking at a desired timing for the instruction fetch cycle and (2) requesting a break. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 pcb bie rrrrrrrrrrrrrrr r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0010000000000000 rrrrrrrrrrrrrrr/wr/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 12 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 pcb 0 r/w pc break select specifies either before or a fter instruction execution as the break timing for the instru ction fetch cycle. this bit is invalid for breaks other than the ones for the instruction fetch cycle. 0: sets the pc break before instruction execution. 1: sets the pc break after instruction execution. 0 bie 0 r/w break enable specifies whether or not to request a break when the match condition is satisfied for the channel. 0: does not request a break. 1: requests a break.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1112 of 1286 rej09b0158-0100 ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 pcb bie rrrrrrrrrrrrrrr r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0010000000000000 rrrrrrrrrrrrrrr/wr/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 12 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 pcb 0 r/w pc break select specifies either before or a fter instruction execution as the break timing for the instru ction fetch cycle. this bit is invalid for breaks other than ones for the instruction fetch cycle. 0: sets the pc break before instruction execution. 1: sets the pc break after instruction execution. 0 bie 0 r/w break enable specifies whether or not to request a break when the match condition is satisfied for the channel. 0: does not request a break. 1: requests a break.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1113 of 1286 rej09b0158-0100 29.2.3 match address setting registers 0 and 1 (car0 and car1) car0 and car1 are readable/writable 32-bit registers specifying the virtual address to be included in the break conditions for channels 0 and 1, respectively. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ca ca r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 0 ca undefined r/w compare address specifies the address to be included in the break conditions. when the operand bus has been specified using the cbr0 register, specify the sab address in ca[31:0]. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ca ca r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 0 ca undefined r/w compare address specifies the address to be included in the break conditions. when the operand bus has been specified using the cbr1 register, specify the sab address in ca[31:0].
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1114 of 1286 rej09b0158-0100 29.2.4 match address mask setting registers 0 and 1 (camr0 and camr1) cmar0 and cmar1 are readable/writable 32-bit registers which specify the bits to be masked among the address bits sp ecified by using the match address setting register of the corresponding channel. (set the bits to be masked to 1.) ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cam cam r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 0 cam undefined r/w compare address mask specifies the bits to be masked among the address bits which are specified usin g the car0 register. (set the bits to be masked to 1.) 0: address bits ca[n] are included in the break condition. 1: address bits ca[n] are masked and not included in the break condition. [n] = any values from 31 to 0 ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cam cam r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w:
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1115 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 0 cam undefined r/w compare address mask specifies the bits to be masked among the address bits which are specified usin g the car1 register. (set the bits to be masked to 1.) 0: address bits ca[n] are included in the break condition. 1: address bits ca[n] are masked and not included in the break condition. [n] = any values from 31 to 0 29.2.5 match data setting register 1 (cdr1) cdr1 is a readable/writable 32-bit register which specifies the data value to be included in the break conditions for channel 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cd cd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 0 cd undefined r/w compare data value specifies the data value to be included in the break conditions. when the operand bus has been specified using the cbr1 register, specify the sdb data value in cd[31:0].
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1116 of 1286 rej09b0158-0100 table 29.3 settings for match data setting register bus and size selected using cbr1 cd[31:24] cd[23:16] cd[15:8] cd[7:0] operand bus (byte) don't care don' t care don't care sdb7 to sdb0 operand bus (word) don't care don't care sdb15 to sdb8 sdb7 to sdb0 operand bus (longword) sdb31 to sdb24 sdb23 to sdb16 sdb15 to sdb8 sdb7 to sdb0 notes: 1. if the data value is included in the match conditions, be sure to specify the operand size. 2. the ocbi instruction is handled as longw ord write access without the data value, and the pref, ocbp, and ocbwb instructions are handled as longword read access without the data value. theref ore, do not include the data va lue in the match conditions for these instructions. 3. if the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting regist er and match data mask setting register. 29.2.6 match data mask setting register 1 (cdmr1) cdmr1 is a readable/writable 32-bit register whic h specifies the bits to be masked among the data value bits specified using the match data setting register. (set the bits to be masked to 1.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cdm cdm r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 0 cdm undefined r/w compare data value mask specifies the bits to be masked among the data value bits specified using the cdr1 register. (set the bits to be masked to 1.) 0: data value bits cd[n] are included in the break condition. 1: data value bits cd[n] are masked and not included in the break condition. [n] = any values from 31 to 0
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1117 of 1286 rej09b0158-0100 29.2.7 execution count break register 1 (cetr1) cetr1 is a readable/writable 32-bit register which specifies the numb er of the channel hits before a break occurs. a maximum value of 2 12 ? 1 can be specified. when the execution count value is included in the match conditions by using the match condition setting register, the value of this register is decremented by one every time the cha nnel is hit. when the channel is hit after the register value reaches h'001, a break occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 cet rrrrrrrrrrrrrrr r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 cet undefined r/w execution count specifies the execution count to be included in the break conditions.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1118 of 1286 rej09b0158-0100 29.2.8 channel match flag register (ccmfr) ccmfr is a readable/writable 32-bit register whic h indicates whether or not the match conditions have been satisfied for each channel. when a channel match condition has been satisfied, the corresponding flag bit is set to 1. to clear the flags, write the da ta containing value 0 for the bits to be cleared and value 1 for the other bits to this register. (the logical and between the value which has been written and the current register value is actually written to the register.) sequential operation using multiple channels is available by using these match flags. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 mf1 mf0 rrrrrrrrrrrrrrr r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrr/wr/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 mf1 0 r/w channel 1 condition match flag this flag is set to 1 when the channel 1 match condition has been satisfied. to clear the flag, write 0 to this bit. 0: channel 1 match condition has not been satisfied. 1: channel 1 match condition has been satisfied. 0 mf0 0 r/w channel 0 condition match flag this flag is set to 1 when the channel 0 match condition has been satisfied. to clear the flag, write 0 to this bit. 0: channel 0 match condition has not been satisfied. 1: channel 0 match condition has been satisfied.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1119 of 1286 rej09b0158-0100 29.2.9 break control register (cbcr) cbcr is a readable/writable 32-bit register which specifies whether or not to use the user break debugging support function. for details on the user break debugging support function, refer to section 29.4, user break debugging support function. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 ubde rrrrrrrrrrrrrrr r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 rrrrrrrrrrrrrrrr/w bit : initial value : r/w: bit : initial value : r/w: bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 ubde 0 r/w user break debugging support function enable specifies whether or not to use the user break debugging support function. 0: does not use the user break debugging support function. 1: uses the user break d ebugging support function.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1120 of 1286 rej09b0158-0100 29.3 operation description 29.3.1 definition of words related to accesses "instruction fetch" refers to an access in whic h an instruction is fetched. for example, fetching the instruction located at the branch destination afte r executing a branch instru ction is an instruction access. "operand access" refers to any memory acces s accompanying execution of an instruction. for example, accessi ng an address (pc + + ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1121 of 1286 rej09b0158-0100 29.3.2 user break operation sequence the following describes the sequence from when the break condition is set until the user break exception handling is initiated. 1. specify the operand size, bus, instruction fetch/operand access, and read/write as the match conditions using the match condition setting register (cbr0 or cbr1). specify the break address using the match address setting register (car0 or car1), and specify the address mask condition using the match address mask setting register (camr0 or camr1). to include the asid in the match conditions, set the aie bit in the match condition setting register and specify the asid value by the aiv b it in the same register. to include the data value in the match conditions, set the dbe bit in the match condition setting register; specify the break data using the match data setting register (cdr1); and specify the data mask condition using the match data mask setting register (cdmr1). to include the execution count in the match conditions, set the etbe bit of the match condition setting register; and specify the execution count usi ng the execution count break register (cetr1). to use the sequential break, set the mfe bit of the match condition setting register; and specify the number of the first channel using the mfi bit. 2. specify whether or no t to request a break when the match condition is satisfied and the break timing when the match condition is satisfied as a result of fetching the instruction using the match operation setting register (crr0 or crr1). after having set all the bits in the match condition setting register except th e ce bit and the other necessary registers, set the ce bit and read the match condition setting register again. this ensures that the set values in the control registers are valid for the subsequent instructions immediately after reading the register. setting the ce bit of the match condition setting register in the initial state after reset via the control registers may cause an undesired break. 3. when the match condition has been satisfied, the corresponding condition match flag (mf1 or mf0) in the channel match flag register (ccmfr) is set. a break is also requested to the cpu according to the set values in the match opera tion setting register (crr0 or crr1). the cpu operates differently according to the bl bit value of the sr register: when the bl bit is 0, the cpu accepts the break request and executes the specified exception handling; and when the bl bit is 1, the cpu does not execute the exception handling. 4. the match flags (mf1 and mf0) can be used to confirm whether or not the corresponding match condition has been satisfied. although the flag is set when the condition is satisfied, it is not cleared automatically; th erefore, write 0 to the flag bit by issuing a memory store instruction to the channel match flag register (ccmfr) in order to use the flag again. 5. breaks may occur virtually at the same time for channels 0 and 1. in this case, only one break request is sent to the cpu; however, the two condition match flags corresponding to these breaks may be set.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1122 of 1286 rej09b0158-0100 6. while the bl bit in the sr re gister is 1, no break requests ar e accepted. however, whether or not the condition has been satisfied is determined. when the condition is determined to be satisfied, the corresponding condition match flag is set. 7. if the sequential break conditions are set, the condition match flag is set every time the match conditions are satisfied for each channel. when the conditions have been satisfied for the first channel in the sequence but no t for the second channel in th e sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state. 29.3.3 instruction fetch cycle break 1. if the instruction fetch cycle is set in the ma tch condition setting register (cbr0 or cbr1), the instruction fetch cycle is handled as a match cond ition. to request a break upon satisfying the match condition, set the bie bit in the match operation setting register (crr0 or crr1) of the corresponding channel. either before or after executing the instruction can be selected as the break timing according to the pcb bit value. if the instruction fetch cycle is specified as a match condition, be sure to clear the lsb to 0 in the match address setting register (car0 or car1); otherwise, no break occurs. 2. if pre-instruction-execution break is specified for the instructi on fetch cycle, the break is requested when the instruction is fetched and de termined to be executed. therefore, this function cannot be used for the instructions which are fetched through overrun (i.e., the instructions fetched during branching or making transition to the interrupt routine but not executed). for priorities of pre-instruction-execution break and the other exceptions, refer to section 5, exception handling. if pre-instruction-execution break is specified for the delayed slot of the delayed branch instruction, the break is requested before the delayed branch instruction is executed. however, do not specify pre-instruction-execution break for the delayed slot of the rte instruction. 3. if post-instruction-execution break is specified for the instruction fetch cycle, the break is requested after the instruction which satisfied the match condition has been executed and before the next instruction is executed. similar to pre-instruction-execution break, this function cannot be used for the instructions which are fetched through overrun. for priorities of post-instruction-execution break and the other exceptions, refer to section 5, exception handling. if post-instruction-execution break is specified for the delayed branch instruction and its delayed slot, the break does not occur until the first instruction at the branch destination. 4. if the instruction fetch cycle is specified as the channel 1 match condition, the dbe bit of match condition setting register cbr1 becomes invalid, the settings of match data setting register cdr1 and match data mask setting register cdmr1 are ignored. therefore, the data value cannot be specified for th e instruction fetch cycle break.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1123 of 1286 rej09b0158-0100 29.3.4 operand access cycle break 1. table 29.4 shows the relation between the operand sizes specified using the match condition setting register (cbr0 or cbr1) and the addres s bits to be compared for the operand access cycle break. table 29.4 relation between operand sizes and address bits to be compared selected operand size addr ess bits to be compared quadword address bits a31 to a3 longword address bits a31 to a2 word address bits a31 to a1 byte address bits a31 to a0 operand size is not included in the match conditions address bits a31 to a3 for quadword access address bits a31 to a2 for longword access address bits a31 to a1 for word access address bits a31 to a0 for byte access the above table means that if ad dress h'00001003 is set in the match address setting register (car0 or car1), for example, the match condi tion is satisfied for the following access cycles (assuming that all the other conditions are satisfied): ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1124 of 1286 rej09b0158-0100 3. the operand access accompanying the pref, ocbp, ocbwb, and ocbi instructions are access without the data value; ther efore, if the data value is included in the match conditions for these instructions, the match conditions will never be satisfied. 4. if the operand bus is selected, a break occurs after executing the instruction which has satisfied the conditions and immediately before executing the next instruction. however, if the data value is included in the match conditions, a break may occur afte r executing several instructions after the instruction which has satisfi ed the conditions; therefore, it is impossible to identify the instruction causing the break. if such a break has occurred for the delayed branch instruction or its delayed slot, the break does not occur until the first instruction at the branch destination. however, do not specify the operand break for the delayed slot of the rte instruction. and if the data value is included in the match conditions, it is not allowed to set the break for the preceding the rte instruction by one to six instructions. 29.3.5 sequential break 1. sequential break conditions can be specified by setting the mfe and mfi bits in the match condition setting registers (cbr0 and cbr1). (sequential break involves two cases such that channel 0 break condition is satisfied then cha nnel 1 break condition is satisfied, and vice versa.) to use the sequential break function, clear the mfe bit of the match condition setting register and the bie bit of the match operati on setting register of the first channel in the sequence, and set the mfe bit an d specify the number of the s econd channel in the sequence using the mfi bit in the match condition setting regi ster of the second channel in the sequence. if the sequential break condition is set, the condition match flag is set every time the match condition is satisfied for each channel. when the condition has been satisfied for the first channel in the sequence but no t for the second channel in th e sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state. 2. for channel 1, the execution count break condition can also be included in the sequential break conditions. 3. if the match conditions for the first and second channels in the sequence are satisfied within a significantly short time, sequential operation may not be guaranteed in some cases, as shown below.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1125 of 1286 rej09b0158-0100 ? instruction b is 0 instruction after instruction a equivalent to setting the same addresses; do not use this setting. instruction b is one instruction after instruct ion a sequential operation is not guaranteed. instruction b is two or more instructions after instruction a sequential operation is guaranteed. ? instruction b is 0 or one instruction after instruction a sequential operation is not guaranteed. instruction b is two or more instructions after instruction a sequential operation is guaranteed. ? instruction b is 0 to fi ve instructions after instruction a sequential operation is not guaranteed. instruction b is six or more instructions after instruction a sequential operation is guaranteed. ? instruction b is 0 to fi ve instructions after instruction a sequential operation is not guaranteed. instruction b is six or more instructions after instruction a sequential operation is guaranteed.
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1126 of 1286 rej09b0158-0100 29.3.6 program count er value to be saved when a break has occurred, the address of the instruction to be executed when the program restarts is saved in the spc then the exception handling state is initiated. a unique instruction causing a break can be identified unless the data value is included in the match conditions. ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1127 of 1286 rej09b0158-0100 29.4 user break debugging support function by using the user break debugging support function, the branch destination address can be modified when the cpu accepts the user break re quest. specifically, se tting the ubde bit of break control register cbcr to 1 allows branchin g to the address indicated by dbr instead of branching to the address indicated by the [vbr + spc pc ssr sr sr.bl b'1 sr.md b'1 sr.rb b'1 exception/interrupt is generated exception exception/interrupt/trap? tr a p interrupt pc h'a000 0000 pc vbr + vector offset execute rte instruction pc spc sr ssr sgr r15 pc dbr debugging program r15 sgr (stc instruction) reset exception? (cbcr.ubde == 1) && (user break)? exception operation ends intevt interrupt code expevt exception code yes no no yes hardware operations exception handling routine tra trapa (imm) expevt h'160 figure 29.2 flowchart of user break debugging support function
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1128 of 1286 rej09b0158-0100 29.5 user break examples match conditions are specified fo r an instruction fetch cycle: ? ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1129 of 1286 rej09b0158-0100 with the above settings, the user break occurs after executing the in struction at address h'00037226 where asid is h'80 before executing the instruction at address h'0003722e where asid is h'70. ? ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1130 of 1286 rej09b0158-0100 with the above settings, the user break occurs after executing the in struction at address h'00037226 where asid is h'80 and before executing the instruction at address h'0003722e where asid is h'70. ? ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1131 of 1286 rej09b0158-0100 data values and execution count are not included in the conditions. with the above settings, the user break occurs after executing the in struction at address h'00008000 to h'00008ffe where asid is h'80 or before executing the instruction at address h'00008010 to h'00008016 where asid is h'70. match conditions are specified for an operand access cycle: ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1132 of 1286 rej09b0158-0100 29.6 usage notes ? ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1133 of 1286 rej09b0158-0100 ? ? ? ? ?
section 29 user break controller (ubc) rev.1.00 dec. 13, 2005 page 1134 of 1286 rej09b0158-0100
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1135 of 1286 rej09b0158-0100 section 30 user debu gging interface (h-udi) the h-udi is a serial interface which conforms to the jtag (ieee 1149.1: ieee standard test access port and boundary-scan ar chitecture) standard. the h-udi is also used for emulator connection. 30.1 features the h-udi is a serial interface wh ich conforms to the jtag standard. the h-udi is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the appropriate emulator users manual for the method of connecting the emulator. the h-udi has six pins: tck, tms, tdi, tdo, trst , and asebrk /brkack. the pin functions except asebrk /brkack and serial communications protocol conform to the jtag standard. this lsi has additional six pins for emulator connection: (audsync, audck, and audata3 to audata0). these six pins for emulator are multiplexed with on-chip modules. and the h-udi has one chip-mode setting pin: (mpmd). the h-udi has two tap controller blocks; one is for the boundary-scan test and another is h-udi function except the boundary-scan test. the h-udi initial state is for the boundary scan after power-on or trst asserted. it is necessary to set h- udi switchover command to use the h-udi function. and the cpu cannot access the boundary scan tap controller. figure 30.1 shows a block diagram of the h-udi. the h-udi has the tap (test access port) controll er and four registers (sdbpr, sdbsr, sdir, and sdint). sdbpr supports the jtag bypass mode, sdbsr supports the jtag boundary scan mode, sdir is used for commands, and sdint is used for h-udi interrupts. sdir is directly accessed from the tdi and tdo pins. the tap controller, control registers and boundary scan tap controller are initialized by driving the trst pin low or by applying the tck signal for five or more clock cycles with the tms pin set to 1. this initialization sequence is independent of the reset pin for this lsi. other circuits are initialized by a normal reset.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1136 of 1286 rej09b0158-0100 sdir sdbsr sdbpr tck tdo tdi tms trst shift register pin multiplexer tap controller decoder peripheral bus sdint trace controller break controller interrupt/reset etc asebrk /brkack audsync/ fce * audck/fale * audata3/fd3 * audata2/fd2 * audata1/fd1 * audata0/fd0 * drak3 / ce2b /audsync * drak2 / ce2a /audck * dack3 / irqout /audata3 * dack2 / mresetout /audata2 * dreq3 / intc /audata1 * dreq2 / intb /audata0 * note: * these pins are multiplexed with on-chip module's. to use the h-udi (aud) function, select the h-udi module by omselr in gpio. [legend] omselr: on-chip module select register sdbpr: bypass register sdbsr: boundary scan register sdint: interrupt source register sdir: instruction register boundary-scan tap controller omselr gpio pin multiplexer 6 6 figure 30.1 h-udi block diagram
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1137 of 1286 rej09b0158-0100 30.2 input/output pins table 30.1 shows the pin configuration for the h-udi. table 30.1 pin configuration pin name function i/o description when not in use tck clock input functions as the serial cl ock input pin stipulated in the jtag standard. data input to the h-udi via the tdi pin or data output via the tdo pin is performed in synchronization with this signal. open * 1 tms mode input mode select input changing this signal in syn chronization with the tck signal determines the signifi cance of data input via the tdi pin. its protocol conforms to the jtag standard (ieee standard 1149.1). open * 1 trst * 2 reset input h-udi reset input this signal is received asynchronously with a tck signal. asserting this signal resets the jtag interface circuit. when a power is supplied, the trst pin should be asserted for a gi ven period regardless of whether or not the jtag function is used, which differs from the jtag standard. fixed to ground or connected to the preset pin * 3 tdi data input input data input data is sent to the h-udi by changing this signal in synchronization with the tck signal. open * 1 tdo data output output data output data is read from the h-udi in synchronization with the tck signal. open asebrk / brkack emulator i/o pins for an emulator open * 1 audsync, audck, audata3 to audata0 emulator output pins for an emulator open mpmd chip-mode input selects the operation mode of this lsi, whether emulation support mode (low level) or lsi operation mode (high level). open notes: 1. this pin is pulled up in this lsi. w hen using interrupts or resets via the h-udi or emulator, the use of external pull-up resistors will not cause any problem. 2. when using interrupts or resets via the h-udi or emulator, the trst pin should be designed so that it can be controlled independently and can be controlled to retain low level while the preset pin is asserted at a power-on reset.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1138 of 1286 rej09b0158-0100 3. this pin should be connected to ground, the preset , or another pin which operates in the same manner as the preset pin. however, when connected to a ground pin, the following problem occurs. since the trst pin is pulled up within this lsi, a weak current flows when the pin is externally c onnected to ground pin. the value of the current is determined by a resistance of the pull-up mos for the port pin. although this current does not affect the operation of this lsi, it consumes unnecessary power. the tck clock or the cpg of this lsi should be set to ensure that the frequency of the tck clock is less than the peripheral-clock frequency of this lsi. 30.3 boundary scan tap controllers (idcode, extest, sample/preload, and bypass) the h-udi contains two separate tap controllers: one for controlling the boundary-scan function and another for controlling the h-udi reset and interrupt functions. assertion of trst , for example at power-on reset, activat es the boundary-scan tap controller and enables the boundary- scan function prescribed in the jtag standards. executing a switchover command to the h-udi allows usage of the h-udi reset and h-udi interrupts. this lsi, however, has the following limitations: ? clock-related pins (extal, xtal, extal2, and xtal2) are out of the scope of the boundary-scan test. ? reset-related pin ( preset ) is out of the scope of the boundary-scan test. ? h-udi-related pins (tck, tdi, tdo, tms, trst and mpmd) are out of the scope of the boundary-scan test. ? ddrif-related pins are out of the scope of the boundary-scan test. ? xrtctbi pin is out of the scope of the boundary-scan test. ? during the boundary scan (idcode, extest, sample/preload, bypass, and h-udi switchover command), the maximum tck signal frequency is 2 mhz. ? the external controller has 8-bit access to the bo undary-scan tap controll er via the h-udi. note: during the boundary scan, the mpmd and preset pins should be fixed high-level. table 30.2 shows the commands supported by boundary-scan tap controller. figure 30.2 shows the sequence for switching from boundary-scan tap controller to h-udi.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1139 of 1286 rej09b0158-0100 table 30.2 commands supported by boundary-scan tap controller bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 description 0 1 0 1 0 1 0 1 idcode 1 1 1 1 1 1 1 1 bypass 0 0 0 0 0 0 0 0 extest 0 1 0 0 0 0 0 0 sample/preload 0 0 0 0 1 0 0 0 h-udi (switchover command) other than above setting prohibited 00010000 test-logic -reset run-test -idle select-dr select-ir capture-ir exit1-ir update-ir run-test-idle test-logic -reset select-dr select-ir capture-ir shift-ir --- test-logic -reset run-test -idle test-logic -reset run-test -idle shift-ir tck tms trst tdi h-udi run-test-idle trst is asserted h-udi select command is input to boundary-scan tap controller h-udi is used trst is asserted boundary-scan tap controller external pins h-udi selection status status h-udi select command (b'00001000) (when shift-ir state > 8 cycles, input of last 8 cycles is valid) switchover is determined at falling of first tck cycle after the boundary-scan tap controller has entered the run-test/idle state figure 30.2 sequence for switching from boundary-scan tap controller to h-udi
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1140 of 1286 rej09b0158-0100 30.4 register descriptions the h-udi has the following registers. table 30.3 register configuration (1) cpu side register name abbrev. r/w p4 address * 1 area 7 address * 1 size initial value * 2 instruction register sdir r h'fc11 0000 h'1c11 0000 16 h'0eff interrupt source register sdint r/w h'fc11 0018 h'1c11 0018 16 h'0000 boundary scan register sdbsr ? ? ? ? ? bypass register sdbpr ? ? ? ? ? notes: 1. the p4 address is an address when ac cessing through p4 area in a virtual address space. the area 7 address is an address when accessing through area 7 in a physical space using the tlb. 2. the low level of the trst pin or the test-logic-reset state of the tap controller initializes to these values. table 30.4 register configuration (2) h-udi side register name abbrev. r/w size initial value * 1 instruction register sdir r/w 32 h'ffff fffd (fixed value * 2 ) interrupt source register sdint w * 3 32 h'0000 0000 boundary scan register sdbsr ? ? ? bypass register sdbpr r/w 1 undefined note: 1. the low level of the trst pin or the test-logic-reset state of the tap controller initializes to these values. 2. when reading via the h-udi, the value is always h'ffff fffd. 3. only 1 can be written to the lsb by the h-udi interrupt command. table 30.5 register status in each processing state register name abbrev. power-on reset manual reset sleep instruction register sdir h'0eff retained retained interrupt source register sdint h'0000 retained retained
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1141 of 1286 rej09b0158-0100 30.4.1 instruction register (sdir) sdir is a 16-bit read-only register that can be read from the cpu. commands are set via the serial input (tdi). sdir is initialized by trst or in the test-logic-reset state and can be written by the h-udi irrespective of the cpu mode. operatio n is not guaranteed when a reserved command is set to this register. ti bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 00111011111111 rrrrrrrrrrrrrrr r bit bit name initial value r/w description 15 to 8 ti 0000 1110 r test instruction bits 7 to 0 0110 xxxx: h-udi reset negate 0111 xxxx: h-udi reset assert 101x xxxx: h-udi interrupt 0000 1110: initial state other than above: setting prohibited note: though h-udi reset asserted, cpg, watchdog/reset and part of rtc registers are not initialized. 7 to 0 ? all 1 r reserved these bits are always read as 1.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1142 of 1286 rej09b0158-0100 30.4.2 interrupt so urce register (sdint) sdint is a 16-bit register that can be read from or written to by the cpu. specifying an h-udi interrupt command in sdir via h-udi pin (update-ir) sets the intreq bit to 1. while an h- udi interrupt command is set in sdir, sdint which is connected between the tdi and tdo pins can be read as a 32-bit register. in this case, the upper 16 bits will be 0 and the lower 16 bits represent the sdint value. only 0 can be written to the intreq bit by the cpu. while this bit is set to 1, an interrupt request will continue to be generated. this bit, theref ore, should be cleared by the interrupt handling routine. it is initialized by trst or in the test-logic-reset state. intreq bit: initial value: r/w: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 00000000000000 rrrrrrrrrrrrrrr r/w bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 intreq 0 r/w interrupt request indicates whether or not an interrupt by an h-udi interrupt command has occurred. clearing this bit to 0 by the cpu cancels an interrupt request. when writing 1 to this bit, the previous value is maintained. 30.4.3 bypass register (sdbpr) sdbpr is a one-bit register that supports th e j-tag bypass mode. when the bypass command is set to the boundary scan tap controller, the tdi and tdo are connected by way of sdbpr. this register cannot be accessed from the cpu regardless of the ls i mode. though this register is not initialized by a power-on reset and the trst pin asserted, initialized to 0 in the capture-dr state.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1143 of 1286 rej09b0158-0100 30.4.4 boundary scan register (sdbsr) sdbsr is a shift register, located on the pad, for controlling the input/output pins, which supports the boundary scan mode of the jtag standard. using the extest and sample/preload commands, a boundary-scan test complying with the jtag standards (ieee1149.1) can be carried out. table 30.6 show s the correspondence between pins of this lsi and the sdbsr values. this register cannot be accessed from the cpu regardless of the ls i mode. this register is not initialized by a power-on reset and the trst pin asserted. table 30.6 sdbsr configuration number pin name i/o * number pin name i/o * from tdi 503 dreq0 output 524 dack3 / irqout /audata3 output 502 dreq0 control 523 dack3 / irqout /audata3 control 501 dreq0 input 522 dack3 / irqout /audata3 input 500 drak3 / ce2b /audsync output 521 dack2 / mresetout /audata2 output 499 drak3 / ce2b /audsync control 520 dack2 / mresetout /audata2 control 498 drak3 / ce2b /audsync input 519 dack2 / mresetout /audata2 input 497 drak2 / ce2a /audck output 518 dack1 /mode1 output 496 drak2 / ce2a /audck control 517 dack1 /mode1 control 495 drak2 / ce2a /audck input 516 dack1 /mode1 input 494 drak1 /mode7 output 515 dack0 /mode0 output 493 drak1 /mode7 control 514 dack0 /mode0 control 492 drak1 /mode7 input 513 dack0 /mode0 input 491 drak0 /mode2 output 512 dreq3 / intc /audata1 output 490 drak0 /mode2 control 511 dreq3 / intc /audata1 control 489 drak0 /mode2 input 510 dreq3 / intc /audata1 input 488 a25 output 509 dreq2 / intb /audata0 output 487 a25 control 508 dreq2 / intb /audata0 control 486 a25 input 507 dreq2 / intb /audata0 input 485 status0/cmt_ctr0 output 506 dreq1 output 484 status0/cmt_ctr0 control 505 dreq1 control 483 status0/cmt_ctr0 input 504 dreq1 input 482 status1/cmt_ctr1 output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1144 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 481 status1/cmt_ctr1 control 448 a15 control 480 status1/cmt_ctr1 input 447 a15 input 479 a22 output 446 a13 output 478 a22 control 445 a13 control 477 a22 input 444 a13 input 476 a23 output 443 a12 output 475 a23 control 442 a12 control 474 a23 input 441 a12 input 473 a24 output 440 a11 output 472 a24 control 439 a11 control 471 a24 input 438 a11 input 470 a19 output 437 a10 output 469 a19 control 436 a10 control 468 a19 input 435 a10 input 467 a20 output 434 a9 output 466 a20 control 433 a9 control 465 a20 input 432 a9 input 464 a21 output 431 a8 output 463 a21 control 430 a8 control 462 a21 input 429 a8 input 461 a16 output 428 a7 output 460 a16 control 427 a7 control 459 a16 input 426 a7 input 458 a17 output 425 a6 output 457 a17 control 424 a6 control 456 a17 input 423 a6 input 455 a18 output 422 a5 output 454 a18 control 421 a5 control 453 a18 input 420 a5 input 452 a14 output 419 a4 output 451 a14 control 418 a4 control 450 a14 input 417 a4 input 449 a15 output 416 a3 output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1145 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 415 a3 control 382 d24 control 414 a3 input 381 d24 input 413 a2 output 380 we3 / iowr output 412 a2 control 379 we3 / iowr control 411 a2 input 378 we3 / iowr input 410 a1 output 377 d23 output 409 a1 control 376 d23 control 408 a1 input 375 d23 input 407 a0 output 374 d22 output 406 a0 control 373 d22 control 405 a0 input 372 d22 input 404 d31 output 371 d21 output 403 d31 control 370 d21 control 402 d31 input 369 d21 input 401 d30 output 368 d20 output 400 d30 control 367 d20 control 399 d30 input 366 d20 input 398 d29 output 365 d19 output 397 d29 control 364 d19 control 396 d29 input 363 d19 input 395 d28 output 362 d18 output 394 d28 control 361 d18 control 393 d28 input 360 d18 input 392 d27 output 359 d17 output 391 d27 control 358 d17 control 390 d27 input 357 d17 input 389 d26 output 356 d15 output 388 d26 control 355 d15 control 387 d26 input 354 d15 input 386 d25 output 353 d16 output 385 d25 control 352 d16 control 384 d25 input 351 d16 input 383 d24 output 350 we2 / iord output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1146 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 349 we2 / iord control 316 d5 control 348 we2 / iord input 315 d5 input 347 d14 output 314 d6 output 346 d14 control 313 d6 control 345 d14 input 312 d6 input 344 d13 output 311 d1 output 343 d13 control 310 d1 control 342 d13 input 309 d1 input 341 d12 output 308 d2 output 340 d12 control 307 d2 control 339 d12 input 306 d2 input 338 d11 output 305 d3 output 337 d11 control 304 d3 control 336 d11 input 303 d3 input 335 d10 output 302 we0 / reg output 334 d10 control 301 we0 / reg control 333 d10 input 300 we0 / reg input 332 d9 output 299 d0 output 331 d9 control 298 d0 control 330 d9 input 297 d0 input 329 we1 output 296 breq output 328 we1 control 295 breq control 327 we1 input 294 breq input 326 d7 output 293 back output 325 d7 control 292 back control 324 d7 input 291 back input 323 d8 output 290 r/ w output 322 d8 control 289 r/ w control 321 d8 input 288 r/ w input 320 d4 output 287 rd / frame output 319 d4 control 286 rd / frame control 318 d4 input 285 rd / frame input 317 d5 output 284 bs output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1147 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 283 bs control 250 pciclk input 282 bs input 249 gnt0 / gntin output 281 cs4 output 248 gnt0 / gntin control 280 cs4 control 247 gnt0 / gntin input 279 cs4 input 246 pcireset output 278 rdy output 245 req2 output 277 rdy control 244 req2 control 276 rdy input 243 req2 input 275 cs2 output 242 req1 output 274 cs2 control 241 req1 control 273 cs2 input 240 req1 input 272 cs5 output 239 gnt2 output 271 cs5 control 238 gnt2 control 270 cs5 input 237 gnt2 input 269 cs6 output 236 gnt1 output 268 cs6 control 235 gnt1 control 267 cs6 input 234 gnt1 input 266 clkout control 233 ad31 output 265 clkout output 232 ad31 control 264 cs0 output 231 ad31 input 263 cs0 control 230 req3 output 262 cs0 input 229 req3 control 261 cs1 output 228 req3 input 260 cs1 control 227 ad30 output 259 cs1 input 226 ad30 control 258 inta output 225 ad30 input 257 inta control 224 gnt3 output 256 inta input 223 gnt3 control 255 req0 / reqout output 222 gnt3 input 254 req0 / reqout control 221 ad27 output 253 req0 / reqout input 220 ad27 control 252 pciclk output 219 ad27 input 251 pciclk control 218 ad29 output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1148 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 217 ad29 control 184 ad17 control 216 ad29 input 183 ad17 input 215 ad26 output 182 ad19 output 214 ad26 control 181 ad19 control 213 ad26 input 180 ad19 input 212 ad28 output 179 ad16 output 211 ad28 control 178 ad16 control 210 ad28 input 177 ad16 input 209 cbe3 output 176 ad18 output 208 cbe3 control 175 ad18 control 207 cbe3 input 174 ad18 input 206 ad25 output 173 irdy output 205 ad25 control 172 irdy control 204 ad25 input 171 irdy input 203 idsel output 170 cbe2 output 202 idsel control 169 cbe2 control 201 idsel input 168 cbe2 input 200 ad24 output 167 trdy output 199 ad24 control 166 trdy control 198 ad24 input 165 trdy input 197 ad21 output 164 pciframe output 196 ad21 control 163 pciframe control 195 ad21 input 162 pciframe input 194 ad23 output 161 stop output 193 ad23 control 160 stop control 192 ad23 input 159 stop input 191 ad20 output 158 par output 190 ad20 control 157 par control 189 ad20 input 156 par input 188 ad22 output 155 devsel output 187 ad22 control 154 devsel control 186 ad22 input 153 devsel input 185 ad17 output 152 lock output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1149 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 151 lock control 118 ad12 control 150 lock input 117 ad12 input 149 ad15 output 116 ad10 output 148 ad15 control 115 ad10 control 147 ad15 input 114 ad10 input 146 ad13 output 113 ad4 output 145 ad13 control 112 ad4 control 144 ad13 input 111 ad4 input 143 perr output 110 ad2 output 142 perr control 109 ad2 control 141 perr input 108 ad2 input 140 serr output 107 ad8 output 139 serr control 106 ad8 control 138 serr input 105 ad8 input 137 ad11 output 104 ad7 output 136 ad11 control 103 ad7 control 135 ad11 input 102 ad7 input 134 ad9 output 101 ad0 output 133 ad9 control 100 ad0 control 132 ad9 input 99 ad0 input 131 cbe1 output 98 ad5 output 130 cbe1 control 97 ad5 control 129 cbe1 input 96 ad5 input 128 ad14 output 95 ad3 output 127 ad14 control 94 ad3 control 126 ad14 input 93 ad3 input 125 cbe0 output 92 ad1 output 124 cbe0 control 91 ad1 control 123 cbe0 input 90 ad1 input 122 ad6 output 89 nmi output 121 ad6 control 88 nmi control 120 ad6 input 87 nmi input 119 ad12 output 86 irq/ irl0 output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1150 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 85 irq/ irl0 control 58 tclk/ iois16 84 irq/ irl0 input 57 tclk/ iois16 83 irq/ irl1 output 56 scif0_txd/hspi_tx/ fwe /mode8 output 82 irq/ irl1 control 55 scif0_txd/hspi_tx/ fwe /mode8 control 81 irq/ irl1 input 54 scif0_txd/hspi_tx/ fwe /mode8 input 80 irq/ irl2 output 53 scif0_rxd/hspi_rx/frb output 79 irq/ irl2 control 52 scif0_rxd/hspi_rx/frb control 78 irq/ irl2 input 51 scif0_rxd/hspi_rx/frb input 77 irq/ irl3 output 50 scif0_cts / intd /fcle output 76 irq/ irl3 control 49 scif0_cts / intd /fcle control 75 irq/ irl3 input 48 scif0_cts / intd /fcle input 74 irq/ irl4 /fd4/mode3 output 47 scif0_rts / hspi_cs / fse output 73 irq/ irl4 /fd4/mode3 control 46 scif0_rts / hspi_cs / fse control 72 irq/ irl4 /fd4/mode3 input 45 scif0_rts / hspi_cs / fse input 71 irq/ irl5 /fd5/mode4 output 44 scif1_sck/mccmd output 70 irq/ irl5 /fd5/mode4 control 43 scif1_sck/mccmd control 69 irq/ irl5 /fd5/mode4 input 42 scif1_sck/mccmd input 68 irq/ irl6 /fd6/mode6 output 41 scif1_txd/mcclk/mode5 output 67 irq/ irl6 /fd6/mode6 control 40 scif1_txd/mcclk/mode5 control 66 irq/ irl6 /fd6/mode6 input 39 scif1_txd/mcclk/mode5 input 65 irq/ irl7 /fd7 output 38 scif1_rxd/mcdat output 64 irq/ irl7 /fd7 control 37 scif1_rxd/mcdat control 63 irq/ irl7 /fd7 input 36 scif1_rxd/mcdat input 62 scif0_sck/hspi_clk/ fre output 35 siof_txd/hac_sdout/ ssi_sdata output 61 scif0_sck/hspi_clk/ fre control 34 siof_txd/hac_sdout/ ssi_sdata control 60 scif0_sck/hspi_clk/ fre input 33 siof_txd/hac_sdout/ ssi_sdata input 59 tclk/ iois16 32 siof_rxd/hac_sdin/ ssi_sck output
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1151 of 1286 rej09b0158-0100 number pin name i/o * number pin name i/o * 31 siof_rxd/hac_sdin/ ssi_sck control 14 audata2/fd2 output 30 siof_rxd/hac_sdin/ ssi_sck input 13 audata2/fd2 control 29 siof_sync/hac_sync/ ssi_ws output 12 audata2/fd2 input 28 siof_sync/hac_sync/ ssi_ws control 11 audata3/fd3 output 27 siof_sync/hac_sync/ ssi_ws input 10 audata3/fd3 control 26 siof_mclk/ hac_res output 9 audata3/fd3 input 25 siof_mclk/ hac_res control 8 audck/fale output 24 siof_mclk/ hac_res input 7 audck/fale control 23 siof_sck/hac_bitclk/ ssi_clk output 6 audck/fale input 22 siof_sck/hac_bitclk/ ssi_clk control 5 audsync/ fce output 21 siof_sck/hac_bitclk/ ssi_clk input 4 audsync/ fce control 20 audata0/fd0 output 3 audsync/ fce input 19 audata0/fd0 control 2 asebrk /brkack output 18 audata0/fd0 input 1 asebrk /brkack control 17 audata1/fd1 output 0 asebrk /brkack input 16 audata1/fd1 control to tdo 15 audata1/fd1 input note: * control is an active-high signal. when control is driven high, the corresponding pin is driven according to the out value.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1152 of 1286 rej09b0158-0100 30.5 operation 30.5.1 tap control figure 30.3 shows the internal states of the tap controller. the state tran sitions basically conform to the jtag standard. ? state transitions occur according to the tms value at the rising edge of the tck signal. ? the tdi value is sampled at the rising edge of th e tck signal and shifted at the falling edge of the tck signal. ? the tdo value is changed at the falling edge of the tck signal. the tdo signal is in a hi-z state other than in the shift-dr or shift-ir state. ? a transition to the test-logic-reset by clearing trst to 0 is performed asynchronously with the tck signal. test -logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 0 1 0 1 1 1 0 figure 30.3 tap controller state transitions
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1153 of 1286 rej09b0158-0100 30.5.2 h-udi reset a power-on reset is generated by the sdir command. after the h-udi reset assert command has been sent from the h-udi pin, sending the h- udi reset negate command resets the cpu (see figure 30.4). the required time between the h-udi reset assert and h-udi reset negate commands is the same as the time for holding the reset pin low in order to reset this lsi by a power-on reset. h-udi reset assert command setting command setting 17 to 42 pck cycles 4 pck cycles h-udi reset negate h-udi pin chip internal reset cpu state reset handling reset normal figure 30.4 h-udi reset 30.5.3 h-udi interrupt the h-udi interrupt function generates an interrupt by setting the appropriate command in sdir from the h-udi. an h-udi interrupt is a genera l exception/interrupt operation, resulting in branching to the vbr address. the h-udi returns from the interrupt handling routine with a rte instruction. when an h-udi interrupt occurs, the exception code h'600 is stored in the interrupt event register (intevt). the prior ity level for the h-udi interrupt can be specified by the bits 28 to 24 in int2pri3. an h-udi interrupt request signal is asserted when the intreq bit in sdint is set to 1 by setting the appropriate command. since the interrupt request signal is not negated until the intreq bit is cleared to 0 by software, it is not possible to lose the interrupt request. while an h-udi interrupt command is set in sdir, sdint is connected between the tdi and tdo pins.
section 30 user debugging interface (h-udi) rev.1.00 dec. 13, 2005 page 1154 of 1286 rej09b0158-0100 30.6 usage notes ? once an sdir command is set, it will be changed only by an assertion of the trst signal, making the tap controller test-logic-reset state, or writing other commands from the h- udi. ? the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. ? an h-udi interrupt or an h-udi reset can be accept ed to cancel sleep mode.
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1155 of 1286 rej09b0158-0100 section 31 electrical characteristics 31.1 absolute maximum ratings table 31.1 absolute maximum ratings *1, *2 item symbol value unit v ddq v dd-rtc ? 0.3 to 4.6 i/o, rtc, ddrif power supply voltage v ccq-ddr ? 0.3 to 3.6 v v dd v dd-pll1/2/3 internal power supply voltage v dd-dll1/2 ? 0.3 to 1.8 v v in ? 0.3 to v ddq + 0.3 * 3 input voltage v in-ddr ? 0.3 to v ccq-ddr + 0.3 * 3 v operating temperature t opr ? 20 to 75 ? 40 to 85 * 4 c storage temperature t stg ? 55 to 125 c notes: 1. the lsi may be permanently dama ged if the maximum ratings are exceeded. 2. the lsi may be permanently damaged if any of the v ss pins are not connected to gnd. 3. the upper limit of the input voltage mu st not exceed the power supply voltage. 4. r8a77800adbg (v) only (code "v" indicates lead free product). 5. for the powering-on and powering-off s equence, see appendix h, turning on and off power supply. 6. it is prohibited to input signals to the following seven pins immediately after power-on reset because the initial states of these pins are port outputs. - dack0 /mode0 (gpio port l3 pin output) - dack1 /mode1 (gpio port l2 pin output) - drak0 /mode2 (gpio port l1 pin output) - drak1 /mode7 (gpio port l0 pin output) - drak2 / ce2a /audck (gpio port k1 pin output) - drak3 / ce2b /audsync (gpio port k0 pin output) - scif0_txd/hspi_tx/ fwe /mode8 (gpio port h3 pin output)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1156 of 1286 rej09b0158-0100 31.2 dc characteristics table 31.2 dc characteristics (t a = ? 20 to 75c / ? 40 to 85c) item symbol min. typ. max. unit test conditions v ddq 3.0 3.3 3.6 3.0 3.3 3.6 normal operation, sleep mode, module standby mode v dd-rtc 2.0 ? 3.6 rtc backup mode v dd v dd-pll1/2/3 power supply voltage v dd-dll1/2 1.15 1.25 1.35 v normal operation, sleep mode v ccq-ddr 2.3 2.5 2.7 reference voltage ddr-v ref 1.15 1.25 1.35 normal operation, sleep mode, ddr backup mode normal operation ? 740 1300 ick = 400mhz sleep mode i dd ? ? 530 normal operation ? 150 220 ick = 400mhz sleep mode i ddq ? ? 90 bck = 100mhz i dd-pll ? ? 25 ma normal operation i dd-dll ? ? 400 a ddr normal operation ? ? 530 ma ddrck = 160mhz ddr backup mode i ccq-ddr ? ? 160 ma supply only ddr i/o (v ccq-ddr = 2.5v, ddr-v ref = 1.25v) rtc operation ? ? 660 a v dd-rtc = 3.3v current dissipation rtc backup mode i dd-rtc ? ? 8 a 32.768khz operation supply only v dd-rtc = 2.0v
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1157 of 1286 rej09b0158-0100 item symbol min. typ. max. unit test conditions preset , nmi, trst , asebrk /brkack, scif0_rts , irq/ irl7 /fd7, irq/ irl6 /fd6/mode6, irq/ irl5 /fd5/mode4, irq/ irl4 /fd4/mode3, irq/ irl3 , irq/ irl2 , irq/ irl1 , irq/ irl0 v ddq 0.9 ? v ddq + 0.3 v ddq = 3.0 to 3.6 v ddr pins ddr- v ref + 0.15 ? v ccq-ddr + 0.3 v ddr-v ref = 1.15 to 1.35v v ccq-ddr = 2.3 to 2.7v pciclk v ddq 0.6 ? v ddq + 0.3 other pci pins v ddq 0.5 ? v ddq + 0.3 other input pins v ih 2 ? v ddq + 0.3 v ddq = 3.0 to 3.6v preset , nmi, trst , asebrk /brkack, scif0_rts , irq/ irl7 /fd7, irq/ irl6 /fd6/mode6, irq/ irl5 /fd5/mode4, irq/ irl4 /fd4/mode3, irq/ irl3 , irq/ irl2 , irq/ irl1 , irq/ irl0 ? 0.3 ? v ddq 0.1 v ddq = 3.0 to 3.6 v ddr pins ?0.3 ? ddr- v ref ? 0.15 ddr-v ref = 1.15 to 1.35v pciclk ?0.3 ? v ddq 0.2 other pci pins ?0.3 ? v ddq 0.3 input voltage other input pins v il ? 0.3 ? v ddq 0.2 v ddq = 3.0 to 3.6v
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1158 of 1286 rej09b0158-0100 item symbol min. typ. max. unit test conditions ddr pins |l| ? ? 2 v in = 0.5, v ccq-ddr ? 0.5v input leak current all input pins |lin| ? ? 1 a v in = 0.5, v ddq ? 0.5v three-state leak current i/o, all output pins (off condition) |lsti| ? ? 1 a v in = 0.5, v ddq ? 0.5v pci pins 2.4 ? ? v ddq = 3.0 to 3.6v i oh = ? 4ma ddr pins 1.84 ? ? v ccq-ddr = 2.3v i oh = ? 7.6ma other output pins v oh 2.4 ? ? v ddq = 3.0 to 3.6v i oh = ? 2ma pci pins ? ? 0.55 v ddq = 3.0 to 3.6v i ol = 4ma ddr pins ? ? 0.54 v ccq-ddr = 2.3v i ol = 7.6ma output voltage other output pins v ol ? ? 0.55 v v ddq = 3.0 to 3.6v i ol = 2ma pull-up resistance all pins r pull 20 60 180 k ? ddr pins ? ? 5 pin capacitance other pins c l ? ? 10 pf note: the current dissipation values are for v ih min = v ddq ? 0.5 v and v il max = 0.5 v with all output pins unload.
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1159 of 1286 rej09b0158-0100 table 31.3 permissible output currents item symbol min. typ. max. unit permissible output low current (per pin; ddr pins) ? ? 16 permissible output low current (per pin; pci pins) ? ? 4 permissible output low current (per pin; other than ddr and pci pins) i ol ? ? 2 permissible output low current (total) i ol ? ? 120 permissible output high current (per pin; ddr pins) ? ? 16 permissible output high current (per pin; pci pins) ? ? 4 permissible output high current (per pin; other than ddr and pci pins) ? i oh ? ? 2 permissible output high current (total) | ? i oh | ? ? 40 ma note: to protect chip reliability, do not e xceed the output current values in table 31.3. 31.3 ac characteristics in principle, this lsi's input should be synchronous. unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. table 31.4 clock timing item symbol min. typ. max. unit cpu, fpu, cache, tlb 2 ? 402 ddr-sdram bus 112 ? 164 external bus 2 ? 101 pci bus dc ? 67 peripheral modules 2.5 ? 51 mhz operating frequency rtc oscillator f 32 ? 33 khz
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1160 of 1286 rej09b0158-0100 31.3.1 clock and cont rol signal timing table 31.5 clock and co ntrol signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75c/ ? 40 to 85c, c l = 30pf) item symbol min. max. unit figure extal clock input frequency pll1 24-times/pll2 operation f ex 2 33.4 mhz extal clock input cycle time t excyc 30 500 ns 31.1 extal clock input low-level pulse width t exl 3.5 ? ns 31.1 extal clock input high-level pulse width t exh 3.5 ? ns 31.1 extal clock input rise time t exr ? 4 ns 31.1 extal clock input fall time t exf ? 4 ns 31.1 clkout clock output pll1/pll2 operation f op 25 101 mhz clkout clock output cycle time t clkoutcyc 10 40 ns 31.2 clkout clock output low-level pulse width t clkoutl1 1 ? ns 31.2 clkout clock output high-level pulse width t clkouth1 1 ? ns 31.2 clkout clock output rise time t clkoutr ? 3 ns 31.2 clkout clock output fall time t clkoutf ? 3 ns 31.2 clkout clock output low-level pulse width t clkoutl2 3 ? ns 31.3 clkout clock output high-level pulse width t clkouth2 3 ? ns 31.3 power-on oscillation settling time t osc1 18 ? ms 31.4 power-on oscillation settling time/mode setting t oscmode 18 ? ms 31.4 power-on rtc oscillation settling time t rtc-osc ? 3 s moden reset setup time t moders 3 ? t cyc 31.5 moden reset hold time t moderh 0 ? ns 31.5 preset assert time t resw 20 ? t cyc 31.4 pll synchronization settling time t pll 200 ? s 31.6 trst reset hold time t trstrh 0 ? ns 31.4 notes: 1. when a crystal resonator is conn ected to extal and xtal, the maximum frequency is 33.4mhz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. the load copacitance connected to the clkout pin should be a maximum of 50 pf. 3. t cyc shows 1 cycle time of a clkout clock.
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1161 of 1286 rej09b0158-0100 t excyc t exh t exl t exr t exf 1/2v ddq v ih v ih v il v il extal input v ih 1/2v ddq note: when the clock is input from the extal pin. figure 31.1 extal clock input timing t clkoutcyc t clkouth1 clkout t clkoutl1 t ckor t ckof 1/2v ddq v oh v oh v ol v ol v oh 1/2v ddq figure 31.2 clkout clock output timing (1) t clkouth2 clkout 1.5v 1.5v 1.5v t clkoutl2 figure 31.3 clkout clock output timing (2)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1162 of 1286 rej09b0158-0100 internal clock vdd moden preset trst t osc1 v dd min t mdrh t oscmode t trstrh stable oscillation t resw clkout note: oscillation settling time when on-chip resonator is used. figure 31.4 power-on oscillation settling time t moders t moderh t prf t prr preset moden figure 31.5 mode pins setup/hold timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1163 of 1286 rej09b0158-0100 extal input t pll clkout output figure 31.6 pll synchronization settling time 31.3.2 control signal timing table 31.6 control signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75c/ ? 40 to 85c, c l = 30pf) item symbol min. max. unit figure breq setup time t breqs 2.5 ? ns 31.7 breq hold time t breqh 1.5 ? ns 31.7 back delay time t backd ? 6 ns 31.7 bus three-state delay time t boff1 ? 12 ns 31.7 bus buffer on time t bon1 ? 12 ns 31.7 clkout a[25:0], csn , bs , r/ w , ce2a , ce2b , we , rd breq back t breqh t breqs t breqh t backd t backd t boff1 t bon1 t breqs figure 31.7 control signal timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1164 of 1286 rej09b0158-0100 31.3.3 bus timing table 31.7 bus timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75c/ ? 40 to 85c, c l = 30pf) item symbol min. max. unit notes address delay time t ad 1.5 6 ns bs delay time t bsd 1.5 6 ns cs delay time t csd 1.5 6 ns r/ w delay time t rwd 1.5 6 ns rd delay time t rsd 1.5 6 ns read data setup time t rds 2.5 ? ns read data hold time t rdh 1.5 ? ns we delay time (falling edge) t wedf ? 6 ns relative to clkout falling edge we delay time t wed1 1.5 6 ns write data delay time t wdd 1.5 6 ns rdy setup time t rdys 2.5 ? ns rdy hold time t rdyh 1.5 ? ns frame delay time t fmd 1.5 6 ns mpx iois16 setup time t io16s 2.5 ? ns pcmcia iois16 hold time t io16h 1.5 ? ns pcmcia iowr delay time (falling edge) t icwsdf 1.5 6 ns pcmcia iord delay time t icrsd 1.5 6 ns pcmcia dack delay time t dacd 1.5 6 ns
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1165 of 1286 rej09b0158-0100 t1 t ad t ad t2 clkout a25-a0 csn r/ w rd d31-d0 (read) d31-d0 (write) bs dack t wdd t wdd t wdd t rdh t rds t csd t csd t rwd t rwd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd rdy we figure 31.8 sram bus cycl e: basic bus cycle (no wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1166 of 1286 rej09b0158-0100 t wdd t wdd t wdd clkout a25-a0 csn r/ w rd d31-d0 (read) d31-d0 (write) bs dack rdy we t1 t ad tw t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t bsd t bsd t dacd t dacd figure 31.9 sram bus cycle: ba sic bus cycle (one internal wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1167 of 1286 rej09b0158-0100 t wdd t wdd t wdd clkout a25-a0 csn r/ w rd d31-d0 (read) d31-d0 (write) bs dack rdy we t1 t ad tw twe t2 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t rdyh t rdys t rdyh t rdys t bsd t bsd t dacd t dacd figure 31.10 sram bus cycle: basic bus cycle (one internal wait + one external wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1168 of 1286 rej09b0158-0100 t wdd t wdd t wdd ts1 t ad t1 t2 th1 t ad t rdh t rds t csd t rwd t rwd t csd t rsd t rsd t rsd t wed1 t wedf t wedf t bsd t bsd t dacd t dacd clkout a25-a0 csn r/ w rd d31-d0 (read) d31-d0 (write) bs dack rdy we figure 31.11 sram bus cycle: basic bus cycle (no wait, no address setup/hold time insert ion, rds = 1, rdh = 0, wts = 1, wth = 1)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1169 of 1286 rej09b0158-0100 clkout a25-a5 t1 t2 csn r/ w rd d31-d0 (read) bs rdy a4-a0 tb2 tb1 tb2 tb1 tb2 tb1 t csd t ad t rwd t bsd t rds t bsd t rsd t rsd t rdh t ad t ad t csd t rwd t rdh t rsd t rds dack t dacd t dacd figure 31.12 burst rom bus cycle (no wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1170 of 1286 rej09b0158-0100 t1 t2 tb2 tb1 tb2 tb1 tb2 tb1 twb twb twb twe tw t ad t csd t rsd t rdh t rds t bsd t ad t rdh t rsd t rds t ad t csd t rdyh t rdys t rdyh t rdys t rdyh t rdys t dacd t dacd t rwd t rwd clkout a25-a5 csn r/ w rd d31-d0 (read) bs rdy a4-a0 dack figure 31.13 burst rom bus cycle (1st data: one internal wait + one external wait ; 2nd/3rd/4th data: one internal wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1171 of 1286 rej09b0158-0100 t1 tb2 t csd t rwd t bsd t rds t bsd t rsd t ad ts1 tb1 tb2 t ad t rdh tb1 tb2 t2 tb1 t ad t csd t rwd t rdh t rsd t rds th1 ts1 th1 ts1 th1 ts1 th1 clkout a25-a5 csn r/ w rd d31-d0 (read) bs rdy a4-a0 dack t dacd t dacd figure 31.14 burst rom bus cycle (no wait, no address setup/hold ti me insertion, rd s = 1, rdh = 0)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1172 of 1286 rej09b0158-0100 tw t1 twe tb2 tb1 twb twbe tb1 tb2 twb twbe twb t2 tb2 twbe tb1 clkout a25-a5 a4-a0 d31-d0 (read) t ad t ad t ad t rdh t rds t rdh t rds bs rdy dack rd t bsd t bsd t bsd t bsd t rsd t rsd csn t rwd t csd t rwd t csd t dacd t dacd t rsd r/ w t rdyh t rdys t rdyh t rdys t rdyh t rdys t rdyh t rdys figure 31.15 burst rom bus cycle (one internal wait + one external wait)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1173 of 1286 rej09b0158-0100 tpcm1 tpcm2 tpcm0 tpcm1 tpcm2 tpcm1we tpcm1w tpcm2w clkout cexx reg ( we0 ) r/ w rd d15-d0 (read) d15-d0 (write) bs dack rdy we1 t ad t ad t wdd t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t rsd t rsd t rsd t wedf t wed1 t wedf t dacd t rdh t rds t dacd (1) tedx = 0, tehx = 0, no wait (2) tedx = 1, tehx = 1, one internal wait + one external wait a25-a0 figure 31.16 pcmcia memory bus cycle
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1174 of 1286 rej09b0158-0100 tpci1 tpci2 tpci0 tpci1 tpci2 tpci1we tpci1w tpci2w clkout cexx reg ( we0 ) r/ w iord ( we2 ) bs dack rdy iois16 iowr ( we3 ) t ad t ad t bsd t bsd t bsd t bsd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icwsdf t icwsdf t dacd t rdh t rds t rdyh t rdys t rdyh t rdys t io16h t io16s t io16h t io16s t dacd t ad t ad t wdd t wdd t wdd t rwd t csd t csd t rwd t icrsd t icrsd t icrsd t icwsdf t icwsdf t icwsdf t dacd t rdh t rds t dacd d15-d0 (read) d15-d0 (write) (1) tedx = 0, tehx = 0, no wait (2) tedx = 1, tehx = 1, one internal wait + one external wait a25-a0 figure 31.17 pcmc ia i/o bus cycle
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1175 of 1286 rej09b0158-0100 tpci0 tpci1 tpci2w tpci2 tpci1w tpci0 tpci1 tpci2w tpci2 tpci1w clkout a25-a1 a0 cexx reg ( we0 ) r/ w iord ( we2 ) d15- d 0 (read) d15-d0 (write) bs rd y iois 16 io wr ( we3 ) t bs d t bs d t ad t ad t wdd t wdd t wdd t wdd t wdd t rwd t rwd t ad t csd t csd t csd t i crsd t icr s d t icrsd t ic ws d f t icw s df t icwsdf t icwsdf t icw s df t r dh t rds t rd y s t rd y h t io16 s t i o 16h t rd y s t rd y h figure 31.18 pcmc ia i/o bus cycle (tedx = 1, thex = 1, iw/pciw = 1, one internal wait, dynamic bus sizing)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1176 of 1286 rej09b0158-0100 tm1 tmd1w tmd1 tm0 tmd1w tmd1 tmd1we clkou t csn r/ w we d31-d0 bs dack rdy rd / frame t fmd t fmd t bsd t bsd t bsd t bsd t csd t csd t dacd t rdh t rds d0 t rdyh t rd y s t dacd t rwd t rw d t wed1 t wed 1 t fmd t fmd t csd t csd t rdh t rds t wdd a d0 t wdd t wdd a t wdd t rwd t rwd t wed1 t wed1 t dacd t dacd t rdyh t rdys t rdyh t rdys 1st d ata bus cycl e infor mation d3 1-d29: access size 000: byt e 00 1: word (2 byt es) 010: l on g (4 bytes) 1xx: burst (32 bytes) d25-d0: address (1) 1st dat a : one internal wait (2) 1st data : o ne internal wai t + o ne external wai t 1st data bus cycl e infor m ation d3 1-d29: access si ze 000: b y te 001: w or d (2 bytes ) 01 0: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address figure 31.19 mpx basic bus cycle: read
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1177 of 1286 rej09b0158-0100 tm1 tmd1w tmd1 clkout csn r/ w we d31-d0 bs dack rdy rd / frame t fmd t fmd t bsd t bsd t csd t csd t dacd t rdyh t rdys t dacd t wed1 t wed1 tm1 tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd d0 d0 t rdyh t rdys t dacd t rwd t rwd t rwd t rwd t wed1 t wed1 a t rdyh t rdys t rdyh t rdys t wdd t wdd t wdd a t wdd t wdd t wdd tm1 tmd1w tmd1we tmd1 t fmd t fmd t bsd t bsd t csd t csd t dacd t dacd t wed1 t wed1 d0 t rwd t rwd a t wdd t wdd t wdd 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address (1) 1st data : no wait 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address (2) 1st data : one internal wait (3) 1st data : one internal wait + one external wait 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address figure 31.20 mpx basic bus cycle: write
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1178 of 1286 rej09b0158-0100 clkout csn r/ w d31-d0 bs dack rdy rd / frame tm1 tmd1w tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t dacd t dacd d4 t rwd t rwd a t wdd d3 d2 d1 d7 d6 d5 d8 t wdd t rdh t rds tm1 tmd1w tmd1 tmd2we tmd2 tmd3 tmd7 tmd8we tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd d8 t rwd t rwd a t wdd d7 d3 d1 d2 t wdd t rdh t rds t rdys t rdyh t rdyh (1) 1st data : one internal wait, 2nd to 8th data : no internal wait 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address (2) 1st data : one internal wait, 2nd to 8th data : no internal wait + external wait control figure 31.21 mpx bus cycle: burst read
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1179 of 1286 rej09b0158-0100 clkout csn r/ w d31-d0 bs dack rdy rd / frame tm1 tmd1 tmd2 tmd3 tmd4 tmd5 tmd6 tmd7 tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd d4 t rwd t rwd a t wdd d3 d2 d1 d7 d6 d5 d8 d8 d7 d2 d1 d3 t wdd t wdd tm1 tmd1w tmd1 tmd2we tmd2 tmd3 tmd7 tmd8we tmd8 t fmd t fmd t bsd t bsd t csd t csd t rdys t rdyh t dacd t dacd t rwd t rwd a t wdd t wdd t wdd t rdys t rdyh 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address (1) no internal wait (2) 1st data : one internal wait, 2nd to 8th data : no internal wait + external wait control 1st data bus cycle information d31-d29: access size 000: byte 001: word (2 bytes) 010: long (4 bytes) 1xx: burst (32 bytes) d25-d0: address figure 31.22 mpx bu s cycle: burst write
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1180 of 1286 rej09b0158-0100 t1 tw t2 clkout csn r/ w rd (1) basic read cycle : no wait (2) basic read cycle : one internal wait (3) basic read cycle : one internal wait + one external wait we d31-d0 (read) bs dack rdy a25-a0 t csd t csd t dacd t rdyh t rdys t dacd t rwd t rwd t1 t2 t csd t csd t dacd t dacd t wed1 t rwd t rwd t rdyh t rdys t rdyh t rdys t ad t ad t ad t ad t1 tw twe t2 t rsd t rsd t rsd t rsd t rsd t rsd t rsd t rsd t wed1 t wed1 t wedf t wed1 t wedf t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t bsd t bsd t bsd t bsd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds t rdh t rds t rdh t rds figure 31.23 byte co ntrol sram bus cycle
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1181 of 1286 rej09b0158-0100 clkout csn r/ w rd we d31-d0 (read) bs dack rdy a25-a0 ts1 t1 t2 th1 t rsd t rsd t wed1 t wedf t wed1 t csd t csd t dacd t bsd t bsd t dacd t rwd t rwd t rsd t ad t ad t rdh t rds figure 31.24 byte control sram bus cycl e: basic read cycle (no wait, no address setup/hold ti me insertion, rd s = 1, rdh = 0)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1182 of 1286 rej09b0158-0100 31.3.4 ddrif signal timing table 31.8 ddrif signal timing (v ccq-ddr = 2.3 to 2.7v, ddr-v ref = 1.25v, v dd = 1.25v, t a = ? 20 to 75c/ ? 40 to 85 c, c l = 30pf, r t = 50 ?, dll1/2 on, fast slew rate) item symbol min. max. unit figure notes 6.2 12 ddr320 mclk output cycle t mclk 7.5 12 ns 31.25 ddr266 mclk output high-level pulse width t mclkh 0.45 0.55 t mclk 31.25 mclk output low-level pulse width t mclkl 0.45 0.55 t mclk 31.25 1.0 ? ddr320 address and control signal setup time to mclk rising edge t adctls 1.2 ? ns 31.26, 31.27 ddr266 1.0 ? ddr320 address and control signal hold time to mclk rising edge t adctlh 1.2 ? ns 31.26, 31.27 ddr266 ? 0.75 0.75 ddr320 mclk-to-mdqs skew time (read) t rmdqs-mclk ? 0.8 0.8 ns 31.26 ddr266 ? 0.5 ddr320 mdqs-mda skew (for dqs and associated mda signals) t rmdqsq ? 0.6 ns ddr266 write command to first mdqs delay time (rising edge) t wmdqss 0.8 1.2 t mclk 31.27 mdqs falling edge setup time to mclk rising edge (write) t wdss 0.25 ? t mclk 31.27 mdqs falling edge hold time to mclk rising edge (write) t wdsh 0.25 ? t mclk 31.27
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1183 of 1286 rej09b0158-0100 item symbol min. max. unit figure notes mdqs high-level pulse width (write) t wmdqsh 0.35 ? t mclk 31.27 mdqs low-level pulse width (write) t wmdqsl 0.35 ? t mclk 31.27 0.7 ? ddr320 mda and mdqm setup time to mdqs rising/ falling edge (write) t wds 0.75 ? ns 31.27 ddr266 0.7 ? ddr320 mda and mdqm hold time to mdqs rising/ falling edge (write) t wdh 0.75 ? ns 31.27 ddr266 note: t mclk : one mclk cycle time mclk t mclk t mclkl t mclkh mclk figure 31.25 mclk output timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1184 of 1286 rej09b0158-0100 mclk mclk mdqs d0 d1 d2 d3 d0 d1 d2 d3 mdqs mda mda cke, mcs , we , ma, ba, mras , mcas t adctls t rmdqsq t rmdqs-mclk (min) t adctlh t rmdqs t rmdqs-mclk (max) figure 31.26 read timing of ddr-sdram (2 burst read)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1185 of 1286 rej09b0158-0100 mclk mclk mdqs d0 d1 d2 mda, mdqm cke, mcs , we , ma, ba, mras , mcas t adctls write command t wds t wdh t wmdqss (min) t adctlh t wmdqsh t wdss t wdsh t wds t wdh t wds t wdh t wmdqsl mdqs d0 d1 d2 mda, mdqm t wds t wdh t wmdqss (max) t wmdqsh t wdss t wdsh t wmdqsl d3 d3 figure 31.27 write timing of ddr-sdram (2 burst write)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1186 of 1286 rej09b0158-0100 31.3.5 intc module signal timing table 31.9 intc module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure notes nmi pulse width (high) t nmih 5 ? t cyc 31.28 normal mode sleep mode nmi pulse width (low) t nmil 5 ? t cyc 31.28 normal mode sleep mode irq/ irl7 to irq/ irl0 setup time t irqs 3.5 ? ns 31.29 irq input irq/ irl7 to irq/ irl0 hold time t irqh 1.5 ? ns 31.29 irq input irq/ irl7 to irq/ irl0 setup time t irls 3.5 ? ns 31.29 irl input irq/ irl7 to irq/ irl0 hold time t irlh 1.5 ? ns 31.29 irl input gpio interrupt setup time (port e6- e0, h1, h0, j0, k5, k4) t gpios 3.5 ? ns 31.29 gpio interrupt input gpio interrupt hold time (port e6- e0, h1, h0, j0, k5, k4) t gpioh 1.5 ? ns 31.29 gpio interrupt input irqout output delay time t irqod 1.5 6 ns 31.29 irqout output note: t cyc : one clkout cycle time nmi t nmil t nmih figure 31.28 nmi input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1187 of 1286 rej09b0158-0100 irq/ irl , gpio irqout clkout t irqs t irls t gpios t irqh t irlh t gpioh t irqod figure 31.29 irq/irl, gpio interrupt input and irqout output timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1188 of 1286 rej09b0158-0100 31.3.6 pcic module signal timing table 31.10 pcic signal timing (i n pcireq/pcignt non-port mode) (1) (v ddq = 3.0 to 3.6 v, v dd = 1.25 v, t a = ? 20 to 75 c/?40 to 85 c, c l = 30 pf) 33 mhz 66 mhz pin item symbol min max min max unit figure clock cycle t pcicyc 30 ? 15 30 ns 31.30 clock pulse width (high) t pcihigh 11 ? 6 ? ns 31.30 clock pulse width (low) t pcilow 11 ? 6 ? ns 31.30 clock rise time t pcir ? 4 ? 1.5 ns 31.30 pciclk clock fall time t pcif ? 4 ? 1.5 ns 31.30 input setup time t pcisu 3 ? 3 ? ns 31.32 idsel input hold time t pcih 1.5 ? 1.5 ? ns 31.32 output data delay time t pcival 2 10 2 6 ns 31.31 tri-state drive delay time t pcion 2 10 2 6 ns 31.31 tri-state high-impedance delay time t pcioff 2 12 2 6 ns 31.31 input setup time t pcisu 3 ? 3 ? ns 31.32 ad31?ad0 cbe3?cbe0 par pciframe irdy trdy stop lock devsel perr input hold time t pcih 1.5 ? 1.5 ? ns 31.32 output data delay time t pcival 2 10 2 6 ns 31.31 tri-state drive delay time t pcion 2 10 2 6 ns 31.31 tri-state high-impedance delay time t pcioff ? 12 ? 6 ns 31.31 input setup time t pcisu 3 ? 3 ? ns 31.32 req0 / reqout req3 ? req1 gnt0 / gntin gnt3 ? gnt1 input hold time t pcih 1.5 ? 1.5 ? ns 31.32 tri-state drive delay time t pcion 2 10 2 6 ns 31.31 tri-state high-impedance delay time t pcioff 2 12 2 6 ns 31.31 input setup time t pcisu 3 ? 3 ? ns 31.32 serr inta ? intd input hold time t pcih 1.5 ? 1.5 ? ns 31.32
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1189 of 1286 rej09b0158-0100 0.5v ddq 0.5v ddq t pcicyc pciclk t pcihigh v h v h v h v l v l t pcilow t pcif t pcir figure 31.30 pci clock input timing output delay tri-state output pciclk t pcival 0.4v ddq 0.4v ddq t pcion t pcioff figure 31.31 output signal timing input pciclk 0.4v ddq 0.4v ddq 0.4v ddq t pcih t pcisu figure 31.32 input signal timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1190 of 1286 rej09b0158-0100 31.3.7 dmac module signal timing table 31.11 dmac modu le signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure notes dreq setup time t drqs 2.5 ? ns 31.33 dreq hold time t drqh 1.5 ? ns 31.33 drak delay time t drakd 1.5 5.3 ns 31.33 dack delay time t dacd 1.5 6 ns 31.8 etc. t drakd t drqh t drqh t drqs t drqs clkout dreq drac figure 31.33 dreq and drak timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1191 of 1286 rej09b0158-0100 31.3.8 tmu module signal timing table 31.12 tmu module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure notes timer clock pulse width (high) t tclkwh 4 ? t pcyc 31.34 timer clock pulse width (low) t tclkwl 4 ? t pcyc 31.34 timer clock rise time t tclkr ? 0.8 t pcyc 31.34 timer clock fall time t tclkf ? 0.8 t pcyc 31.34 note: t pcyc : one pck cycle tim t tclkwh tclk t tclkwl t tclkf t tclkr figure 31.34 tclk input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1192 of 1286 rej09b0158-0100 31.3.9 cmt module signal timing table 31.13 cmt module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure cmt_ctr output delay time t tmd ? 8 ns 31.35 cmt_ctr input setup time t tms 5 ? ns 31.35 cmt_ctr input hold time t tmh 5 ? ns 31.35 timer clock low level width t tmlow 1.5 ? t cyc 31.36 timer clock high level width t tmhigh 1.5 ? t cyc 31.36 note: t cyc : one clkout cycle time t tmd t tms t tmh clkout cmt_ctr cmt_ctr figure 31.35 cmt timing (1) t tmhigh t tms t tmlow clkout cmt_ctr figure 31.36 cmt timing (2)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1193 of 1286 rej09b0158-0100 31.3.10 scif module signal timing table 31.14 scif module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure notes input clock cycle (asynchronous) 4 ? t pcyc 31.37 input clock cycle (synchronous) t scyc 6 ? t pcyc 31.37 input clock pulse width t sckw 0.4 0.6 t scyc 31.37 input clock rise time t sckr ? 0.8 t pcyc 31.37 input clock fall time t sckf ? 0.8 t pcyc 31.37 transfer data delay time t txd 1.5 6 ns 31.38 receive data setup time (synchronous) t rxs 16 ? ns 31.38 receive data hold time (synchronous) t rxh 16 ? ns 31.38 note: t pcyc : one pck cycle time t sckw scifn_sck t scyc t sckf t sckr figure 31.37 scifn_sck input clock timing (n = 0, 1)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1194 of 1286 rej09b0158-0100 scifn_txd scifn_sck scifn_rxd t scyc t rxs t rxh t txd t txd figure 31.38 scif channel n i/o synchr onous mode clock timing (n = 0, 1)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1195 of 1286 rej09b0158-0100 31.3.11 siof module signal timing table 31.15 siof mo dule signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure siof_mclk clock input cycle time t mcyc t pcyc * ? ns 31.39 siof_mclk input high level width t mwh 0.4 t mcyc ? ns 31.39 siof_mclk input low level width t mwl 0.4 t mcyc ? ns 31.39 siof_sck clock cycle time t sicyc t pcyc * ? ns 31.40 to 31.44 siof_sck output high level width t swho 0.4 t sicyc ? ns 31.40 to 31.43 siof_sck output low level width t swlo 0.4 t sicyc ? ns 31.40 to 31.43 siof_sync output delay time t fsd ? 10 ns 31.40 to 31.43 siof_sck input high level width t swhi 0.4 t sicyc ? ns 31.44 siof_sck input low level width t swli 0.4 t sicyc ? ns 31.44 siof_sync input setup time t fss 10 ? ns 31.44 siof_sync input hold time t fsh 10 ? ns 31.44 siof_txd output delay time t stdd ? 10 ns 31.40 to 31.44 siof_rxd input setup time t srds 10 ? ns 31.40 to 31.44 siof_rxd input hold time t srdh 10 ? ns 31.40 to 31.44 note: * t pcyc is a cycle time of a peripheral clock (pck). t mwh t mwl t mcyc siof_mclk figure 31.39 siof_mclk input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1196 of 1286 rej09b0158-0100 t sicyc t swlo t swho t fsd t stdd t stdd t srds t srdh t fsd siof_sck (output) siof_sync (output) siof_txd siof_rxd figure 31.40 siof transmission/reception timing (master mode 1, fall sampling) t sicyc t swho t swlo t fsd t stdd t stdd t srds t srdh t fsd siof_sck (output) siof_sync (output) siof_txd siof_rxd figure 31.41 siof transmission/reception timing (master mode 1, rise sampling)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1197 of 1286 rej09b0158-0100 t sicyc t swlo t swho t stdd t stdd t stdd t stdd t srds t srdh t fsd t fsd siof_sck (output) siof_sync (output) siof_txd siof_rxd figure 31.42 siof transmission/reception timing (master mode 2, fall sampling) t sicyc t swho t swlo t stdd t stdd t stdd t stdd t srds t srdh t fsd t fsd siof_sck (output) siof_sync (output) siof_txd siof_rxd figure 31.43 siof transmission/reception timing (master mode 2, rise sampling)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1198 of 1286 rej09b0158-0100 t sicyc t swli t swhi t fsh t stdd t stdd t srds t srdh t fss siof_sck (input) siof_sync (input) siof_txd siof_rxd figure 31.44 siof transmission/reception timing (slave mode 1, slave mode 2)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1199 of 1286 rej09b0158-0100 31.3.12 hspi module signal timing table 31.16 hspi module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure hspi_clk frequency t spicyc ? pck/8 hz 31.45 hspi clock high level width t spihw 60 ? ns 31.45 hspi clock low level width t spilw 60 ? ns 31.45 hspi_tx setup time (master mode) t suspitx 20 ? ns 31.45 hspi_tx delay time (master mode) t dspitx ? 20 ns 31.45 hspi_tx setup time (slave mode) t suspitx 10 ? ns 31.45 hspi_tx delay time (slave mode) t dspitx ? 80 ns 31.45 hspi_rx setup time t suspirx 20 ? ns 31.45 hspi_rx hold time t hlspirx 20 ? ns 31.45 hspi_cs lead time t cslead 100 ? ns 31.45 note: pck : peripheral clock frequency
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1200 of 1286 rej09b0158-0100 (clkp= 1) hspi_clk (clkp= 0) hspi_clk hspi_cs (fbs = 0) hspi_tx hspi_rx (fbs = 1) hspi_tx hspi_rx t spicyc t spilw t spihw t cslead t suspitx t dspitx msb msb-1 msb msb-1 msb-2 msb msb-1 msb msb-1 t suspirx t hlspirx t suspitx t dspitx t suspirx t hlspirx figure 31.45 hspi data output/input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1201 of 1286 rej09b0158-0100 31.3.13 mmcif module signal timing table 31.17 mmcif module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure mcclk clock cycle time t mmcyc 50 ? ns 31.46 mcclk clock high level width t mmwh 0.4 t mmcyc ? ns 31.46 mcclk clock low level width t mmwl 0.4 t mmcyc ? ns 31.46 mccmd output data delay time t mmtcd ? 10 ns 31.46 mccmd input data setup time t mmrcs 10 ? ns 31.47 mccmd input data hold time t mmrch 10 ? ns 31.47 mcdat output data delay time t mmtdd ? 10 ns 31.46 mcdat input data setup time t mmrds 10 ? ns 31.47 mcdat input data hold time t mmrdh 10 ? ns 31.47 t mmwh t mmtcd t mmtcd t mmtdd t mmtdd t mmcyc t mmwl mcclk mccmd (output) mcdat (output) figure 31.46 mmcif transmit timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1202 of 1286 rej09b0158-0100 t mmrcs t mmrch t mmrdh t mmrds mcclk mccmd (input) mcdat (input) figure 31.47 mmcif receive timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1203 of 1286 rej09b0158-0100 31.3.14 hac interface module signal timing table 31.18 hac interfac e module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85c, c l = 30pf) item symbol min. max. unit figure hac_res active low pulse width t rst_low 1000 ? ns 31.48 hac_sync active high pulse width t syn_high 1000 ? ns 31.49 hac_sync delay time 1 t syncd1 0 15 ns 31.51 hac_sync delay time 2 t syncd2 0 15 ns 31.51 hac_sd_out delay time t sdoutd 0 15 ns 31.51 hac_sd_in setup time t sdins 10 ? ns 31.51 hac_sd_in hold time t sdinh 10 ? ns 31.51 hac_bit_clk input high level width t icl_high t pcyc /2 ? ns 31.50 hac_bit_clk input low level width t icl_low t pcyc /2 ? ns 31.50 note: t pcyc : one pck cycle time hac_res t rst_low figure 31.48 hac cold reset timing hac_sync t syn_high figure 31.49 hac sync output timing t icl_high t icl_low hac_bitclk figure 31.50 hac clock input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1204 of 1286 rej09b0158-0100 hac_bitclk hac_sdin hac_sdout hac_sync t sdins t sdinh t sdoutd t syncd1 t syncd2 figure 31.51 hac interface module signal timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1205 of 1286 rej09b0158-0100 31.3.15 ssi interface module signal timing table 31.19 ssi interface module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit notes figure output cycle time t osck 40 710 ns output 31.52 input cycle time t isck 80 3300 ns input 31.52 input high level width/output high level width t ihc /t ohc 65 ? ns input, output 31.52 input low level width/output low level width t ilc /t olc 65 ? ns input, output 31.52 ssi_sck output rise time t rc ? 60 ns output 31.52 ssi_sdata/ws output delay time t dtr ? 10 ns transmit 31.53, 31.54 ssi_sdata/ws input setup time t sr 10 ? ns receive 31.55, 31.56 ssi_sdata/ws input hold time t htr 10 ? ns receive 31.55, 31.56 t ohc t ihc v ih, v oh v ih, v oh v ih, v oh v il, v ol v il, v ol v il, v ol t olc t ilc t isck, t osck t rc ssi_sck figure 31.52 ssi clock input/output timing t dtr ssi_sck ssi_ws, ssi_sdata figure 31.53 ssi transmit timing (1)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1206 of 1286 rej09b0158-0100 t dtr ssi_sck ssi_ws, ssi_sdata figure 31.54 ssi transmit timing (2) t sr t htr ssi_sck ssi_ws, ssi_sdata figure 31.55 ssi receive timing (1) t sr t htr ssi_sck ssi_ws, ssi_sdata figure 31.56 ssi receive timing (2)
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1207 of 1286 rej09b0158-0100 31.3.16 flctl module signal timing table 31.20 flctl module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf, no wait) item symbol min. max. unit figure command output setup time t ncds 2 t fcyc ? 10 ? ns command output hold time t nchd 1.5 t fcyc ? 5 ? ns 31.57 data output setup time t ndos 0.5 t fcyc ? 5 ? ns data output hold time t ndoh 0.5 t fcyc ? 10 ? ns 31.57, 31.58 31.60 command to address transition time 1 t ncdad1 1.5 t fcyc ? 10 ? ns 31.57, 31.58 command to address transition time 2 t ncdad2 2 t fcyc ? 10 ? ns 31.58 fwe cycle time t nwc t fcyc ? 5 ? ns 31.58, 31.60 fwe low pulse width t nwp 0.5 t fcyc ? 5 ? ns 31.57, 31.58, 31.60, 31.61 fwe high pulse width t nwh 0.5 t fcyc ? 5 ? ns 31.58, 31.60 address to ready/busy transition time t nadrb ? 32 t pcyc ns 31.58, 31.59 ready/busy to data read transition time 1 t nrbdr1 1.5 t fcyc ? ns ready/busy to data read transition time 2 t nrbdr2 32 t pcyc ? ns fre cycle time t nscc t fcyc ? 5 ? ns 31.59 fre low pulse width t nsp 0.5 t fcyc ? 5 ? ns 31.59, 31.61 fre high pulse width t nsph 0.5 t fcyc ? 5 ? ns 31.59 read data setup time t nrds 24 ? ns read data hold time t nrdh 5 ? ns 31.59, 31.61 data write setup time t ndws 32 t pcyc ? ns 31.59
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1208 of 1286 rej09b0158-0100 item symbol min. max. unit figure command to status read transition time t ncdsr 4 t fcyc ? ns command output off to status read transition time t ncdfsr 3.5 t fcyc ? ns status read setup time t nsts 2.5 t fcyc ? ns 31.60 notes: 1. t fcyc : one flctl clock cycle time 2. t pcyc : one pck cycle time t ndos t ncds t nwp t ncdh t ncdad1 t ndoh command (low) (high) (high) fce fcle fale fwe fre fd7 to fd0 frb (r/ b ) figure 31.57 command issue timi ng of nand-type flash memory
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1209 of 1286 rej09b0158-0100 t nwp t nwp t ncdad1 t nadrb t nwh t nwp t nwh t ndos t ndoh t ndos t ndoh t ndos t ndoh t nwc t ncdad2 address (low) (high) (high) fce fcle fale fwe fre fd7 to fd0 frb (r/ b ) address address figure 31.58 address issue timi ng of nand-type flash memory t nsp t nrbdr2 t nadrb t nrbdr1 t nsph t nrds t nrdh t nsp t nsp t nscc data t nrds t nrds t nrdh data (low) (low) fce fcle fale fwe fre fd7 to fd0 frb (r/ b ) (high) figure 31.59 data read timing of nand-type flash memory
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1210 of 1286 rej09b0158-0100 t nwp t ndws t nwh t ndos t ndoh t nwp t nwp t nwc data t ndos t ndos t ndoh data (low) (low) fce fcle fale fwe fre fd7 to fd0 frb (r/ b ) (high) (high) figure 31.60 data write timing of nand-type flash memory t ndos t ncds t nwp t ncdh t nsts t ncdfsr t ndoh command (low) (high) fce fcle fale fwe fre fd7 to fd0 frb (r/ b ) (low) t nrds t nsp t ncdsr t nrdh status figure 31.61 status read timing of nand-type flash memory
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1211 of 1286 rej09b0158-0100 31.3.17 gpio signal timing table 31.21 gpio signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure gpio output delay time t iopd 1.5 6 ns 31.62 gpio input setup time t iops 3.5 ? ns 31.62 gpio input hold time t ioph 1.5 ? ns 31.62 clkout gpio output gpio input t iopd t iops t ioph figure 31.62 gpio timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1212 of 1286 rej09b0158-0100 31.3.18 h-udi module signal timing table 31.22 h-udi module signal timing (v ddq = 3.0 to 3.6v, v dd = 1.25v, t a = ? 20 to 75 c/ ? 40 to 85 c, c l = 30pf) item symbol min. max. unit figure notes input clock cycle t tckcyc 50 ? ns 31.63, 31.65 input clock pulse width (high) t tckh 15 ? ns 31.63 input clock pulse width (low) t tckl 15 ? ns 31.63 input clock rise time t tckr ? 10 ns 31.63 input clock fall time t tckf ? 10 ns 31.63 asebrk setup time t asebrks 10 ? t cyc 31.64 asebrk hold time t asebrkh 10 ? t cyc 31.64 tdi/tms setup time t tdis 15 ? ns 31.65 tdi/tms hold time t tdih 15 ? ns 31.65 tdo data delay time t tdo 0 10 ns 31.65 asebrk pin break pulse width t pinbrk 2 ? t pcyc 31.66 notes: 1. t cyc : one clkout cycle time 2. t pcyc : one pck cycle time t tckh t tckf t tckr t tckl t tckcyc v ih v ih v ih 1/2v ddq tck 1/2v ddq v il v il note: when clock is input from tck pin. figure 31.63 tck input timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1213 of 1286 rej09b0158-0100 asebrk / brkack preset t asebrkh t asebrks figure 31.64 preset hold timing tdi tms tck tdo t tckcyc t tdo t tdih t tdis figure 31.65 h-udi data transfer timing a sebrk t pinbrk figure 31.66 asebrk pin break timing
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1214 of 1286 rej09b0158-0100 31.4 ac characteristic test conditions the ac characteristic test conditions are as follows : ? input/output signal reference level: v*/2 ? input pulse level: v ssq to v* ? input rise/fall time: 1 ns note: v*: v ddq , v ccq-ddr (v ddq = 3.0 to 3.6v, v ccq-ddr = 2.3 to 2.7v) the output load circuit is shown in figure 31.67 i ol i oh * 2 * 3 * 2 * 1 * 3 c l r t reference level lsi output pin vtt=ddr-v ref (ddr pins only) dut output notes: 1. c l = 30pf (all pins). c l is the total value that includes the capacitance of measurement instruments. the capacitance of each pin is set to 30 pf. 2. r t = 50 ? , v tt = drr - v ref (ddr pins only) 3. i ol = i oh = 7.6 ma (ddr pins), 4 ma (pci pins), 2 ma (other output pins) ? 7.6 ma (ddr pins), ? 4 ma (pci pins), ? 2 ma (other output pins) figure 31.67 output load circuit
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1215 of 1286 rej09b0158-0100 31.5 change in delay time based on load capacitance figure 31.68 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larg er than the stipulated value (30 pf) is connected to the lsi pins. when connecting an external device w ith a load capacitance exceeding the regulation, use the chart in figure 31.68 as reference for system design. note that if the load capacitance to be connec ted exceeds the range shown in figure 31.68 the graph will not be a straight line. +4.0 ns +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pf +25 pf +50 pf load capacitance delay time figure 31.68 load capacitance-delay time
section 31 electric al characteristics rev.1.00 dec. 13, 2005 page 1216 of 1286 rej09b0158-0100
appendix rev.1.00 dec. 13, 2005 page 1217 of 1286 rej09b0158-0100 appendix a. cpu operation mode register (cpuopm) the cpuopm is used to control the cpu operation mode. this register can be read from or written to the address h'ff2f 0000 in p4 area or h'1f2f 0000 in area 7 as 32-bit size. the write value to the reserved bits should be the initial valu e. the operation is not guaranteed if the write value is not the initial value. the cpuopm register should be updated by the cpu store instruc tion not the access from superhyway bus master except cpu. after the cpuopm is updated, read cpuopm once, and execute one of the following two methods. 1. execute a branch using the rte instruction. 2. execute the icbi instruction for any address (including non-cacheable area). after one of these methods are ex ecuted, it is guaranteed that the cpu runs under the updated cpuopm value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000000 00 initial value: rrrrrrrrrrrrrrrr r r r/w r r/w r r r r/w: bit: initial value: r/w: 1514131211109876543210 000000 rrrrrrr r intmu rabd 11111000
appendix rev.1.00 dec. 13, 2005 page 1218 of 1286 rej09b0158-0100 bit bit name initial value r/w description 31 to 6 ? h'000000f r reserved the write value must be the initial value. 5 rabd 1 r/w speculative execution bit for subroutine return 0: instruction fetch for subroutine return is issued speculatively. when this bit is set to 0, refer to appendix c, speculative execution for subroutine return. 1: instruction fetch for subroutine return is not issued speculatively. 4 ? 0 r reserved the write value must be the initial value. 3 intmu 0 r/w interrupt mode switch bit 0: sr.imask is not changed when an interrupt is accepted. 1: sr.imask is changed to the accepted interrupt level. 2 to 0 ? all 0 r reserved the write value must be the initial value.
appendix rev.1.00 dec. 13, 2005 page 1219 of 1286 rej09b0158-0100 b. instruction prefetching and its side effects this lsi is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. therefore, program code must not be located in the last 64-b yte area of any memory space. if program code is located in these areas , a bus access for instruct ion prefetch may occur exceeding the memory areas bounda ry. a case in which this is a problem is shown below. address : h'03ff fff8 h'03ff fffa h'03ff fffc h'03ff fffe h'4000 0000 h'4000 0002 instruction prefetch address instruction : add r1,r4 pc (program counter) jmp @r2 nop nop area 0 area 1 figure b.1 instruction prefetch figure b.1 presupposes a case in which the inst ruction (add) indicated by the program counter (pc) and the address h'04000002 instruction pref etch are executed simult aneously. it is also assumed that the program branches to an area ot her than area 1 after executing the following jmp instruction and delay slot instruction. in this case, a bus access (instruction prefetch ) to area 1 may unintentionally occur from the programming flow. instruction prefetch side effects: 1. it is possible that an exte rnal bus access caused by an inst ruction prefetch may result in misoperation of an external device, such as a fifo, connected to the area concerned. 2. if there is no device to reply to an external bus request caused by an instruction prefetch, hang- up will occur. remedies: 1. these illegal instruction fetches can be avoided by using the mmu. 2. the problem can be avoided by not locating program code in the last 64 bytes of any area.
appendix rev.1.00 dec. 13, 2005 page 1220 of 1286 rej09b0158-0100 c. speculative execution for subroutine return the sh-4a has the mechanism to issue an instru ction fetch speculatively when returning from subroutine. by issueing an instruction fetch speculatively, the execution cycles to return from subroutine may be shortened. this function is enabled by setting 0 to the bit 5 (rabd) of cpu operation mode register (cpuopm). but this speculative instruction fetc h may issue the access to the address that should not be accessed from the program. therefore a bu s access to an unexpected area or an internal instruction address error may cause a problem. as for the effect of this bus access to unexpected memory area, refer to appendix b, in struction prefetch side effects:. usage condition: when the specul ative execution for subroutine return is enabled, the rts instruction should be used to return to the address set in pr by the jsr, bsr or bsrf instructions. it can preven t the access to unexpected address and avoid the problem.
appendix rev.1.00 dec. 13, 2005 page 1221 of 1286 rej09b0158-0100 d. register address map the address map gives information on the on-chip i/o registers. the below listed address is the big endian byte order. when registers consist of 16 or 32 bits, the addresses of the msbs are given. access size indicates the number of bits. note: access to reserved addresses and acce ss with under access size are prohibited. since operation or continued operation is not guaranteed, do not attempt such access. legend: the initial value ?x? means undefined or depends on the setting of the external pins. for details, refer to the each module section. h-udi (h'fc00 0000-h'fc7f ffff; 8m bytes) physical address register name abbreviation initial value r/w access size module h'fc00 0000 to h'fc10 ffff reserved (1,114,112 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fc11 0000 instruction register sdir h'0eff r 16 h-udi h'fc11 0018 interrupt source register sdint h'0000 r/w 16 h-udi h'fc11 001a to h'fc7f ffff reserved (7,274,470 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1222 of 1286 rej09b0158-0100 dmac (h'fc80 0000-h'fcff ffff; 8m bytes) physical address register name abbreviation initial value r/w access size module h'fc80 0000 to h'fc80 7fff reserved (32,768 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fc80 8000 to h'fc80 801f reserved (32 bytes) ? ? ? ? ? h'fc80 8020 dma source address register 0 sar0 h'xxxx xxxx r/w 32 dmac h'fc80 8024 dma destination address register 0 dar0 h'xxxx xxxx r/w 32 dmac h'fc80 8028 dma transfer count register 0 tcr0 h'xxxx xxxx r/w 32 dmac h'fc80 802c dma channel control register 0 chcr0 h'4000 0000 r/w 32 dmac h'fc80 8030 dma source address register 1 sar1 h'xxxx xxxx r/w 32 dmac h'fc80 8034 dma destination address register 1 dar1 h'xxxx xxxx r/w 32 dmac h'fc80 8038 dma transfer count register 1 tcr1 h'xxxx xxxx r/w 32 dmac h'fc80 803c dma channel control register 1 chcr1 h'4000 0000 r/w 32 dmac h'fc80 8040 dma source address register 2 sar2 h'xxxx xxxx r/w 32 dmac h'fc80 8044 dma destination address register 2 dar2 h'xxxx xxxx r/w 32 dmac h'fc80 8048 dma transfer count register 2 tcr2 h'xxxx xxxx r/w 32 dmac h'fc80 804c dma channel control register 2 chcr2 h'4000 0000 r/w 32 dmac h'fc80 8050 dma source address register 3 sar3 h'xxxx xxxx r/w 32 dmac h'fc80 8054 dma destination address register 3 dar3 h'xxxx xxxx r/w 32 dmac h'fc80 8058 dma transfer count register 3 tcr3 h'xxxx xxxx r/w 32 dmac h'fc80 805c dma channel control register 3 chcr3 h'4000 0000 r/w 32 dmac h'fc80 8060 dma operation register0 dmaor0 h'0000 r/w 16 dmac h'fc80 8062 to h'fc80 806f reserved (14 bytes) ? ? ? ? ? h'fc80 8070 dma source address register 4 sar4 h'xxxx xxxx r/w 32 dmac
appendix rev.1.00 dec. 13, 2005 page 1223 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fc80 8074 dma destination address register 4 dar4 h'xxxx xxxx r/w 32 dmac h'fc80 8078 dma transfer count register 4 tcr4 h'xxxx xxxx r/w 32 dmac h'fc80 807c dma channel control register 4 chcr4 h'4000 0000 r/w 32 dmac h'fc80 8080 dma source address register 5 sar5 h'xxxx xxxx r/w 32 dmac h'fc80 8084 dma destination address register 5 dar5 h'xxxx xxxx r/w 32 dmac h'fc80 8088 dma transfer count register 5 tcr5 h'xxxx xxxx r/w 32 dmac h'fc80 808c dma channel control register 5 chcr5 h'4000 0000 r/w 32 dmac h'fc80 8090 to h'fc80 80ff reserved (112 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1224 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fc80 8100 to h'fc80 811f reserved (32 bytes) ? ? ? ? ? h'fc80 8120 dma source address register b 0 sarb0 h'xxxx xxxx r/w 32 dmac h'fc80 8124 dma destination address register b 0 darb0 h'xxxx xxxx r/w 32 dmac h'fc80 8128 dma transfer count register b 0 tcrb0 h'xxxx xxxx r/w 32 dmac h'fc80 812c reserved (4 bytes) ? ? ? ? ? h'fc80 8130 dma source address register b 1 sarb1 h'xxxx xxxx r/w 32 dmac h'fc80 8134 dma destination address register b 1 darb1 h'xxxx xxxx r/w 32 dmac h'fc80 8138 dma transfer count register b 1 tcrb1 h'xxxx xxxx r/w 32 dmac h'fc80 813c reserved (4 bytes) ? ? ? ? ? h'fc80 8140 dma source address register b 2 sarb2 h'xxxx xxxx r/w 32 dmac h'fc80 8144 dma destination address register b 2 darb2 h'xxxx xxxx r/w 32 dmac h'fc80 8148 dma transfer count register b 2 tcrb2 h'xxxx xxxx r/w 32 dmac h'fc80 814c reserved (4 bytes) ? ? ? ? ? h'fc80 8150 dma source address register b 3 sarb3 h'xxxx xxxx r/w 32 dmac h'fc80 8154 dma destination address register b 3 darb3 h'xxxx xxxx r/w 32 dmac h'fc80 8158 dma transfer count register b 3 tcrb3 h'xxxx xxxx r/w 32 dmac h'fc80 815c to h'fc80 8fff reserved (3,748 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fc80 9000 dma extended resource selector 0 dmars0 h'0000 r/w 16 dmac h'fc80 9004 dma extended resource selector 1 dmars1 h'0000 r/w 16 dmac h'fc80 9008 dma extended resource selector 2 dmars2 h'0000 r/w 16 dmac h'fc80 900a to h'fc80 7fff reserved (61,430 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1225 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fc81 8000 to h'fc81 801f reserved (32 bytes) ? ? ? ? ? h'fc81 8020 dma source address register 6 sar6 h'xxxx xxxx r/w 32 dmac h'fc81 8024 dma destination address register 6 dar6 h'xxxx xxxx r/w 32 dmac h'fc81 8028 dma transfer count register 6 tcr6 h'xxxx xxxx r/w 32 dmac h'fc81 802c dma channel control register 6 chcr6 h'4000 0000 r/w 32 dmac h'fc81 8030 dma source address register 7 sar7 h'xxxx xxxx r/w 32 dmac h'fc81 8034 dma destination address register 7 dar7 h'xxxx xxxx r/w 32 dmac h'fc81 8038 dma transfer count register 7 tcr7 h'xxxx xxxx r/w 32 dmac h'fc81 803c dma channel control register 7 chcr7 h'4000 0000 r/w 32 dmac h'fc81 8040 dma source address register 8 sar8 h'xxxx xxxx r/w 32 dmac h'fc81 8044 dma destination address register 8 dar8 h'xxxx xxxx r/w 32 dmac h'fc81 8048 dma transfer count register 8 tcr8 h'xxxx xxxx r/w 32 dmac h'fc81 804c dma channel control register 8 chcr8 h'4000 0000 r/w 32 dmac h'fc81 8050 dma source address register 9 sar9 h'xxxx xxxx r/w 32 dmac h'fc81 8054 dma destination address register 9 dar9 h'xxxx xxxx r/w 32 dmac h'fc81 8058 dma transfer count register 9 tcr9 h'xxxx xxxx r/w 32 dmac h'fc81 805c dma channel control register 9 chcr9 h'4000 0000 r/w 32 dmac h'fc81 8060 dma operation register1 dmaor1 h'0000 r/w 16 dmac h'fc81 8062 to h'fc81 806f reserved (14 bytes) ? ? ? ? ? h'fc81 8070 dma source address register 10 sar10 h'xxxx xxxx r/w 32 dmac h'fc81 8074 dma destination address register 10 dar10 h'xxxx xxxx r/w 32 dmac h'fc81 8078 dma transfer count register 10 tcr10 h'xxxx xxxx r/w 32 dmac h'fc81 807c dma channel control register 10 chcr10 h'4000 0000 r/w 32 dmac h'fc81 8080 dma source address register 11 sar11 h'xxxx xxxx r/w 32 dmac h'fc81 8084 dma destination address register 11 dar11 h'xxxx xxxx r/w 32 dmac
appendix rev.1.00 dec. 13, 2005 page 1226 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fc81 8088 dma transfer count register 11 tcr11 h'xxxx xxxx r/w 32 dmac h'fc81 808c dma channel control register 11 chcr11 h'4000 0000 r/w 32 dmac h'fc81 8090 to h'fc81 80ff reserved (112 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1227 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fc81 8100 to h'fc81 811f reserved (32 bytes) ? ? ? ? ? h'fc81 8120 dma source address register b 6 sarb6 h'xxxx xxxx r/w 32 dmac h'fc81 8124 dma destination address register b 6 darb6 h'xxxx xxxx r/w 32 dmac h'fc81 8128 dma transfer count register b 6 tcrb6 h'xxxx xxxx r/w 32 dmac h'fc81 812c reserved (4 bytes) ? ? ? ? ? h'fc81 8130 dma source address register b 7 sarb7 h'xxxx xxxx r/w 32 dmac h'fc81 8134 dma destination address register b 7 darb7 h'xxxx xxxx r/w 32 dmac h'fc81 8138 dma transfer count register b 7 tcrb7 h'xxxx xxxx r/w 32 dmac h'fc81 813c reserved (4 bytes) ? ? ? ? ? h'fc81 8140 dma source address register b 8 sarb8 h'xxxx xxxx r/w 32 dmac h'fc81 8144 dma destination address register b 8 darb8 h'xxxx xxxx r/w 32 dmac h'fc81 8148 dma transfer count register b 8 tcrb8 h'xxxx xxxx r/w 32 dmac h'fc81 814c reserved (4 bytes) ? ? ? ? ? h'fc81 8150 dma source address register b 9 sarb9 h'xxxx xxxx r/w 32 dmac h'fc81 8154 dma destination address register b 9 darb9 h'xxxx xxxx r/w 32 dmac h'fc81 8158 dma transfer count register b 9 tcrb9 h'xxxx xxxx r/w 32 dmac h'fc81 815c to h'fcff ffff reserved (8,289,956 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1228 of 1286 rej09b0158-0100 pci memory (h'fd00 0000-h'fdff ffff; 16m bytes external memory area) physical address register name abbreviation initial value r/w access size module h'fd00 0000 to h'fdff ffff pci memory space 0 (16,777,216 bytes) ? ? ? ? ? pcic (h'fe00 0000-h'fe3f ffff; 4m bytes) 'r/w' indicates read/write acce ss from the superhyway bus. physical address register name abbreviation initial value r/w access size module h'fe00 0000 to h'fe00 0007 reserved (8 bytes) ? ? ? ? ? h'fe00 0008 pci enable control register pciecr h'0000 0000 r/w 32 pcic h'fe00 000c to h'fe03 ffff reserved (262,132 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1229 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fe04 0000 pci device id register pcidid h'0002 r 16 pcic h'fe04 0002 pci vendor id register pcivid h'1912 r 16 pcic h'fe04 0004 pci status register pcistatus h'0290 r/w 16 pcic h'fe04 0006 pci command register pcicmd h'0080 r/w 16 pcic h'fe04 0008 pci base class code register pcibcc h'00 r/w 8 pcic h'fe04 0009 pci sub class code register pcisub h'00 r/w 8 pcic h'fe04 000a pci program interface r egister pcipif h'00 r/w 8 pcic h'fe04 000b pci revision id register pcirid h'00 r 8 pcic h'fe04 000c pci bist register pcibist h'00 r 8 pcic h'fe04 000d pci header type register pcihdr h'00 r 8 pcic h'fe04 000e pci latency timer register pciltm h'00 r/w 8 pcic h'fe04 000f pci cacheline size register pcicls h'20 r 8 pcic h'fe04 0010 pci i/o base address register pciibar h'0000 0001 r/w 32 pcic h'fe04 0014 pci memory base address register 0 pcimbar0 h'0000 0000 r/w 32 pcic h'fe04 0018 pci memory base address register 1 pcimbar1 h'0000 0000 r/w 32 pcic h'fe04 001c to h'fe04 002b reserved (16 bytes) ? ? ? ? ? h'fe04 002c pci subsystem id register pcisid h'0000 r/w 16 pcic h'fe04 002e pci subsystem vendor id register pcisvid h'0000 r/w 16 pcic h'fe04 0030 to h'fe04 0036 reserved (7 bytes) register ? ? ? ? ? h'fe04 0037 pci capabilities pointer register pcicp h'40 r 8 pcic h'fe04 0038 reserved (4 bytes) ? ? ? ? ? h'fe04 003c pci maximum latency register pcimaxlat h'00 r 8 pcic h'fe04 003d pci minimum grant register pcimingnt h'00 r 8 pcic h'fe04 003e pci interrupt pin register pciintpin h'01 r/w 8 pcic h'fe04 003f pci interrupt line register pciintline h'00 r/w 8 pcic h'fe04 0040 pci power management capability register pcipmc h'000a r/w 16 pcic h'fe04 0042 pci next item pointer register pcinip h'00 r 8 pcic
appendix rev.1.00 dec. 13, 2005 page 1230 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fe04 0043 pci capability id register pcicid h'01 r 8 pcic h'fe04 0044 pci power consumption/dissipation data register pcipcdd h'00 r/w 8 pcic h'fe04 0045 pci pmcsr bridge support extension register pcipmcsrbse h'00 r 8 pcic h'fe04 0046 pci power management control/status register pcipmcsr h'0000 r/w 16 pcic h'fe04 0048 to h'fe04 00ff reserved (184 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1231 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fe04 0100 pci control register pcicr h'0000 00xx r/w 32 pcic h'fe04 0104 pci local space register 0 pcilsr0 h'0000 0000 r/w 32 pcic h'fe04 0108 pci local space register 1 pcilsr1 h'0000 0000 r/w 32 pcic h'fe04 010c pci local address register 0 pcilar0 h'0000 0000 r/w 32 pcic h'fe04 0110 pci local address register 1 pcilar1 h'0000 0000 r/w 32 pcic h'fe04 0114 pci interrupt register pciir h'0000 0000 r/w 32 pcic h'fe04 0118 pci interrupt mask register pciimr h'0000 0000 r/w 32 pcic h'fe04 011c pci error address information register pciair h'xxxx xxxx r 32 pcic h'fe04 0120 pci error command information register pcicir h'xx00 000x r 32 pcic h'fe04 0124 to h'fe04 012f reserved (12 bytes) ? ? ? ? ? h'fe04 0130 pci arbiter interrupt register pciaint h'0000 0000 r/w 32 pcic h'fe04 0134 pci arbiter interrupt mask register pciaintm h'0000 0000 r/w 32 pcic h'fe04 0138 pci arbiter bus master information register pcibmir h'0000 00xx r 32 pcic h'fe04 013c to h'fe04 01bf reserved (132 bytes) ? ? ? ? ? h'fe04 01c0 pci pio address register pcipar h'80xx xxxx r/w 32 pcic h'fe04 01c4 to h'fe04 01cb reserved (8 bytes) ? ? ? ? ? h'fe04 01cc pci power management interrupt register pcipint h'0000 0000 r/w 32 pcic h'fe04 01d0 pci power management interrupt mask register pcipintm h'0000 0000 r/w 32 pcic h'fe04 01d4 to h'fe04 01df reserved (12 bytes) ? ? ? ? ? h'fe04 01e0 pci memory bank register 0 pcimbr0 h'0000 0000 r/w 32 pcic h'fe04 01e4 pci memory bank mask register 0 pcimbmr0 h'0000 0000 r/w 32 pcic h'fe04 01e8 pci memory bank register 1 pcimbr1 h'0000 0000 r/w 32 pcic
appendix rev.1.00 dec. 13, 2005 page 1232 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fe04 01ec pci memory bank mask register 1 pcimbmr1 h'0000 0000 r/w 32 pcic h'fe04 01f0 pci memory bank register 2 pcimbr2 h'0000 0000 r/w 32 pcic h'fe04 01f4 pci memory bank mask register 2 pcimbmr2 h'0000 0000 r/w 32 pcic h'fe04 01f8 pci i/o bank register pciiobr h'0000 0000 r/w 32 pcic h'fe04 01fc pci i/o bank master regi ster pciiobmr h'0000 0000 r/w 32 pcic physical address register name abbreviation initial value r/w access size module h'fe04 0200 to h'fe04 020f reserved (16 bytes) ? ? ? ? ? h'fe04 0210 pci cache snoop control register 0 pcicscr0 h'0000 0000 r/w 32 pcic h'fe04 0214 pci cache snoop control register 1 pcicscr1 h'0000 0000 r/w 32 pcic h'fe04 0218 pci cache snoop address register 0 pcicsar0 h'0000 0000 r/w 32 pcic h'fe04 021c pci cache snoop address register 1 pcicsar1 h'0000 0000 r/w 32 pcic h'fe04 0220 pci pio data register pcipdr h'xxxx xxxx r/w 32 pcic h'fe04 022c to h'fe04 03ff reserved (468 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fe04 0400 to h'fe3f ffff reserved (3,931,136 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1233 of 1286 rej09b0158-0100 superhyway ram (h'fe40 0000-h'fe7f ffff; 4m bytes) physical address register name abbreviation initial value r/w access size module h'fe40 0000 to h'fe40 ffff reserved (65,536 bytes) ? ? ? ? ? h'fe41 0000 to h'fe41 3fff superhyway ram 0 (16,384 bytes) ? undefined r/w * superhyway ram h'fe41 4000 to h'fe41 ffff reserved (49,152 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fe42 0000 to h'fe42 3fff superhyway ram 1 (16,384 bytes) ? undefined r/w * superhyway ram h'fe42 4000 to h'fe7f ffff reserved (4,046,848 bytes) ? ? ? ? ? note: * 8-/16-/32-/64-bit and 16-/32-byte
appendix rev.1.00 dec. 13, 2005 page 1234 of 1286 rej09b0158-0100 ddrif (h'fe80 0000-h'feff ffff; 8m bytes) physical address register name abbreviation initial value r/w access size module h'fe80 0000 to h'fe80 0007 reserved (8 bytes) ? ? ? ? ? h'fe80 0008 memory interface mode register mim (1) h'0000 0000 r/w 32 ddrif h'fe80 000c memory interface mode register mim (2) h'0c34 x100 r/w 32 ddrif h'fe80 0010 ddr-sdram control register scr (1) h'0000 0000 r/w 32 ddrif h'fe80 0014 ddr-sdram control register scr (2) h'0000 0000 r/w 32 ddrif h'fe80 0018 ddr-sdram timing register str (1) h'0000 0000 r/w 32 ddrif h'fe80 001c ddr-sdram timing register str (2) h'0000 0000 r/w 32 ddrif h'fe80 0030 ddr-sdram row attribute register sdr (1) h'0000 0000 r/w 32 ddrif h'fe80 0034 ddr-sdram row attribute register sdr (2) h'0000 0000 r/w 32 ddrif h'fe80 0038 to h'fe80 03ff reserved (968 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'fe80 0400 ddr-sdram back-up register dbk (1) h'0000 0000 r 32 ddrif h'fe80 0408 ddr-sdram back-up register dbk (2) h'0000 000x r 32 ddrif h'fe80 040c to h'febf ffff reserved (4,193,268 bytes) ? ? ? ? ? h'fecx xxxx * ddr-sdram mode register sdmr ? w 32 ddrif note: * the ddr-sdram mode register is placed in the ddr-sdram. the setting value is written to the ddr-sdram register by accessing this address . for details, refer to section 12, ddr-sdram interface (ddrif).
appendix rev.1.00 dec. 13, 2005 page 1235 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'fec8 0000 to h'feff ffff reserved (3,670,016 bytes) ? ? ? ? ? cpu and l ram (h'ff00 0000 -h'ff3f ffff; 4m bytes) physical address register name abbreviation initial value r/w access size module h'ff00 0000 page table entry high register pteh h'xxxx xxxx r/w 32 mmu h'ff00 0004 page table entry low register ptel h'xxxx xxxx r/w 32 mmu h'ff00 0008 translation table base register ttb h'xxxx xxxx r/w 32 mmu h'ff00 000c tlb exception address register tea h'xxxx xxxx r/w 32 mmu h'ff00 0010 mmu control register mmucr h'0000 0000 r/w 32 mmu h'ff00 0014 to h'ff00 001b reserved (8 bytes) ? ? ? ? ? h'ff00 001c cache control register ccr h'0000 0000 r/w 32 cache h'ff00 0020 trapa exception register tra h'xxxx xxxx r/w 32 exception handling h'ff00 0024 exception event register expevt h'0000 0000 r/w 32 exception handling h'ff00 0028 interrupt event register in tevt h'xxxx xxxx r/w 32 exception handling h'ff00 002c to h'ff00 0037 reserved (12 bytes) ? ? r/w ? ? h'ff00 0038 queue address control register 0 qacr0 h'0000 00xx r/w 32 cache h'ff00 003c queue address control register 1 qacr1 h'0000 00xx r/w 32 cache h'ff00 0040 to h'ff00 004f reserved (16 bytes) ? ? ? ? ? h'ff00 0050 l memory transfer source address register 0 lsa0 h'xxxx xxxx r/w 32 l ram
appendix rev.1.00 dec. 13, 2005 page 1236 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ff00 0054 l memory transfer source address register 1 lsa1 h'xxxx xxxx r/w 32 l ram h'ff00 0058 l memory transfer destination address register 0 lda0 h'xxxx xxxx r/w 32 l ram h'ff00 005c l memory transfer destination address register 1 lda1 h'xxxx xxxx r/w 32 l ram h'ff00 0060 to h'ff00 006f reserved (16 bytes) ? ? ? ? ? h'ff00 0070 physical address space control register pascr h'0000 0000 r/w 32 mmu h'ff00 0074 on-chip memory control register ramcr h'0000 0000 r/w 32 cache/ l ram h'ff00 0078 instruction re-fetch inhibit control register irmcr h'0000 0000 r/w 32 mmu h'ff00 007c to h'ff1f ffff reserved (2,097,028 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1237 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ff20 0000 match condition setting register 0 cbr0 h'2000 0000 r/w 32 ubc h'ff20 0004 match operation setting register 0 crr0 h'0000 2000 r/w 32 ubc h'ff20 0008 match address setting register 0 car0 h'xxxx xxxx r/w 32 ubc h'ff20 000c match address mask setting register 0 camr0 h'xxxx xxxx r/w 32 ubc h'ff20 0010 to h?ff20 001f reserved (16 bytes) ? ? ? ? ? h'ff20 0020 match condition setting register 1 cbr1 h'2000 0000 r/w 32 ubc h'ff20 0024 match operation setting register 1 crr1 h'0000 2000 r/w 32 ubc h'ff20 0028 match address setting register 1 car1 h'xxxx xxxx r/w 32 ubc h'ff20 002c match address mask setting register 1 camr1 h'xxxx xxxx r/w 32 ubc h'ff20 0030 match data setting register 1 cdr1 h'xxxx xxxx r/w 32 ubc h'ff20 0034 match data mask setting register 1 cdmr1 h'xxxx xxxx r/w 32 ubc h'ff20 0038 execution count break register 1 cetr1 h'xxxx xxxx r/w 32 ubc h'ff20 003c to h?ff20 05ff reserved (1,476 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ff20 0600 channel match flag register ccmfr h'0000 0000 r/w 32 ubc h'ff20 0604 to h'ff20 061f reserved (28 bytes) ? ? ? ? ? h'ff20 0620 break control register cbcr h'0000 0000 r/w 32 ubc h'ff20 0624 to h'ff2e ffff reserved (981,468bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1238 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ff2f 0000 cpu operation mode register cpuopm h'0000 03e0 r/w 32 exception handling h'ff2f 0004 to h'ff3f ffff reserved (1,114,108 bytes) ? ? ? ? ? superhyway router (h'ff40 000 0-h'ff7f ffff; 4m bytes) physical address register name abbreviation initial value r/w access size module h'ff40 0000 to h'ff40 001f reserved (32 bytes) ? ? ? ? ? h'ff40 0020 memory address map select register mmselr h'0000 0000 r/w 32 lbsc physical address register name abbreviation initial value r/w access size module h'ff40 0024 to h'ff7f ffff reserved (4,194,268 bytes) ? ? ? ? ? lbsc (h'ff80 0000-h'ffbf ffff; 4m bytes) physical address register name abbreviation initial value r/w access size module h'ff80 0000 to h'ff80 0fff reserved (4,096 bytes) ? ? ? ? ? h'ff80 1000 bus control register bcr h'0000 0000 r/w 32 lbsc h'ff80 1004 to h'ff80 1fff reserved (4,092 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1239 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ff80 2000 cs0 bus control register cs0bcr h'7777 7770 r/w 32 lbsc h'ff80 2004 reserved (4 bytes) ? ? ? ? ? h'ff80 2008 cs0 wait control register cs0wcr h'7777 770f r/w 32 lbsc h'ff80 200c reserved (4 bytes) ? ? ? ? ? h'ff80 2010 cs1 bus control register cs1bcr h'7777 7770 r/w 32 lbsc h'ff80 2014 reserved (4 bytes) ? ? ? ? ? h'ff80 2018 cs1 wait control register cs1wcr h'7777 770f r/w 32 lbsc h'ff80 201c reserved (4 bytes) ? ? ? ? ? h'ff80 2020 cs2 bus control register cs2bcr h'7777 7770 r/w 32 lbsc h'ff80 2024 reserved (4 bytes) ? ? ? ? ? h'ff80 2028 cs2 wait control register cs2wcr h'7777 770f r/w 32 lbsc h'ff80 202c to h'ff80 203f reserved (20 bytes) ? ? ? ? ? h'ff80 2040 cs4 bus control register cs4bcr h'7777 7770 r/w 32 lbsc h'ff80 2044 reserved (4 bytes) ? ? ? ? ? h'ff80 2048 cs4 wait control register cs4wcr h'7777 770f r/w 32 lbsc h'ff80 204c reserved (4 bytes) ? ? ? ? ? h'ff80 2050 cs5 bus control register cs5bcr h'7777 7770 r/w 32 lbsc h'ff80 2054 reserved (4 bytes) ? ? ? ? ? h'ff80 2058 cs5 wait control register cs5wcr h'7777 770f r/w 32 lbsc h'ff80 205c reserved (4 bytes) ? ? ? ? ? h'ff80 2060 cs6 bus control register cs6bcr h'7777 7770 r/w 32 lbsc h'ff80 2064 reserved (4 bytes) ? ? ? ? ? h'ff80 2068 cs6 wait control register cs6wcr h'7777 770f r/w 32 lbsc h'ff80 206c reserved (4 bytes) ? ? ? ? ? h'ff80 2070 cs5 pcmcia control register cs5pcr h'7700 0000 r/w 32 lbsc h'ff80 2074 to h'ff80 207f reserved (12 bytes) ? ? ? ? ? h'ff80 2080 cs6 pcmcia control register cs6pcr h'7700 0000 r/w 32 lbsc h'ff80 2084 to h'ffbf ffff reserved (4,185,980 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1240 of 1286 rej09b0158-0100 peripheral modules (h'ffc0 0000-h'ffff ffff; 4m bytes) physical address register name abbreviation initial value r/w access size module h'ffc0 0000 to h'ffc7 ffff reserved (524,288 bytes) ? ? ? ? ? h'ffc8 0000 frequency control regist er frqcr h'1xxx x3xx r/w 32 cpg h'ffc8 0004 to h'ffc8 0023 reserved (32 bytes) ? ? ? ? ? h'ffc8 0024 pll control register pllcr h'0000 e001 r/w 32 cpg h'ffc8 0028 to h'ffc8 002f reserved (8 bytes) ? ? ? ? ? h'ffc8 0030 standby control register mstpcr h'0000 0000 r/w 32 cpg h'ffc8 0034 to h'ffcb ffff reserved (262,092 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffcc 0000 watchdog timer stop time register wdtst h'0000 0000 r/w 32 wdt h'ffcc 0004 watchdog timer control/status register wdtcsr h'0000 0000 r/w 32 wdt h'ffcc 0008 watchdog timer base stop time register wdtbst h'0000 0000 r/w 32 wdt h'ffcc 000c reserved (4 bytes) ? ? ? ? ? h'ffcc 0010 watchdog timer counter wdtcnt h'0000 0000 r 32 wdt h'ffcc 0014 reserved (4 bytes) ? ? ? ? ? h'ffcc 0018 watchdog timer base counter wdtbcnt h'0000 0000 r 32 wdt h'ffcc 001c to h'ffcf ffff reserved (262,116 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1241 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffd0 0000 interrupt control register 0 icr0 h'x000 0000 r/w 32 intc h'ffd0 0004 to h'ffd0 000f reserved (12 bytes) ? ? ? ? ? h'ffd0 0010 interrupt priority register intpri h'0000 0000 r/w 32 intc h'ffd0 0014 to h'ffd0 001b reserved (8 bytes) ? ? ? ? ? h'ffd0 001c interrupt control register 1 icr1 h'0000 0000 r/w 32 intc h'ffd0 0020 reserved (4 bytes) ? ? ? ? ? h'ffd0 0024 interrupt source register intreq h'0000 0000 r/w 32 intc h'ffd0 0028 to h'ffd0 0043 reserved (28 bytes) ? ? ? ? ? h'ffd0 0044 interrupt mask register 0 intmsk0 h'0000 0000 r/w 32 intc h'ffd0 0048 interrupt mask register 1 intmsk1 h'ff00 0000 r/w 32 intc h'ffd0 004c to h'ffd0 0063 reserved (24 bytes) ? ? ? ? ? h'ffd0 0064 interrupt mask clear register 0 intmskclr0 h'0000 0000 r/w 32 intc h'ffd0 0068 interrupt mask clear register 1 intmskclr1 h'0000 0000 r/w 32 intc h'ffd0 006c to h'ffd0 00bf reserved (84 bytes) ? ? ? ? ? h'ffd0 00c0 nmi flag control register nmifcr h'x000 0000 r/w 32 intc h'ffd0 00c4 to h'ffd2 ffff reserved (196,412 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffd3 0000 user interrupt mask level register userimask h'0000 0000 r/w 32 intc h'ffd3 0004 to h'ffd3 ffff reserved (65,532 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1242 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffd4 0000 interrupt priority registers 0 int2pri0 h'0000 0000 r/w 32 intc h'ffd4 0004 interrupt priority registers 1 int2pri1 h'0000 0000 r/w 32 intc h'ffd4 0008 interrupt priority registers 2 int2pri2 h'0000 0000 r/w 32 intc h'ffd4 000c interrupt priority registers 3 int2pri3 h'0000 0000 r/w 32 intc h'ffd4 0010 interrupt priority registers 4 int2pri4 h'0000 0000 r/w 32 intc h'ffd4 0014 interrupt priority registers 5 int2pri5 h'0000 0000 r/w 32 intc h'ffd4 0018 interrupt priority registers 6 int2pri6 h'0000 0000 r/w 32 intc h'ffd4 001c interrupt priority registers 7 int2pri7 h'0000 0000 r/w 32 intc h'ffd4 0020 to h'ffd4 002f reserved (16 bytes) ? ? ? ? ? h'ffd4 0030 interrupt source register (mask state is not affected) int2a0 h'xxxx xxxx r 32 intc h'ffd4 0034 interrupt source register (mask state is affected) int2a1 h'0000 0000 r 32 intc h'ffd4 0038 interrupt mask register int2mskrg h'ffff ffff r/w 32 intc h'ffd4 003c interrupt mask clear register int2mskcr h'0000 0000 r/w 32 intc h'ffd4 0040 individual module interrupt source registers 0 int2b0 h'xxxx xxxx r 32 intc h'ffd4 0044 individual module interrupt source registers 1 int2b1 h'xxxx xxxx r 32 intc h'ffd4 0048 individual module interrupt source registers 2 int2b2 h'xxxx xxxx r 32 intc h'ffd4 004c individual module interrupt source registers 3 int2b3 h'xxxx xxxx r 32 intc h'ffd4 0050 individual module interrupt source registers 4 int2b4 h'xxxx xxxx r 32 intc h'ffd4 0054 individual module interrupt source registers 5 int2b5 h'xxxx xxxx r 32 intc h'ffd4 0058 individual module interrupt source registers 6 int2b6 h'xxxx xxxx r 32 intc h'ffd4 005c individual module interrupt source registers 7 int2b7 h'xxxx xxxx r 32 intc h'ffd4 0060 to h'ffd4 007f reserved (32 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1243 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffd4 0080 interrupt mask register 2 intmsk2 h'ff00 0000 r/w 32 intc h'ffd4 0084 interrupt mask clear register 2 intmskclr2 h'0000 0000 r/w 32 intc h'ffd4 0088 to h'ffd4 008f reserved (8 bytes) ? ? ? ? ? h'ffd4 0090 gpio interrupt set register int2gpic h'0000 0000 r/w 32 intc h'ffd4 0094 to h'ffd7 ffff reserved (261,996 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffd8 0000 timer output control register tocr h'00 r/w 8 tmu h'ffd8 0004 timer start register 0 tstr0 h'00 r/w 8 tmu h'ffd8 0008 timer constant register 0 tcor0 h'ffff ffff r/w 32 tmu h'ffd8 000c timer counter 0 tcnt0 h'ffff ffff r/w 32 tmu h'ffd8 0010 timer control register 0 tcr0 h'0000 r/w 16 tmu h'ffd8 0014 timer constant register 1 tcor1 h'ffff ffff r/w 32 tmu h'ffd8 0018 timer counter 1 tcnt1 h'ffff ffff r/w 32 tmu h'ffd8 001c timer control register 1 tcr1 h'0000 r/w 16 tmu h'ffd8 0020 timer constant register 2 tcor2 h'ffff ffff r/w 32 tmu h'ffd8 0024 timer counter 2 tcnt2 h'ffff ffff r/w 32 tmu h'ffd8 0028 timer control register 2 tcr2 h'0000 r/w 16 tmu h'ffd8 002c input capture register 2 tcpr2 h'xxxx xxxx r 32 tmu h'ffd8 0030 to h'ffdb ffff reserved (262,096 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1244 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffdc 0000 reserved (4 bytes) ? ? ? ? ? h'ffdc 0004 timer start register 1 tstr1 h'00 r/w 8 tmu h'ffdc 0008 timer constant register 3 tcor3 h'ffff ffff r/w 32 tmu h'ffdc 000c timer counter 3 tcnt3 h'ffff ffff r/w 32 tmu h'ffdc 0010 timer control register 3 tcr3 h'0000 r/w 16 tmu h'ffdc 0014 timer constant register 4 tcor4 h'ffff ffff r/w 32 tmu h'ffdc 0018 timer counter 4 tcnt4 h'ffff ffff r/w 32 tmu h'ffdc 001c timer control register 4 tcr4 h'0000 r/w 16 tmu h'ffdc 0020 timer constant register 5 tcor5 h'ffff ffff r/w 32 tmu h'ffdc 0024 timer counter 5 tcnt5 h'ffff ffff r/w 32 tmu h'ffdc 0028 timer control register 5 tcr5 h'0000 r/w 16 tmu h'ffdc 002a to h'ffdf ffff reserved (262,102 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffe0 0000 serial mode register 0 scsmr0 h'0000 r/w 16 scif h'ffe0 0004 bit rate register 0 scbrr0 h'ff r/w 8 scif h'ffe0 0008 serial control register 0 scscr0 h'0000 r/w 16 scif h'ffe0 000c transmit fifo data register 0 scftdr0 h'xx w 8 scif h'ffe0 0010 serial status register 0 scfsr0 h'0060 r/w 16 scif h'ffe0 0014 receive fifo data register 0 scfrdr0 h'xx r 8 scif h'ffe0 0018 fifo control register 0 scfcr0 h'0000 r/w 16 scif h'ffe0 001c transmit fifo data count register 0 sctfdr0 h'0000 r 16 scif h'ffe0 0020 receive fifo data count register 0 scrfdr0 h'0000 r 16 scif h'ffe0 0024 serial port register 0 scsptr0 h'000x r/w 16 scif h'ffe0 0028 line status register 0 sclsr0 h'0000 r/w 16 scif h'ffe0 002c serial error register 0 screr0 h'0000 r 16 scif h'ffe0 002e to h'ffe0 ffff reserved (65,490 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1245 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe1 0000 serial mode register 1 scsmr1 h'0000 r/w 16 scif h'ffe1 0004 bit rate register 1 scbrr1 h'ff r/w 8 scif h'ffe1 0008 serial control register 1 scscr1 h'0000 r/w 16 scif h'ffe1 000c transmit fifo data register 1 scftdr1 h'xx w 8 scif h'ffe1 0010 serial status register 1 scfsr1 h'0060 r/w * 16 scif h'ffe1 0014 receive fifo data register 1 scfrdr1 h'xx r 8 scif h'ffe1 0018 fifo control register 1 scfcr1 h'0000 r/w 16 scif h'ffe1 001c transmit fifo data count register 1 sctfdr1 h'0000 r 16 scif h'ffe1 0020 receive fifo data count register 1 scrfdr1 h'0000 r 16 scif h'ffe1 0024 serial port register 1 scsptr1 h'00xx r/w 16 scif h'ffe1 0028 line status register 1 sclsr1 h'0000 r/w 16 scif h'ffe1 002c serial error register 1 screr1 h'0000 r 16 scif h'ffe1 002e to h'ffe1 ffff reserved (65,490 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1246 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe2 0000 mode register simdr h'8000 r/w 16 siof h'ffe2 0002 clock select register siscr h'c000 r/w 16 siof h'ffe2 0004 transmit data assign register sitdar h'0000 r/w 16 siof h'ffe2 0006 receive data assign register sirdar h'0000 r/w 16 siof h'ffe2 0008 control data assign register sicdar h'0000 r/w 16 siof h'ffe2 000c control register sictr h'0000 r/w 16 siof h'ffe2 0010 fifo control register sifctr h'1000 r/w 16 siof h'ffe2 0014 status register sistr h'0000 r/w 16 siof h'ffe2 0016 interrupt enable register siier h'0000 r/w 16 siof h'ffe2 0018 to h'ffe2 001f reserved (8 bytes) ? ? ? ? ? h'ffe2 0020 transmit data register sitdr h'xxxx xxxx w 32 siof h'ffe2 0024 receive data register sirdr h'xxxx xxxx r 32 siof h'ffe2 0028 transmit control data register sitcr h'0000 0000 r/w 32 siof h'ffe2 002c receive control data register sircr h'xxxx xxxx r/w 32 siof h'ffe2 002c to h'ffe2 ffff reserved (65,492 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1247 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe3 0000 configuration register cmtcfg h'0000 0000 r/w 32 cmt h'ffe3 0004 free-running timer cmtfrt h'0000 0000 r 32 cmt h'ffe3 0008 control register cmtctl h'0000 0000 r/w 32 cmt h'ffe3 000c irq status register cmtirqs h'0000 0000 r/w 32 cmt h'ffe3 0010 channel 0 time register cmtch0t h'0000 0000 r/w 32 cmt h'ffe3 0014 channel 1 time register cmtch1t h'0000 0000 r/w 32 cmt h'ffe3 0018 channel 2 time register cmtch2t h'0000 0000 r/w 32 cmt h'ffe3 001c channel 3 time register cmtch3t h'0000 0000 r/w 32 cmt h'ffe3 0020 channel 0 stop time register cmtch0st h'0000 0000 r/w 32 cmt h'ffe3 0024 channel 1 stop time register cmtch1st h'0000 0000 r/w 32 cmt h'ffe3 0028 to h'ffe3 002f reserved (8 bytes) ? ? ? ? ? h'ffe3 0030 channel 0 timer/counter cmtch0c h'0000 0000 r/w 32 cmt h'ffe3 0034 channel 1 timer/counter cmtch1c h'0000 0000 r/w 32 cmt h'ffe3 0038 channel 2 timer/counter cmtch2c h'0000 0000 r/w 32 cmt h'ffe3 003c channel 3 timer/counter cmtch3c h'0000 0000 r/w 32 cmt h'ffe3 0040 to h'ffe4 5fff reserved (90,048 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1248 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe4 6000 to h'ffe4 6007 reserved (8 bytes) ? ? ? ? ? h'ffe4 6008 control and status register haccr h'0000 0200 r/w 32 hac h'ffe4 600c to h'ffe4 601f reserved (20 bytes) ? ? ? ? ? h'ffe4 6020 command/status address register haccsar h'0000 0000 r/w 32 hac h'ffe4 6024 command/status data register haccsdr h'0000 0000 r/w 32 hac h'ffe4 6028 pcm left channel register hacpcml h'0000 0000 r/w 32 hac h'ffe4 602c pcm right channel register hacpcmr h'0000 0000 r/w 32 hac h'ffe4 6030 to h'ffe4 604f reserved (32 bytes) ? ? ? ? ? h'ffe4 6050 tx interrupt enable register hactier h'0000 0000 r/w 32 hac h'ffe4 6054 tx status register hactsr h'f000 0000 r/w 32 hac h'ffe4 6058 rx interrupt enable register hacrier h'0000 0000 r/w 32 hac h'ffe4 605c rx status register hacrsr h'0000 0000 r/w 32 hac h'ffe4 6060 hac control register hacacr h'8400 0000 r/w 32 hac h'ffe4 6064 to h'ffe4 ffff reserved (40,860 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffe5 0000 control register spcr h'0000 0000 r/w 32 hspi h'ffe5 0004 status register spsr h'xxxx xx20 r 32 hspi h'ffe5 0008 system control register spscr h'0000 0040 r/w 32 hspi h'ffe5 000c transmit buffer register sptbr h'0000 0000 r/w 32 hspi h'ffe5 0010 receive buffer register sprbr h'0000 0000 r 32 hspi h'ffe5 0014 to h'ffe5 ffff reserved (65,516 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1249 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe6 0000 command register 0 cmdr0 h'00 r/w 8 mmcif h'ffe6 0001 command register 1 cmdr1 h'00 r/w 8 mmcif h'ffe6 0002 command register 2 cmdr2 h'00 r/w 8 mmcif h'ffe6 0003 command register 3 cmdr3 h'00 r/w 8 mmcif h'ffe6 0004 command register 4 cmdr4 h'00 r/w 8 mmcif h'ffe6 0005 command register 5 cmdr5 h'00 r 8 mmcif h'ffe6 0006 command start register cmdstrt h'00 r/w 8 mmcif h'ffe6 000a operation control register opcr h'00 r/w 8 mmcif h'ffe6 000b card status register cstr h'0x r 8 mmcif h'ffe6 000c interrupt control register 0 intcr0 h'00 r/w 8 mmcif h'ffe6 000d interrupt control register 1 intcr1 h'00 r/w 8 mmcif h'ffe6 000e interrupt status register 0 intstr0 h'00 r/w 8 mmcif h'ffe6 000f interrupt status register 1 intstr1 h'00 r/w 8 mmcif h'ffe6 0010 transfer clock control register clkon h'00 r/w 8 mmcif h'ffe6 0011 command timeout control register ctocr h'00 r/w 8 mmcif h'ffe6 0014 transfer byte number count register tbcr h'00 r/w 8 mmcif h'ffe6 0016 mode register moder h'00 r/w 8 mmcif h'ffe6 0018 command type register cmdtyr h'00 r/w 8 mmcif h'ffe6 0019 response type register rsptyr h'00 r/w 8 mmcif h'ffe6 001a transfer block number counter tbncr h'0000 r/w 16 mmcif h'ffe6 001c reserved (4 bytes) ? ? ? ? ? h'ffe6 0020 response register 0 rspr0 h'00 r/w 8 mmcif h'ffe6 0021 response register 1 rspr1 h'00 r/w 8 mmcif h'ffe6 0022 response register 2 rspr2 h'00 r/w 8 mmcif h'ffe6 0023 response register 3 rspr3 h'00 r/w 8 mmcif h'ffe6 0024 response register 4 rspr4 h'00 r/w 8 mmcif h'ffe6 0025 response register 5 rspr5 h'00 r/w 8 mmcif h'ffe6 0026 response register 6 rspr6 h'00 r/w 8 mmcif
appendix rev.1.00 dec. 13, 2005 page 1250 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe6 0027 response register 7 rspr7 h'00 r/w 8 mmcif h'ffe6 0028 response register 8 rspr8 h'00 r/w 8 mmcif h'ffe6 0029 response register 9 rspr9 h'00 r/w 8 mmcif h'ffe6 002a response register 10 rspr10 h'00 r/w 8 mmcif h'ffe6 002b response register 11 rspr11 h'00 r/w 8 mmcif h'ffe6 002c response register 12 rspr12 h'00 r/w 8 mmcif h'ffe6 002d response register 13 rspr13 h'00 r/w 8 mmcif h'ffe6 002e response register 14 rspr14 h'00 r/w 8 mmcif h'ffe6 002f response register 15 rspr15 h'00 r/w 8 mmcif h'ffe6 0030 response register 16 rspr16 h'00 r/w 8 mmcif h'ffe6 0031 crc status register rsprd h'00 r/w 8 mmcif h'ffe6 0032 data timeout register dtoutr h'ffff r/w 16 mmcif h'ffe6 0034 to h'ffe6 003f reserved (12 bytes) ? ? ? ? ? h'ffe6 0040 data register dr h'xxxx r/w 16 mmcif h'ffe6 0042 fifo pointer clear register fifoclr h'00 w 8 mmcif h'ffe6 0044 dma control register dmacr h'00 r/w 8 mmcif h'ffe6 0046 interrupt control register 2 intcr2 h'00 r/w 8 mmcif h'ffe6 0048 interrupt status register 2 intstr2 h'0x r/w 8 mmcif h'ffe6 0049 to h'ffe6 ffff reserved (65,463 bytes) ? ? ? ? ? physical address register name abbreviation initial value r/w access size module h'ffe7 0000 control register ssicr h'0000 0000 r/w 32 ssi h'ffe7 0004 status register ssisr h'0200 0003 r/w 32 ssi h'ffe7 0008 transmit data register ssitdr h'0000 0000 r/w 32 ssi h'ffe7 000c receive data register ssirdr h'0000 0000 r 32 ssi h'ffe7 0010 to h'ffe7 ffff reserved (65,520 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1251 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe8 0000 64 hz counter r64cnt h'xx r 8 rtc h'ffe8 0004 second counter rseccnt h'xx r/w 8 rtc h'ffe8 0008 minute counter rmincnt h'xx r/w 8 rtc h'ffe8 000c hour counter rhrcnt h'xx r/w 8 rtc h'ffe8 0010 day-of-week counter rwkcnt h'xx r/w 8 rtc h'ffe8 0014 day counter rdaycnt h'xx r/w 8 rtc h'ffe8 0018 month counter rmoncnt h'xx r/w 8 rtc h'ffe8 001c year counter ryrcnt h'xxxx r/w 16 rtc h'ffe8 0020 second alarm regist er rsecar h'xx r/w 8 rtc h'ffe8 0024 minute alarm register rminar h'xx r/w 8 rtc h'ffe8 0028 hour alarm regi ster rhrar h'xx r/w 8 rtc h'ffe8 002c day-of-week alarm register rwkar h'xx r/w 8 rtc h'ffe8 0030 day alarm regist er rdayar h'xx r/w 8 rtc h'ffe8 0034 month alarm register rmonar h'xx r/w 8 rtc h'ffe8 0038 rtc control regist er 1 rcr1 h'xx r/w 8 rtc h'ffe8 003c rtc control register 2 rcr2 h'x9 r/w 8 rtc h'ffe8 003d to h'ffe8 004f reserved (19 bytes) ? ? ? ? ? h'ffe8 0050 rtc control register 3 rcr3 h'x0 r/w 8 rtc h'ffe8 0054 year alarm regist er ryrar h'xxxx r/w 16 rtc h'ffe8 0056 to h'ffe8 ffff reserved (65,450 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1252 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffe9 0000 common control register flcmncr h'0000 0000 r/w 32 flctl h'ffe9 0004 command control register flcmdcr h'0000 0000 r/w 32 flctl h'ffe9 0008 command code register flcmcdr h'0000 0000 r/w 32 flctl h'ffe9 000c address register fladr h'0000 0000 r/w 32 flctl h'ffe9 0010 data register fldatar h'0000 0000 r/w 32 flctl h'ffe9 0014 data counter register fldtcntr h'0000 0000 r/w 32 flctl h'ffe9 0018 interrupt dma control register flintdmacr h'0000 0000 r/w 32 flctl h'ffe9 001c ready busy timeout setting register flbsytmr h'0000 0000 r/w 32 flctl h'ffe9 0020 ready busy timeout counter flbsycnt h'0000 0000 r 32 flctl h'ffe9 0024 data fifo register fl dtfifo h'xxxx xxxx r/w 32 flctl h'ffe9 0028 control code fifo register flecfifo h'xxxx xxxx r/w 32 flctl h'ffe9 002c transfer control register fltrcr h'00 r/w 8 flctl h'ffe9 002d to h'ffe9 ffff reserved (65,491 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1253 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffea 0000 port a control register pacr h'0000 r/w 16 gpio h'ffea 0002 port b control register pbcr h'0000 r/w 16 gpio h'ffea 0004 port c control register pccr h'0000 r/w 16 gpio h'ffea 0006 port d control register pdcr h'0000 r/w 16 gpio h'ffea 0008 port e control register pecr h'3000 r/w 16 gpio h'ffea 000a port f control register pfcr h'0000 r/w 16 gpio h'ffea 000c port g control register pgcr h'0000 r/w 16 gpio h'ffea 000e port h control register phcr h'ffff r/w 16 gpio h'ffea 0010 port j control register pjcr h'ffff r/w 16 gpio h'ffea 0012 port k control register pkcr h'ffff r/w 16 gpio h'ffea 0014 port l control register plcr h'ffff r/w 16 gpio h'ffea 0016 port m control register pmcr h'ffff r/w 16 gpio h'ffea 0018 to h'ffea 001f reserved (8 bytes) ? ? ? ? ? h'ffea 0020 port a data register padr h'00 r/w 8 gpio h'ffea 0022 port b data register pbdr h'00 r/w 8 gpio h'ffea 0024 port c data register pcdr h'00 r/w 8 gpio h'ffea 0026 port d data register pddr h'00 r/w 8 gpio h'ffea 0028 port e data register pedr h'x0 r/w 8 gpio h'ffea 002a port f data register pfdr h'00 r/w 8 gpio h'ffea 002c port g data register pgdr h'00 r/w 8 gpio h'ffea 002e port h data register phdr h'xx r/w 8 gpio h'ffea 0030 port j data register pjdr h'xx r/w 8 gpio h'ffea 0032 port k data regist er pkdr h'xx r/w 8 gpio h'ffea 0034 port l data register pldr h'00 r/w 8 gpio h'ffea 0036 port m data register pmdr h'0x r/w 8 gpio h'ffea 0037 to h'ffea 0047 reserved (17 bytes) ? ? ? ? ? h'ffea 0048 port e pull-up control register pepupr h'ff r/w 8 gpio h'ffea 0049 to h'ffea 004d reserved (5 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1254 of 1286 rej09b0158-0100 physical address register name abbreviation initial value r/w access size module h'ffea 004e port h pull-up control register phpupr h'ff r/w 8 gpio h'ffea 0050 port j pull-up control register pjpupr h'ff r/w 8 gpio h'ffea 0052 port k pull-up control register pkpupr h'ff r/w 8 gpio h'ffea 0056 port m pull-up control register pmpupr h'ff r/w 8 gpio h'ffea 0057 to h'ffea 005f reserved (9 bytes) ? ? ? ? ? h'ffea 0060 input pin pull-up control register 1 ppupr1 h'ffff r/w 16 gpio h'ffea 0062 input pin pull-up control register 2 ppupr2 h'ffff r/w 16 gpio h'ffea 0064 to h'ffea 007f reserved (28 bytes) ? ? ? ? ? h'ffea 0080 on-chip module select register omselr h'0000 r/w 16 gpio h'ffea 0082 to h'ffff ffff reserved (1,441,662 bytes) ? ? ? ? ?
appendix rev.1.00 dec. 13, 2005 page 1255 of 1286 rej09b0158-0100 e. package dimensions 1 3 75 9 11 15 13 17 2 64 8 10 14 12 16 19 18 20 21 23 25 22 24 a c e g j l n r u b d f h k m p t w v y ae ad ac ab aa 0.30 c b 21.00 0.30 c a 0.08 m cb a b 0.20 21.00 (index) 0.80 4 449 0.50 0.05 0.4 0.05 2.0 max 0.15 c 0.35 c 0.90 0.90 c a 0.80 unit : mm prbg0449ga-a p-fbga449-21x21-0.80 renesas code jeita code figure e.1 package dimensions (449-pin bga) note: the tj (junction temperature) of this lsi becomes over 125 c if operating with the maximum power consumption. so a careful ther mal design is necessary. use a heat sink or forced air cooling to lower the tj.
appendix rev.1.00 dec. 13, 2005 page 1256 of 1286 rej09b0158-0100 f. mode pin settings the mode8?mode0 pin values are input in the event of a power-on reset via the preset pin. [legend] h: high level input l: low level input table f.1 clock operating modes with external pin combination pin value frequency (vs. input clock) clock operating mode mode 7, 2 mode 1 mode 0 pll1 pll2 cpu clock (ick) super- hyway clock (shck) peripheral clock (pck) ddr clock (ddrck) bus clock (bck) frqcr initial value 0 l on 12 6 3/2 24/5 3 h'1023 3335 1 l h on 12 6 1 24/5 2 h'1024 4336 2 l on 12 6 3/2 24/5 3/2 h'1025 5335 3 ll h h on 12 6 1 24/5 1 h'1026 6336 12 hh l l on 12 4 1 4 2 h'1044 4346 table f.2 area 0 memory map and bus width pin value mode4 mode3 memory interface bus width l l mpx interface 32 bits h sram interface 8 bits h l sram interface 16 bits h sram interface 32 bits table f.3 endian pin value mode5 endian l big endian h little endian
appendix rev.1.00 dec. 13, 2005 page 1257 of 1286 rej09b0158-0100 table f.4 pci mode pin value mode6 pcic operation mode l pcic normal (non-host) h pci host bus bridge table f.5 clock input pin value mode8 clock input l external input clock h crystal resonator table f.6 mode control pin value mpmd mode l emulation support mode h lsi operation mode note: when using emulation support mode, refe r to the emulator manual of the sh7780.
appendix rev.1.00 dec. 13, 2005 page 1258 of 1286 rej09b0158-0100 g. pin functions g.1 pin states table g.1 pin states in reset, power- down state, and bus-released state reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release a[25:0] a[25:0] lbsc o pz * 1 pz/z o ? pz/z d[31:24] d[31:24] (default) lbsc i/o z pz/z pz/z ? pz/z portf[7:0] gpio i/o ? pi/i/o pi/i/o ? pi/i/o d[23:16] d[23:16] (default) lbsc i/o z pz/z pz/z ? pz/z port g[7:0] gpio i/o ? pi/i/o pi/i/o ? pi/i/o d[15:0] d[15:0] lbsc i/o z pz/z pz/z ? pz/z cs[2:0] , cs[6:4] cs[2:0] , cs[6:4] lbsc o h h o ? pz/z back port m0 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o back lbsc o ? h o ? o breq port m1 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o breq lbsc i ? i i ? i bs bs lbsc o h h o ? pz/z r/ w r/ w lbsc o h h o ? pz/z rd / frame rd / frame lbsc o h o o ? pz/z/o rdy rdy lbsc i z pi/i pi/i ? pi/i we0 / reg we0 / reg lbsc o h o o ? pz/z/o we1 we1 lbsc o h o o ? pz/z/o we2 / iord we2 / iord lbsc o h o o ? pz/z/o we3 / iowr we3 / iowr lbsc o h o o ? pz/z/o dack0 /mode0 mode0 (por) cpg i i ? ? ? ? port l3 * 3 (default) gpio o ? o o ? o dack0 dmac o ? o o k o
appendix rev.1.00 dec. 13, 2005 page 1259 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release dack1 /mode1 mode1 (por) cpg i i ? ? ? ? port l2 * 3 (default) gpio o ? o o ? o dack1 dmac o ? o o k o port k3 (default) gpio i/o pi * 2 i/o i/o ? i/o dack2 dmac o ? o o k o dack2 / mresetout / audata2 mresetout reset o ? l o ? o audata2 h-udi o ? o o ? o port k2 (default) gpio i/o pi * 2 i/o i/o ? i/o dack3 / irqout / audata3 dack3 dmac o ? o o k o irqout intc o ? o o ? o audata3 h-udi o ? o o ? o drak0 /mode2 mode2 (por) cpg i i ? ? ? ? port l1 * 3 (default) gpio o ? o o ? o drak0 dmac o ? o o k o drak1 /mode7 mode7 (por) cpg i i ? ? ? ? port l0 * 3 (default) gpio o ? o o ? o drak1 dmac o ? o o k o drak2 / ce2a / audck port k1 * 3 (default) gpio o o o o ? o drak2 dmac o ? o o k o ce2a lbsc o ? o o ? pz/z audck h-udi o ? o o ? o drak3 / ce2b / audsync port k0 * 3 (default) gpio o o o o ? o drak3 dmac o ? o o k o ce2b lbsc o ? o o ? pz/z audsync h-udi o ? o o ? o
appendix rev.1.00 dec. 13, 2005 page 1260 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release dreq0 port k7 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o dreq0 dmac i ? pz/z pi/i pz/z pi/i dreq1 port k6 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o dreq1 dmac i ? pz/z pi/i pz/z pi/i port k5 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o dreq2 / intb / audata0 dreq2 dmac i ? pz/z pi/i pz/z pi/i intb pcic i ? pi/i pi/i ? pi/i audata0 h-udi o ? o o ? o port k4 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o dreq3 / intc / audata1 dreq3 dmac i ? pz/z pi/i pz/z pi/i intc pcic i ? pi/i pi/i ? pi/i audata1 h-udi o ? o o ? o mclk mclk ddrif o o o o ? o mclk mclk ddrif o o o o ? o mdqs[3:0] mdqs[3 :0] ddrif i/o z z i/o ? i/o mdqm[3:0] mdqm[3:0] ddrif o h h o ? o mda[31:0] mda[31:0] ddrif i/o z z i/o ? i/o cke cke ddrif o o o o ? o mcas mcas ddrif o h h o ? o mras mras ddrif o h h o ? o mcs mcs ddrif o h h o ? o mwe mwe ddrif o h h o ? o ma[13:0] ma[13:0] ddrif o l l o ? o ba[1:0] ba[1:0] ddrif o l l o ? o bkprst bkprst ddrif i pi pi pi ? pi
appendix rev.1.00 dec. 13, 2005 page 1261 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release ad [31:24] ad[31:24] (default) pcic i/o z i/o i/o ? i/o port a[7:0] gpio i/o ? i/o i/o ? i/o ad [23:16] ad[23:16] (default) pcic i/o z i/o i/o ? i/o port b[7:0] gpio i/o ? i/o i/o ? i/o ad [15:8] ad[15:8] (default) pcic i/o z i/o i/o ? i/o port c[7:0] gpio i/o ? i/o i/o ? i/o ad [7:0] ad[7:0] (def ault) pcic i/o z i/o i/o ? i/o port d[7:0] gpio i/o ? i/o i/o ? i/o cbe [3:0] cbe[3:0] pcic i/o z i/o i/o ? i/o gnt0 / gntin gnt0 / gntin pcic i/o pz pi/o pi/o ? pi/o gnt[3:1] gnt[3:1] (default) pcic o pz o o ? o port e0-e2 gpio i/o ? pi/o pi/o ? pi/o req0 / reqout req0 / reqout pcic i/o pz i/o i/o ? i/o req[3:1] req[3:1] (default) pcic i pz pi pi ? pi port e3-e5 gpio i/o pz pi/o pi/o ? pi/o devsel devsel pcic i/o pz pi/o pi/o ? pi/o pciframe pciframe pcic i/o pz pi/o pi/o ? pi/o idsel idsel pcic i pz pi pi ? pi inta inta pcic i/o pz pi/o pi/o ? pi/o irdy irdy pcic i/o pz pi/o pi/o ? pi/o lock lock pcic i/o pz pi/o pi/o ? pi/o par par pcic i/o z i/o i/o ? i/o pciclk pciclk pcic i i i i ? i pcireset pcireset pcic o l k k ? o perr perr pcic i/o pz pi/o pi/o ? pi/o
appendix rev.1.00 dec. 13, 2005 page 1262 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release serr serr pcic i/o pz pi/o pi/o ? pi/o stop stop pcic i/o pz pi/o pi/o ? pi/o trdy trdy pcic i/o pz pi/o pi/o ? pi/o clkout clkout cpg o o z/o z/o ? z/o preset preset reset i i i i ? i extal extal cpg i i i i ? i xtal xtal cpg o o o o ? o status0/ cmt_ctr0 status0 (default) reset o h h l ? o cmt_ctr0 cmt i/o ? pz/o i/o k pi/i/o status1/ cmt_ctr1 status1 (default) reset o h h h ? o cmt_ctr1 cmt i/o ? pz/o i/o k pi/i/o irq/ irl[3:0] irq/ irl[3:0] intc i pi * 2 pi/i pi/i ? pi/i mode3 (por) lbsc i i ? ? ? ? irq/ irl4 /fd4/ mode3 irq/ irl4 (default) intc i ? i i ? i fd4 flctl i/o ? i/o i/o k i/o mode4 (por) lbsc i i ? ? ? ? irq/ irl5 /fd5/ mode4 irq/ irl5 (default) intc i ? i i ? i fd5 flctl i/o ? i/o i/o k i/o mode6 (por) pcic i i ? ? ? ? irq/ irl6 /fd6/ mode6 irq/ irl6 (default) intc i ? i i ? i fd6 flctl i/o ? z i/o k i/o irq/ irl7 /fd7 port e6 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o irq/ irl7 intc i ? pi/i pi/i ? pi/i fd7 flctl i/o ? i/o pi/i/o k pi/i/o nmi nmi intc i pi * 2 pi/i pi/i ? pi/i
appendix rev.1.00 dec. 13, 2005 page 1263 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release scif0_cts / intd /fcle port h1 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif0_cts scif i/o ? pi/i/o pi/i/o k pi/i/o intd pcic i ? pi/i pi/i ? pi/i scif0_rts / hspi_cs / fse port h0 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif0_rts scif i/o ? pi/i/o pi/i/o k pi/i/o hspi_cs hspi i/o ? pi/i/o pi/i/o k pi/i/o fse flctl o ? o o k o scif0_rxd/ hspi_rx/frb port h2 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif_rxd scif i ? pi/i pi/i pz/z pi/i hspi_rx hspi i ? pi/i pi/i pz/z pi/i frb flctl i ? pi/i pi/i pz/z pi/i scif0_sck/ hspi_clk/ fre port h4 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif0_sck scif i/o ? pi/i pi/i/o k pi/i/o hspi_clk hspi i/o ? pi/i/o pi/i/o k pi/i/o fre flctl o ? o o k o mode8 (por) cpg i i ? ? ? ? scif0_txd/ hspi_tx/ fwe / mode8 port h3 * 3 (default) gpio o ? o o ? o scif0_txd scif o ? pz/z o k o hspi_tx hspi o ? pz/z o k o fwe flctl o ? pz/z o k o scif1_rxd/ mcdat port h5 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif1_rxd scif i ? pi/i pi/i pz/z pi/i mcdat mmcif i/o ? pi/i pi/i/o k pi/i/o
appendix rev.1.00 dec. 13, 2005 page 1264 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release scif1_sck/ mccmd port h7 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o scif1_sck scif i/o ? pi/i pi/i/o k pi/i/o mccmd mmcif i/o ? pi/i pi/i/o k pi/i/o mode5 (por) lbsc i i ? ? ? ? scif1_txd/ mcclk/mode5 port h6 * 3 (default) gpio o ? o o ? o scif1_txd scif o ? o o k o mcclk mmcif o ? o o k o port j2 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o siof_mclk/ hac_res siof_mclk siof i ? pi/i pi/i pz/z pi/i hac_res hac o ? o o k o port j4 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o siof_rxd siof i ? pi/i pi/i pz/z pi/i siof_rxd/ hac_sdin/ ssi_sck hac_sdin hac i ? pi/i pi/i pz/z pi/i ssi_sck ssi i/o ? pi/i pi/i/o k pi/i/o port j1 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o siof_sck siof i/o ? pi/i/o pi/i/o k pi/i/o siof_sck/ hac_bitclk/ ssi_clk hac_bitclk hac i ? pi/i pi/i pz/z pi/i ssi_clk ssi i/o ? pi/i pi/i/o k pi/i/o port j3 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o siof_sync siof i/o ? pi/i/o pi/i/o k pi/i/o siof_sync/ hac_sync/ ssi_ws hac_sync hac o ? o o k o ssi_ws ssi i/o ? pi/i pi/i/o k pi/i/o port j5 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o siof_txd siof o ? o o/z k o/z siof_txd/ hac_sdout/ ssi_sdata hac_sdout hac o ? o o k o ssi_sdata ssi i/o ? pi/i pi/i/o k pi/i/o
appendix rev.1.00 dec. 13, 2005 page 1265 of 1286 rej09b0158-0100 reset pin name (lsi level) pin name (module level) related module i/o power -on manual sleep module standby bus release tclk/ iois16 port j0 (default) gpio i/o pi * 2 pi/i/o pi/i/o ? pi/i/o tclk tmu i/o ? pi/i/o pi/i/o k pi/i/o iois16 lbsc i ? pi/i pi/i ? pi/i asebrk / brkack asebrk / brkack h-udi i/o pi pi/o pi/o ? pi/o tck tck tmu i pi pi pi ? pi trst trst h-udi i pi pi pi ? pi tdi tdi h-udi i pi pi pi ? pi tms tms h-udi i pi pi pi ? pi tdo tdo h-udi o o o o ? o audck/fale audck (default) h-udi o o o o ? o fale flctl o ? o o k o audsync/ fce audsync (default) h-udi o o o o ? o fce flctl o ? o o k o audata[3:0] (default) h-udi o o o o ? o audata[3:0]/ fd [3:0] fd[3:0] flctl i/o ? pi/i/o pi/i/o k pi/i/o mpmd mpmd h-udi i pi pi pi ? pi xrtcstbi xrtcstbi rtc i i i i ? i xtal2 xtal2 rtc o o o o ? o extal2 extal2 rtc i i i i ? i legend: ? : disabled (not selected) or not supported i: input o: output h: high level output l: low level output z: high impedance state pi: input and pulled up with a built-in pull-up resistance. pz: high impedance and pulled up with a built-in pull-up resistance. pi/i, pz/z etc.: depending on the register setting. refer to secti on 11, local bus state controller (lbsc), section 28, g eneral purpose i/o (gpio), and related module section. k: input is high impedance and output is held its state. por: power on reset
appendix rev.1.00 dec. 13, 2005 page 1266 of 1286 rej09b0158-0100 notes: 1. high impedance state until the internal clock is stable. 2. input state until the internal clock is stable. 3. do not input signals to these pins immediately after power-on reset because these initial states are port outputs.
appendix rev.1.00 dec. 13, 2005 page 1267 of 1286 rej09b0158-0100 g.2 handling of unused pins table g.2 treatment of unused pins pin name (lsi level) pin name (module level) module i/o when not in use a[25:0] a[25:0] lbsc o open d[31:24] d[31:24] (def ault) lbsc i/o open port f[7:0] gpio i/o d[23:16] d[23:16] (def ault) lbsc i/o open port g [7:0] gpio i/o d[15:8] d[15:8] lbsc i/o open d[7:0] d[7:0] lbsc i/o must be used cs[2:0] , cs[6:4] cs[2:0] , cs[6:4] lbsc o open back port m0 (default) gpio i/o open back lbsc o breq port m1 (default) gpio i/o open breq lbsc i bs bs lbsc o open r/ w r/ w lbsc o open rd / frame rd / frame lbsc o open rdy rdy lbsc i pulled-down to vssq * 1 we0 / reg we0 / reg lbsc o open we1 we1 lbsc o open we2 / iord we2 / iord lbsc o open we3 / iowr we3 / iowr lbsc o open dack0 /mode0 mode0 (por) cpg i must be used during power-on reset port l3 (default) gpio o open dack0 dmac o dack1 /mode1 mode1 (por) dmac i must be used during power-on reset port l2 (default) gpio o open dack1 dmac o
appendix rev.1.00 dec. 13, 2005 page 1268 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use port k3 (default) gpio i/o open dack2 / mresetout / audata2 dack2 dmac o mresetout reset o audata2 h-udi o port k2 (default) gpio i/o open dack3 / irqout / audata3 dack3 dmac o irqout intc o audata3 h-udi o drak0 /mode2 mode2 (por) cpg i must be used during power-on reset port l1 (default) gpio o open drak0 dmac o drak1 /mode7 mode7 (por) cpg i must be used during power-on reset port l0 (default) gpio o open drak1 dmac o drak2 / ce2a /audck port k1 (default) gpio o open drak2 dmac o ce2a lbsc o audck h-udi o port k0 (default) gpio o open drak3 / ce2b / audsync drak3 dmac o ce2b lbsc o audsync h-udi o dreq0 port k7 (default) gpio i/o open dreq0 dmac i dreq1 port k6 (default) gpio i/o open dreq1 dmac i
appendix rev.1.00 dec. 13, 2005 page 1269 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use port k5 (default) gpio i/o open dreq2 / intb / audata0 dreq2 dmac i intb pcic i audata0 h-udi o port k4 (default) gpio i/o open dreq3 / intc / audata1 dreq3 dmac i intc pcic i audata1 h-udi o mclk mclk ddrif o open mclk mclk ddrif o open mdqs[3:0] mdqs[3:0] ddrif i/o open mdqm[3:0] mdqm[3:0] ddrif o open mda[31:0] mda[31:0] ddrif i/o open cke cke ddrif o open mcas mcas ddrif o open mras mras ddrif o open mcs mcs ddrif o open mwe mwe ddrif o open ma[13:0] ma[13:0] ddrif o open ba[1:0] ba[1:0] ddrif o open bkprst bkprst ddrif i pulled-up to vccq-ddr ad[31:24] ad[31:24] ( default) pcic i/o open port a[7:0] gpio i/o ad[23:16] ad[23:16] ( default) pcic i/o open port b[7:0] gpio i/o ad[15:8] ad[15:8] ( default) pcic i/o open port c[7:0] gpio i/o ad[7:0] ad[7:0] (default) pcic i/o open port d[7:0] gpio i/o
appendix rev.1.00 dec. 13, 2005 page 1270 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use cbe[3:0] cbe[3:0] pcic i/o open gnt0 / gntin gnt0 / gntin pcic i/o open gnt[3:1] gnt[3:1] (default) pcic o open port e0-e2 gpio i/o req0 / reqout req0 / reqout pcic i/o open req[3:1] req[3:1] (default) pcic i open port e3-e5 gpio i/o devsel devsel pcic i/o open pciframe pciframe pcic i/o open idsel idsel pcic i pulled-down to vssq inta inta pcic i/o pulled-up to vddq irdy irdy pcic i/o open lock lock pcic i/o open par par pcic i/o open pciclk pciclk pcic i fixed to vssq pcireset pcireset pcic o open perr perr pcic i/o open serr serr pcic i/o pulled-up to vddq stop stop pcic i/o open trdy trdy pcic i/o open clkout clkout cpg o open preset preset reset i must be used during power-on reset extal extal cpg i must be used xtal xtal cpg o open status0/cmt_ctr0 status 0 (default) reset o open cmt_ctr0 cmt i/o open status1/cmt_ctr1 status 1 (default) reset o open cmt_ctr1 cmt i/o open irq/ irl[3:0] irq/ irl[3:0] intc i pulled-up to vddq
appendix rev.1.00 dec. 13, 2005 page 1271 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use irq/ irl4 /fd4/mode3 mode3 (por) lbsc i must be used during power-on reset irq/ irl4 (default) intc i pulled-up to vddq fd4 flctl i/o irq/ irl5 /fd5/mode4 mode4 (por) lbsc i must be used during power-on reset irq/ irl5 (default) intc i pulled-up to vddq fd5 flctl i/o irq/ irl6 /fd6/mode6 mode6 (por) pcic i must be used during power-on reset irq/ irl6 (default) intc i pulled-up to vddq fd6 flctl i/o irq/ irl7 /fd7 port e6 (default) gpio i/o open irq/ irl7 intc i fd7 flctl i/o nmi nmi intc i pulled-up to vddq port h1 (default) gpio i/o open scif0_cts / intd / fcle scif0_cts scif i intd pcic i port h0 (default) gpio i/o open scif0_rts / hspi_cs / fse scif0_rts scif o hspi_cs hspi i/o fse flctl o port h2 (default) gpio i/o open scif0_rxd/hspi_rx/ frb scif0_rxd scif i hspi_rx hspi i frb flctl i
appendix rev.1.00 dec. 13, 2005 page 1272 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use port h4 (default) gpio i/o open scif0_sck/hspi_clk / fre scif0_sck scif i/o hspi_clk hspi i/o fre flctl o mode8 (por) cpg i must be used during power-on reset scif0_txd/hspi_tx/ fwe /mode8 port h3 (default) gpio o open scif0_txd scif o hspi_tx hspi o fwe flctl o scif1_rxd/mcdat port h5 (default) gpio i/o open scif1_rxd scif i mcdat mmcif i/o scif1_sck/mccmd port h7 (default) gpio i/o open scif1_sck scif i/o mccmd mmcif i/o scif1_txd/mcclk/ mode5 mode5 (por) lbsc i must be used during power-on reset port h6 (default) gpio o open scif1_txd scif o mcclk mmcif o port j2 (default) gpio i/o open siof_mclk/ hac_res siof_mclk siof i hac_res hac o port j4 (default) gpio i/o open siof_rxd/hac_sdin/ ssi_sck siof_rxd siof i hac_sdin hac i ssi_sck ssi i/o
appendix rev.1.00 dec. 13, 2005 page 1273 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use port j1 (default) gpio i/o open siof_sck/ hac_bitclk/ssi_clk siof_sck siof i/o hac_bitclk hac i ssi_clk ssi i/o port j3 (default) gpio i/o open siof_sync/ hac_sync/ssi_ws siof_sync siof i/o hac_sync hac o ssi_ws ssi i/o port j5 (default) gpio i/o open siof_txd/hac_ sdout/ssi_sdata siof_txd siof o hac_sdout hac o ssi_sdata ssi i/o tclk/ iois16 port j0 (default) gpio i/o open tclk tmu i/o iois16 lbsc i asebrk /brkack asebrk /brkack h-udi i/o open * 2 tck tck tmu i open * 2 trst trst h-udi i fixed to ground or connected to preset * 2 * 3 tdi tdi h-udi i open * 2 tms tms h-udi i open * 2 tdo tdo h-udi o open * 2 audck/fale audck (default) h-udi o open fale flctl o audsync/ fce audsync (default) h-udi o open fce flctl o audata[3:0]/fd[3:0] audata[3:0] (default) h-udi o open fd[3:0] flctl i/o
appendix rev.1.00 dec. 13, 2005 page 1274 of 1286 rej09b0158-0100 pin name (lsi level) pin name (module level) module i/o when not in use mpmd mpmd h-udi i pulled-up to vddq * 2 xrtcstbi xrtcstbi rtc i pulled-up to vdd-rtc xtal2 xtal2 rtc o open extal2 extal2 rtc i pulled-up to vdd-rtc notes: power must be supplied to each power supply pin, even when the function pin is not used. when the pin is not used, do not set the register for the pin. 1. this pin is pulled-up within this ls i after power-on reset. set the rdypup bit in ppupr1 (gpio) to 1 to pull-up off the rdy pin's pulled-up. 2. when using an emulator, follow the instruction from the emulator. 3. when not using emulator, the pin should be fixed to ground or connected to another pin which operates in the same manner as preset . however, when fixed to a ground pin, the following problem occurs. since the trst pin is pulled up within this lsi, a weak current flows when the pin is externally c onnected to ground pin. the value of the current is determined by a resistance of the pull-up mos for the port pin. although this current does not affect the operation of this lsi, it consumes unnecessary power.
appendix rev.1.00 dec. 13, 2005 page 1275 of 1286 rej09b0158-0100 h. turning on and off power supply ? turning on power supply ? there is no restriction for the order of th e power supply between each power supplies. within 300 ms after turning on a single power supply, turn on all the other power supplies. (except ddr-sdram power supply backup and rtc power supply backup) ? turning off power supply ? there is no restriction for the order of th e power supply between each power supplies. within 300 ms after turning off a single power supply, turn off all the other power supplies. (except ddr-sdram power supply backup and rtc power supply backup) turning on 0.1 v * min v * min 300 > t 0 [ms] v * min: vdd, vdd-pll1 to 3, vdd-dll1 to 2 = 1.15[v] vccq-ddr = 2.3[v] vddq, vdd-rtc = 3.0[v] turning off v * min 0.2[v] 300 > t 0 [ms] v * min: vdd, vdd-pll1 to 3, vdd-dll1 to 2 = 1.15[v] vccq-ddr = 2.3[v] vddq, vdd-rtc = 3.0[v] figure h.1 sequence of turning on and off power supply
appendix rev.1.00 dec. 13, 2005 page 1276 of 1286 rej09b0158-0100 i. version registers (pvr, prr) the sh7780 has the read-only registers which show the version of a processor core, and the version of a product. by using the value of these registers, it becomes possible to be able to distinguish the version and product of a processor from software, and to realize the scalability of the high system. since the values of the version registers differ for every product, please refer to the hardware manual or cont act renesas technology corp. note: the bit 7 to bit 0 of pvr register and the bit 3 to bit 0 of prr register should be masked by the software. table i.1 register configuration register name abbrev. r/w initial value p4 address area 7 address access size processor version register pvr r h'1020 0axx h'ff00 0030 h'1f00 0030 32 product register prr r h'000 0 092x h'ff00 0044 h'1f00 0044 32 [legend] x: undefined ? processor version register (pvr) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: version information version information 0001000000100000 initial value: rrrrrrrrrrrrrrrr r/w: bit: initial value: r/w: 1514131211109876543210 000010 rrrrrrr r 10 ? product register (prr) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: version information version information 0000000000000000 initial value: rrrrrrrrrrrrrrrr r/w: bit: initial value: r/w: 1514131211109876543210 000010 rrrrrrr r 0100 rrrr 10
appendix rev.1.00 dec. 13, 2005 page 1277 of 1286 rej09b0158-0100 j. part number list table j.1 sh7780 product lineup product name voltage operating frequency part number operating temperature package sh7780 1.25 v 400 mhz r8a77800adbg ? 40 to 85 c 449-pin bga R8A77800ADBGV 449-pin bga (lead free) r8a77800anbg ? 20 to 75 c 449-pin bga r8a77800anbgv 449-pin bga (lead free)
appendix rev.1.00 dec. 13, 2005 page 1278 of 1286 rej09b0158-0100
rev.1.00 dec. 13, 2005 page 1279 of 1286 rej09b0158-0100 index numerics 16-bit timer input capture ...................................... 697 output compare ................................. 699 32-bit address extended mode................ 188 32-bit timer input capture ...................................... 692 output compare ................................. 693 a address space identifier (asid)............. 155 address space of the ddrif.................. 404 address translation ................................. 155 addressing modes..................................... 53 alarm function....................................... 729 area ........................................................ 320 areas....................................................... 357 arithmetic operation instructions ............. 61 asid....................................................... 167 asynchronous serial communication mode.............................. 733 ati ......................................................... 730 audio codec interface (hac)................ 955 auto-reload count operation ................ 671 auto-request mode ................................ 588 b baud rate generator................................. 827 big endian................................................. 48 block diagram............................................ 9 branch instructions ................................... 65 break....................................................... 794 bri ......................................................... 793 burst mode.............................................. 599 burst mode ............................................. 599 burst rom interface............................... 370 bus arbitration........................................ 395 byte control sram interface ................ 389 c cacheability bit ....................................... 168 caches..................................................... 197 clock pulse generator (cpg) ................. 613 clocked synchronous serial communication mode.............................. 733 command access mode ....................... 1044 compare match timer (cmt)................ 677 control registers........................................ 34 crystal oscillato r circuit ........................ 730 cui ......................................................... 730 cycle-steal mode..................................... 597 d data address error ................................... 115 data alignment....................................... 406 data tlb miss exception................ 110, 180 data tlb multiple hit exception ............ 180 data tlb multiple-hit exception ............ 109 data tlb protection violation exception......................................... 113, 181 ddr-sdram interface (ddrif).......... 401 ddr-sdram power supply backup .... 650 delay slot .................................................. 51 delayed branches ...................................... 51 direct memory access controller (dmac).................................................. 557 dirty bit................................................... 169 division by zero...................................... 142 double-precision floating-point extended registers...................................... 38
rev.1.00 dec. 13, 2005 page 1280 of 1286 rej09b0158-0100 double-precision floating-point registers or single-precision floating-point registers.............................. 38 dual address mode.................................. 595 e effective address ...................................... 53 endian..................................................... 352 eri.......................................................... 793 exception flow........................................ 104 exception handling ................................... 97 exception/interrupt codes ....................... 102 execution cycles ....................................... 87 external memory space map ................. 322 external request mode ............................ 588 f fixed mode ............................................. 592 fixed-point transfer instructions............... 59 floating-point control instructions ........... 70 floating-point double-precision instructions ............................................... 70 floating-point graphics acceleration instructions ............................................... 71 floating-point re gisters....................... 35, 38 floating-point single-precision instructions ............................................... 69 fpu error ................................................ 142 fpu exception ........................................ 123 fpu exception handling ......................... 142 fpu exception sources........................... 142 g general fpu disable exception .............. 120 general fpu disable exceptions and slot fpu disable exceptions ............. 142 general illegal instruction exception ...... 118 general interrupt request......................... 125 general purpose i/o (gpio)................. 1055 general registers ....................................... 34 geometric operation instructions ............ 144 h hardware itlb miss handling................ 175 h-udi reset ............................................ 108 i i/o card interface .................................... 372 ic memory card interface ....................... 372 inexact exception .................................... 142 initial page write exception............. 112, 182 instruction address error ......................... 116 instruction execution state ........................ 49 instruction fetch cycle break................. 1122 instruction set............................................ 51 instruction tlb miss exception...... 111, 178 instruction tlb multiple hit exception... 177 instruction tlb multiple-hit exception .. 109 instruction tlb protection violation excep tion.......................... 114, 179 intermittent mode 16............................... 598 interrupt controller (intc) .................... 243 interrupt response time......................... 311 interrupts ticpi .................................................. 674 tuni................................................... 674 invalid operation ..................................... 142 irl interrupts ......................................... 297 irq interrupts ......................................... 296 issue rates.................................................. 87 itlb ....................................................... 170 itlb address array ................................. 184 itlb data array....................................... 185
rev.1.00 dec. 13, 2005 page 1281 of 1286 rej09b0158-0100 l l memory ............................................... 227 little endian.............................................. 48 load-store architecture ............................. 51 local bus state controller (lbsc) ........ 315 logic operation instructions ..................... 63 m manual reset ........................................... 108 master mode........................................... 397 memory management unit.............. 147, 320 memory-mapped registers ........................ 46 module standby state............................. 649 mpx interface ........................................ 383 multiple virtual memory mode ............... 155 n nmi (nonmaskable interrupt) ................. 124 nmi interrupt ......................................... 296 o on-chip module interrupts ..................... 299 on-chip peripheral module request mode........................................... 589 operand access cycle break .................. 1123 overflow................................................. 142 p p0, p3, and u0 areas ............................... 152 p1 area .................................................... 152 p2 area .................................................... 152 p4 area .................................................... 152 page size bits .......................................... 168 pair single-precision data transfer instructions ............................................. 145 pcmcia interface.................................. 372 pcmcia s upport.................................... 325 pipelining .................................................. 73 power-down mode......................... 428, 643 power-down state...................................... 49 power-on reset ........................................ 108 ppn ......................................................... 168 pre-execution user break/ post-execution user break........................ 122 prefetch instruction ................................. 238 pri .......................................................... 730 privileged mode ........................................ 34 processing modes...................................... 34 programming model.................................. 33 protection key data.................................. 168 r realtime clock (rtc) ............................ 707 registers bcr .................................................... 333 camr0............................................. 1114 camr1............................................. 1114 car0 ................................................ 1113 car1 ................................................ 1113 cbcr................................................ 1119 cbr0 ................................................ 1105 cbr1 ................................................ 1105 ccmfr............................................. 1118 ccr .................................................... 201 cdmr1............................................. 1116 cdr1 ................................................ 1115 cetr1 .............................................. 1117 chcr.................................................. 572 clkon............................................... 885 cmdr................................................. 871 cmdstrt.......................................... 872 cmdtyr ........................................... 889 cmtcfg ............................................ 681 cmtchnc.......................................... 690 cmtchnst........................................ 689
rev.1.00 dec. 13, 2005 page 1282 of 1286 rej09b0158-0100 cmtchnt ......................................... 689 cmtctl............................................ 684 cmtfrt ............................................ 684 cmtirqs .......................................... 688 cpuopm.......................................... 1217 crr0 ................................................ 1111 crr1 ................................................ 1111 csnbcr ............................................. 336 csnpcr.............................................. 347 csnwcr ............................................ 342 cstr .................................................. 875 ctocr............................................... 886 dar.................................................... 568 darb................................................. 569 dbk.................................................... 424 dbr...................................................... 42 dmacr ............................................. 900 dmaor ............................................. 581 dmars.............................................. 584 dr ...................................................... 898 dtoutr............................................ 897 expevt............................................... 99 fifoclr............................................ 899 fladr............................................. 1030 flbsycnt...................................... 1040 flbsytmr ..................................... 1039 flcmcdr ....................................... 1030 flcmdcr ....................................... 1028 flcmncr ....................................... 1026 fldatar........................................ 1033 fldtcntr ..................................... 1032 fldtfifo ....................................... 1041 flecfifo........................................ 1042 flintdmacr ................................ 1034 fltrcr ........................................... 1043 fpscr .......................................... 43, 137 fpul .................................................. 140 frqcr............................................... 619 gbr...................................................... 42 hacacr ........................................... 971 haccr............................................... 958 haccsar ......................................... 960 haccsdr ......................................... 962 hacpcml ......................................... 963 hacpcmr......................................... 965 hacrier........................................... 969 hacrsr ............................................ 970 hactier ........................................... 966 hactsr............................................. 967 icr...................................................... 255 int2a................................................. 277 int2b ................................................. 287 int2gpic........................................... 294 int2mskcr...................................... 285 int2mskr ........................................ 282 int2pri ............................................. 276 intcr ................................................ 877 intevt.............................................. 100 intmsk ............................................. 261 intmskclr ..................................... 266 intpri ............................................... 259 intreq.............................................. 260 intstr .............................................. 880 irmcr ............................................... 165 lda0 .................................................. 234 lda1 .................................................. 236 lsa0................................................... 230 lsa1................................................... 232 mach .................................................. 42 macl................................................... 42 mim.................................................... 412 mmc mode ........................................ 901 mmselr ........................................... 331 mmucr ............................................. 160 moder.............................................. 888 mstpcr............................................. 646 nmifcr ............................................. 271 opcr.................................................. 873 pacr................................................ 1063 padr................................................ 1081
rev.1.00 dec. 13, 2005 page 1283 of 1286 rej09b0158-0100 pascr ............................................... 164 pbcr................................................ 1064 pbdr................................................ 1081 pc ......................................................... 42 pccr................................................ 1066 pcdr................................................ 1082 pdcr................................................ 1067 pddr ............................................... 1082 pecr ................................................ 1069 pedr................................................ 1083 pepupr ........................................... 1087 pfcr ................................................ 1070 pfdr ................................................ 1084 pgcr................................................ 1072 pgdr ............................................... 1084 phcr................................................ 1074 phdr ............................................... 1085 phpupr ........................................... 1088 pjcr ................................................. 1075 pjdr................................................. 1085 pjpupr ............................................ 1089 pkcr................................................ 1077 pkdr ............................................... 1086 pkpupr ........................................... 1090 plcr ................................................ 1079 pldr................................................ 1086 pllcr................................................ 621 pmcr ............................................... 1080 pmdr............................................... 1087 pmpupr .......................................... 1091 pmselr........................................... 1094 ppupr1............................................ 1092 ppupr2............................................ 1093 pr ......................................................... 42 pteh .................................................. 157 ptel................................................... 158 qacr0 ............................................... 203 qacr1 ............................................... 204 r64cnt ............................................. 712 ramcr...................................... 205, 229 rcr1 .................................................. 721 rcr2 .................................................. 723 rcr3 .................................................. 726 rdayar............................................ 719 rdaycnt ......................................... 715 rhrar............................................... 718 rhrcnt ............................................ 713 rminar ............................................ 717 rmincnt .......................................... 713 rmonar........................................... 720 rmoncnt ........................................ 716 rsecar............................................. 717 rseccnt .......................................... 712 rspr................................................... 895 rsptyr ............................................. 890 rwkar.............................................. 718 rwkcnt ........................................... 714 ryrar............................................... 720 ryrcnt ............................................ 716 sar..................................................... 567 sarb .................................................. 568 scbrr................................................ 758 scfcr ................................................ 759 scfrdr ............................................. 742 scfsr ................................................ 751 scftdr ............................................. 743 sclsr ................................................ 767 scr..................................................... 416 screr................................................ 768 scrfdr ............................................. 763 scrsr ................................................ 742 scscr ................................................ 747 scsmr ............................................... 744 scsptr .............................................. 764 sctfdr ............................................. 762 sctsr ................................................ 743 sdbsr.............................................. 1143 sdint............................................... 1142 sdir ................................................. 1141 sdmr ................................................. 422
rev.1.00 dec. 13, 2005 page 1284 of 1286 rej09b0158-0100 sdr .................................................... 421 sgr ...................................................... 42 sicdar ............................................. 825 sictr................................................. 806 sifctr .............................................. 821 siier .................................................. 819 simdr ............................................... 802 sircr ................................................ 812 sirdar ............................................. 824 sirdr ................................................ 810 siscr................................................. 804 sistr ................................................. 813 sitcr................................................. 811 sitdar.............................................. 823 sitdr ................................................ 809 spc....................................................... 42 spcr .................................................. 852 sprbr................................................ 860 spscr ................................................ 857 spsr................................................... 854 sptbr................................................ 859 sr ......................................................... 40 ssicr................................................. 986 ssirdr .............................................. 997 ssisr ................................................. 992 ssitdr .............................................. 997 ssr....................................................... 42 str..................................................... 418 tbcr.................................................. 887 tbncr............................................... 894 tcnt.................................................. 665 tcor ................................................. 665 tcpr2 ................................................ 668 tcr ............................................ 570, 666 tcrb.................................................. 571 tocr ................................................. 662 tra ...................................................... 98 tstr .................................................. 663 ttb .................................................... 159 userimask ..................................... 273 vbr ...................................................... 42 relative prio rities.................................... 102 reset state ................................................. 49 rounding................................................. 141 round-robin mode .................................. 592 rtc power suppl y backup .................... 653 rxi ......................................................... 793 s sector access mode.............................. 1046 sequential br eak.................................... 1124 serial communication interface with fifo (scif).................................... 733 serial i/o with fifo (siof)................... 797 serial protocol interface (hspi) ............. 849 serial sound interface (ssi) module ...... 983 share status bit ........................................ 168 shift instructions ....................................... 64 sign-extended ........................................... 47 single virtual me mory mode................... 155 single-precision floating-point extended register matrix............................ 39 single-precision floating-point extended registers ..................................... 38 single-precision floating-point registers ... 38 single-precision floating-point vector registers..................................................... 38 sleep mode ............................................. 648 slot fpu disable exception..................... 121 slot illegal instruction exception............. 119 sram interface ...................................... 361 system control instructions....................... 66 system registers ........................................ 34 system registers re lated to fpu ................ 35 t t bit........................................................... 52 tap control .......................................... 1152
rev.1.00 dec. 13, 2005 page 1285 of 1286 rej09b0158-0100 tcnt count timing .............................. 671 time setting ........................................... 727 timer unit input capture function ....................... 673 timer unit (tmu).................................. 657 txi ......................................................... 793 types of exceptions ................................ 102 u unconditional trap .................................. 117 underflow............................................... 142 user break controller ............................ 1101 user break operation............................. 1121 user debugging interface...................... 1135 user mode................................................. 34 utlb...................................................... 167 utlb address array................................ 186 utlb data array ..................................... 187 v validity bit .............................................. 168 vector addresses ..................................... 102 virtual address space .............................. 149 vpn ........................................................ 167 w wait cycles between accesses ............... 393 watchdog timer and reset..................... 625 write-back instruction ............................ 238 write-through bit .................................... 169
rev.1.00 dec. 13, 2005 page 1286 of 1286 rej09b0158-0100
renesas 32-bit risc microcomputer hardware manual sh7780 publication date: rev.1.00, dec. 13, 2005 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2005. renesas technology corp. all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 205, azia center, no.133 yincheng rd (n), pudong district, shanghai 200120, china tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 5.0

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